radeon_video.c revision 01e04c3f 
1/**************************************************************************
2 *
3 * Copyright 2013 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include <unistd.h>
29
30#include "util/u_memory.h"
31#include "util/u_video.h"
32
33#include "vl/vl_defines.h"
34#include "vl/vl_video_buffer.h"
35
36#include "radeonsi/si_pipe.h"
37#include "radeon_video.h"
38#include "radeon_vce.h"
39
40/* generate an stream handle */
41unsigned si_vid_alloc_stream_handle()
42{
43	static unsigned counter = 0;
44	unsigned stream_handle = 0;
45	unsigned pid = getpid();
46	int i;
47
48	for (i = 0; i < 32; ++i)
49		stream_handle |= ((pid >> i) & 1) << (31 - i);
50
51	stream_handle ^= ++counter;
52	return stream_handle;
53}
54
55/* create a buffer in the winsys */
56bool si_vid_create_buffer(struct pipe_screen *screen, struct rvid_buffer *buffer,
57			  unsigned size, unsigned usage)
58{
59	memset(buffer, 0, sizeof(*buffer));
60	buffer->usage = usage;
61
62	/* Hardware buffer placement restrictions require the kernel to be
63	 * able to move buffers around individually, so request a
64	 * non-sub-allocated buffer.
65	 */
66	buffer->res = r600_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED,
67						       usage, size));
68
69	return buffer->res != NULL;
70}
71
72/* destroy a buffer */
73void si_vid_destroy_buffer(struct rvid_buffer *buffer)
74{
75	r600_resource_reference(&buffer->res, NULL);
76}
77
78/* reallocate a buffer, preserving its content */
79bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs,
80			  struct rvid_buffer *new_buf, unsigned new_size)
81{
82	struct si_screen *sscreen = (struct si_screen *)screen;
83	struct radeon_winsys* ws = sscreen->ws;
84	unsigned bytes = MIN2(new_buf->res->buf->size, new_size);
85	struct rvid_buffer old_buf = *new_buf;
86	void *src = NULL, *dst = NULL;
87
88	if (!si_vid_create_buffer(screen, new_buf, new_size, new_buf->usage))
89		goto error;
90
91	src = ws->buffer_map(old_buf.res->buf, cs, PIPE_TRANSFER_READ);
92	if (!src)
93		goto error;
94
95	dst = ws->buffer_map(new_buf->res->buf, cs, PIPE_TRANSFER_WRITE);
96	if (!dst)
97		goto error;
98
99	memcpy(dst, src, bytes);
100	if (new_size > bytes) {
101		new_size -= bytes;
102		dst += bytes;
103		memset(dst, 0, new_size);
104	}
105	ws->buffer_unmap(new_buf->res->buf);
106	ws->buffer_unmap(old_buf.res->buf);
107	si_vid_destroy_buffer(&old_buf);
108	return true;
109
110error:
111	if (src)
112		ws->buffer_unmap(old_buf.res->buf);
113	si_vid_destroy_buffer(new_buf);
114	*new_buf = old_buf;
115	return false;
116}
117
118/* clear the buffer with zeros */
119void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
120{
121	struct si_context *sctx = (struct si_context*)context;
122
123	si_sdma_clear_buffer(sctx, &buffer->res->b.b, 0, buffer->res->buf->size, 0);
124	context->flush(context, NULL, 0);
125}
126
127/**
128 * join surfaces into the same buffer with identical tiling params
129 * sumup their sizes and replace the backend buffers with a single bo
130 */
131void si_vid_join_surfaces(struct si_context *sctx,
132			  struct pb_buffer** buffers[VL_NUM_COMPONENTS],
133			  struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
134{
135	struct radeon_winsys *ws = sctx->ws;;
136	unsigned best_tiling, best_wh, off;
137	unsigned size, alignment;
138	struct pb_buffer *pb;
139	unsigned i, j;
140
141	for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
142		unsigned wh;
143
144		if (!surfaces[i])
145			continue;
146
147		if (sctx->chip_class < GFX9) {
148			/* choose the smallest bank w/h for now */
149			wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
150			if (wh < best_wh) {
151				best_wh = wh;
152				best_tiling = i;
153			}
154		}
155	}
156
157	for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) {
158		if (!surfaces[i])
159			continue;
160
161		/* adjust the texture layer offsets */
162		off = align(off, surfaces[i]->surf_alignment);
163
164		if (sctx->chip_class < GFX9) {
165			/* copy the tiling parameters */
166			surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
167			surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
168			surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
169			surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
170
171			for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
172				surfaces[i]->u.legacy.level[j].offset += off;
173		} else {
174			surfaces[i]->u.gfx9.surf_offset += off;
175			for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j)
176				surfaces[i]->u.gfx9.offset[j] += off;
177		}
178
179		off += surfaces[i]->surf_size;
180	}
181
182	for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) {
183		if (!buffers[i] || !*buffers[i])
184			continue;
185
186		size = align(size, (*buffers[i])->alignment);
187		size += (*buffers[i])->size;
188		alignment = MAX2(alignment, (*buffers[i])->alignment * 1);
189	}
190
191	if (!size)
192		return;
193
194	/* TODO: 2D tiling workaround */
195	alignment *= 2;
196
197	pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM,
198			       RADEON_FLAG_GTT_WC);
199	if (!pb)
200		return;
201
202	for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
203		if (!buffers[i] || !*buffers[i])
204			continue;
205
206		pb_reference(buffers[i], pb);
207	}
208
209	pb_reference(&pb, NULL);
210}
211