si_blit.c revision 7ec681f3
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * Copyright 2015 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * on the rights to use, copy, modify, merge, publish, distribute, sub 10 * license, and/or sell copies of the Software, and to permit persons to whom 11 * the Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 23 * USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#include "si_compute.h" 27#include "si_pipe.h" 28#include "util/format/u_format.h" 29#include "util/u_log.h" 30#include "util/u_surface.h" 31 32enum 33{ 34 SI_COPY = 35 SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES | SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND, 36 37 SI_BLIT = SI_SAVE_FRAMEBUFFER | SI_SAVE_TEXTURES | SI_SAVE_FRAGMENT_STATE, 38 39 SI_DECOMPRESS = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE | SI_DISABLE_RENDER_COND, 40 41 SI_COLOR_RESOLVE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE 42}; 43 44void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op) 45{ 46 util_blitter_save_vertex_shader(sctx->blitter, sctx->shader.vs.cso); 47 util_blitter_save_tessctrl_shader(sctx->blitter, sctx->shader.tcs.cso); 48 util_blitter_save_tesseval_shader(sctx->blitter, sctx->shader.tes.cso); 49 util_blitter_save_geometry_shader(sctx->blitter, sctx->shader.gs.cso); 50 util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets, 51 (struct pipe_stream_output_target **)sctx->streamout.targets); 52 util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer); 53 54 if (op & SI_SAVE_FRAGMENT_STATE) { 55 util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend); 56 util_blitter_save_depth_stencil_alpha(sctx->blitter, sctx->queued.named.dsa); 57 util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state); 58 util_blitter_save_fragment_shader(sctx->blitter, sctx->shader.ps.cso); 59 util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask); 60 util_blitter_save_scissor(sctx->blitter, &sctx->scissors[0]); 61 util_blitter_save_window_rectangles(sctx->blitter, sctx->window_rectangles_include, 62 sctx->num_window_rectangles, sctx->window_rectangles); 63 } 64 65 if (op & SI_SAVE_FRAMEBUFFER) 66 util_blitter_save_framebuffer(sctx->blitter, &sctx->framebuffer.state); 67 68 if (op & SI_SAVE_TEXTURES) { 69 util_blitter_save_fragment_sampler_states( 70 sctx->blitter, 2, (void **)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states); 71 72 util_blitter_save_fragment_sampler_views(sctx->blitter, 2, 73 sctx->samplers[PIPE_SHADER_FRAGMENT].views); 74 } 75 76 if (op & SI_DISABLE_RENDER_COND) 77 sctx->render_cond_enabled = false; 78 79 if (sctx->screen->dpbb_allowed) { 80 sctx->dpbb_force_off = true; 81 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state); 82 } 83 84 sctx->blitter_running = true; 85} 86 87void si_blitter_end(struct si_context *sctx) 88{ 89 sctx->blitter_running = false; 90 91 if (sctx->screen->dpbb_allowed) { 92 sctx->dpbb_force_off = false; 93 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state); 94 } 95 96 sctx->render_cond_enabled = sctx->render_cond; 97 98 /* Restore shader pointers because the VS blit shader changed all 99 * non-global VS user SGPRs. */ 100 sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX); 101 102 unsigned num_vbos_in_user_sgprs = si_num_vbos_in_user_sgprs(sctx->screen); 103 sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL && 104 sctx->num_vertex_elements > 105 num_vbos_in_user_sgprs; 106 sctx->vertex_buffer_user_sgprs_dirty = sctx->num_vertex_elements > 0 && 107 num_vbos_in_user_sgprs; 108 si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_pointers); 109} 110 111static unsigned u_max_sample(struct pipe_resource *r) 112{ 113 return r->nr_samples ? r->nr_samples - 1 : 0; 114} 115 116static unsigned si_blit_dbcb_copy(struct si_context *sctx, struct si_texture *src, 117 struct si_texture *dst, unsigned planes, unsigned level_mask, 118 unsigned first_layer, unsigned last_layer, unsigned first_sample, 119 unsigned last_sample) 120{ 121 struct pipe_surface surf_tmpl = {{0}}; 122 unsigned layer, sample, checked_last_layer, max_layer; 123 unsigned fully_copied_levels = 0; 124 125 if (planes & PIPE_MASK_Z) 126 sctx->dbcb_depth_copy_enabled = true; 127 if (planes & PIPE_MASK_S) 128 sctx->dbcb_stencil_copy_enabled = true; 129 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 130 131 assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled); 132 133 sctx->decompression_enabled = true; 134 135 while (level_mask) { 136 unsigned level = u_bit_scan(&level_mask); 137 138 /* The smaller the mipmap level, the less layers there are 139 * as far as 3D textures are concerned. */ 140 max_layer = util_max_layer(&src->buffer.b.b, level); 141 checked_last_layer = MIN2(last_layer, max_layer); 142 143 surf_tmpl.u.tex.level = level; 144 145 for (layer = first_layer; layer <= checked_last_layer; layer++) { 146 struct pipe_surface *zsurf, *cbsurf; 147 148 surf_tmpl.format = src->buffer.b.b.format; 149 surf_tmpl.u.tex.first_layer = layer; 150 surf_tmpl.u.tex.last_layer = layer; 151 152 zsurf = sctx->b.create_surface(&sctx->b, &src->buffer.b.b, &surf_tmpl); 153 154 surf_tmpl.format = dst->buffer.b.b.format; 155 cbsurf = sctx->b.create_surface(&sctx->b, &dst->buffer.b.b, &surf_tmpl); 156 157 for (sample = first_sample; sample <= last_sample; sample++) { 158 if (sample != sctx->dbcb_copy_sample) { 159 sctx->dbcb_copy_sample = sample; 160 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 161 } 162 163 si_blitter_begin(sctx, SI_DECOMPRESS); 164 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample, 165 sctx->custom_dsa_flush, 1.0f); 166 si_blitter_end(sctx); 167 } 168 169 pipe_surface_reference(&zsurf, NULL); 170 pipe_surface_reference(&cbsurf, NULL); 171 } 172 173 if (first_layer == 0 && last_layer >= max_layer && first_sample == 0 && 174 last_sample >= u_max_sample(&src->buffer.b.b)) 175 fully_copied_levels |= 1u << level; 176 } 177 178 sctx->decompression_enabled = false; 179 sctx->dbcb_depth_copy_enabled = false; 180 sctx->dbcb_stencil_copy_enabled = false; 181 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 182 183 return fully_copied_levels; 184} 185 186/* Helper function for si_blit_decompress_zs_in_place. 187 */ 188static void si_blit_decompress_zs_planes_in_place(struct si_context *sctx, 189 struct si_texture *texture, unsigned planes, 190 unsigned level_mask, unsigned first_layer, 191 unsigned last_layer) 192{ 193 struct pipe_surface *zsurf, surf_tmpl = {{0}}; 194 unsigned layer, max_layer, checked_last_layer; 195 unsigned fully_decompressed_mask = 0; 196 197 if (!level_mask) 198 return; 199 200 if (planes & PIPE_MASK_S) 201 sctx->db_flush_stencil_inplace = true; 202 if (planes & PIPE_MASK_Z) 203 sctx->db_flush_depth_inplace = true; 204 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 205 206 surf_tmpl.format = texture->buffer.b.b.format; 207 208 sctx->decompression_enabled = true; 209 210 while (level_mask) { 211 unsigned level = u_bit_scan(&level_mask); 212 213 surf_tmpl.u.tex.level = level; 214 215 /* The smaller the mipmap level, the less layers there are 216 * as far as 3D textures are concerned. */ 217 max_layer = util_max_layer(&texture->buffer.b.b, level); 218 checked_last_layer = MIN2(last_layer, max_layer); 219 220 for (layer = first_layer; layer <= checked_last_layer; layer++) { 221 surf_tmpl.u.tex.first_layer = layer; 222 surf_tmpl.u.tex.last_layer = layer; 223 224 zsurf = sctx->b.create_surface(&sctx->b, &texture->buffer.b.b, &surf_tmpl); 225 226 si_blitter_begin(sctx, SI_DECOMPRESS); 227 util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0, sctx->custom_dsa_flush, 228 1.0f); 229 si_blitter_end(sctx); 230 231 pipe_surface_reference(&zsurf, NULL); 232 } 233 234 /* The texture will always be dirty if some layers aren't flushed. 235 * I don't think this case occurs often though. */ 236 if (first_layer == 0 && last_layer >= max_layer) { 237 fully_decompressed_mask |= 1u << level; 238 } 239 } 240 241 if (planes & PIPE_MASK_Z) 242 texture->dirty_level_mask &= ~fully_decompressed_mask; 243 if (planes & PIPE_MASK_S) 244 texture->stencil_dirty_level_mask &= ~fully_decompressed_mask; 245 246 sctx->decompression_enabled = false; 247 sctx->db_flush_depth_inplace = false; 248 sctx->db_flush_stencil_inplace = false; 249 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state); 250} 251 252/* Helper function of si_flush_depth_texture: decompress the given levels 253 * of Z and/or S planes in place. 254 */ 255static void si_blit_decompress_zs_in_place(struct si_context *sctx, struct si_texture *texture, 256 unsigned levels_z, unsigned levels_s, 257 unsigned first_layer, unsigned last_layer) 258{ 259 unsigned both = levels_z & levels_s; 260 261 /* First, do combined Z & S decompresses for levels that need it. */ 262 if (both) { 263 si_blit_decompress_zs_planes_in_place(sctx, texture, PIPE_MASK_Z | PIPE_MASK_S, both, 264 first_layer, last_layer); 265 levels_z &= ~both; 266 levels_s &= ~both; 267 } 268 269 /* Now do separate Z and S decompresses. */ 270 if (levels_z) { 271 si_blit_decompress_zs_planes_in_place(sctx, texture, PIPE_MASK_Z, levels_z, first_layer, 272 last_layer); 273 } 274 275 if (levels_s) { 276 si_blit_decompress_zs_planes_in_place(sctx, texture, PIPE_MASK_S, levels_s, first_layer, 277 last_layer); 278 } 279} 280 281static void si_decompress_depth(struct si_context *sctx, struct si_texture *tex, 282 unsigned required_planes, unsigned first_level, unsigned last_level, 283 unsigned first_layer, unsigned last_layer) 284{ 285 unsigned inplace_planes = 0; 286 unsigned copy_planes = 0; 287 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1); 288 unsigned levels_z = 0; 289 unsigned levels_s = 0; 290 291 if (required_planes & PIPE_MASK_Z) { 292 levels_z = level_mask & tex->dirty_level_mask; 293 294 if (levels_z) { 295 if (si_can_sample_zs(tex, false)) 296 inplace_planes |= PIPE_MASK_Z; 297 else 298 copy_planes |= PIPE_MASK_Z; 299 } 300 } 301 if (required_planes & PIPE_MASK_S) { 302 levels_s = level_mask & tex->stencil_dirty_level_mask; 303 304 if (levels_s) { 305 if (si_can_sample_zs(tex, true)) 306 inplace_planes |= PIPE_MASK_S; 307 else 308 copy_planes |= PIPE_MASK_S; 309 } 310 } 311 312 if (unlikely(sctx->log)) 313 u_log_printf(sctx->log, 314 "\n------------------------------------------------\n" 315 "Decompress Depth (levels %u - %u, levels Z: 0x%x S: 0x%x)\n\n", 316 first_level, last_level, levels_z, levels_s); 317 318 /* We may have to allocate the flushed texture here when called from 319 * si_decompress_subresource. 320 */ 321 if (copy_planes && 322 (tex->flushed_depth_texture || si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b))) { 323 struct si_texture *dst = tex->flushed_depth_texture; 324 unsigned fully_copied_levels; 325 unsigned levels = 0; 326 327 assert(tex->flushed_depth_texture); 328 329 if (util_format_is_depth_and_stencil(dst->buffer.b.b.format)) 330 copy_planes = PIPE_MASK_Z | PIPE_MASK_S; 331 332 if (copy_planes & PIPE_MASK_Z) { 333 levels |= levels_z; 334 levels_z = 0; 335 } 336 if (copy_planes & PIPE_MASK_S) { 337 levels |= levels_s; 338 levels_s = 0; 339 } 340 341 fully_copied_levels = si_blit_dbcb_copy(sctx, tex, dst, copy_planes, levels, first_layer, 342 last_layer, 0, u_max_sample(&tex->buffer.b.b)); 343 344 if (copy_planes & PIPE_MASK_Z) 345 tex->dirty_level_mask &= ~fully_copied_levels; 346 if (copy_planes & PIPE_MASK_S) 347 tex->stencil_dirty_level_mask &= ~fully_copied_levels; 348 } 349 350 if (inplace_planes) { 351 bool has_htile = si_htile_enabled(tex, first_level, inplace_planes); 352 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level, inplace_planes); 353 354 /* Don't decompress if there is no HTILE or when HTILE is 355 * TC-compatible. */ 356 if (has_htile && !tc_compat_htile) { 357 si_blit_decompress_zs_in_place(sctx, tex, levels_z, levels_s, first_layer, last_layer); 358 } else { 359 /* This is only a cache flush. 360 * 361 * Only clear the mask that we are flushing, because 362 * si_make_DB_shader_coherent() treats different levels 363 * and depth and stencil differently. 364 */ 365 if (inplace_planes & PIPE_MASK_Z) 366 tex->dirty_level_mask &= ~levels_z; 367 if (inplace_planes & PIPE_MASK_S) 368 tex->stencil_dirty_level_mask &= ~levels_s; 369 } 370 371 /* We just had to completely decompress Z/S for texturing. Enable 372 * TC-compatible HTILE on the next clear, so that the decompression 373 * doesn't have to be done for this texture ever again. 374 * 375 * TC-compatible HTILE might slightly reduce Z/S performance, but 376 * the decompression is much worse. 377 */ 378 if (has_htile && !tc_compat_htile && 379 /* We can only transition the whole buffer in one clear, so no mipmapping: */ 380 tex->buffer.b.b.last_level == 0 && 381 tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE && 382 (inplace_planes & PIPE_MASK_Z || !tex->htile_stencil_disabled)) 383 tex->enable_tc_compatible_htile_next_clear = true; 384 385 /* Only in-place decompression needs to flush DB caches, or 386 * when we don't decompress but TC-compatible planes are dirty. 387 */ 388 si_make_DB_shader_coherent(sctx, tex->buffer.b.b.nr_samples, inplace_planes & PIPE_MASK_S, 389 tc_compat_htile); 390 } 391 /* set_framebuffer_state takes care of coherency for single-sample. 392 * The DB->CB copy uses CB for the final writes. 393 */ 394 if (copy_planes && tex->buffer.b.b.nr_samples > 1) 395 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples, false, true /* no DCC */); 396} 397 398static bool si_decompress_sampler_depth_textures(struct si_context *sctx, 399 struct si_samplers *textures) 400{ 401 unsigned i; 402 unsigned mask = textures->needs_depth_decompress_mask; 403 bool need_flush = false; 404 405 while (mask) { 406 struct pipe_sampler_view *view; 407 struct si_sampler_view *sview; 408 struct si_texture *tex; 409 410 i = u_bit_scan(&mask); 411 412 view = textures->views[i]; 413 assert(view); 414 sview = (struct si_sampler_view *)view; 415 416 tex = (struct si_texture *)view->texture; 417 assert(tex->db_compatible); 418 419 si_decompress_depth(sctx, tex, sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z, 420 view->u.tex.first_level, view->u.tex.last_level, 0, 421 util_max_layer(&tex->buffer.b.b, view->u.tex.first_level)); 422 423 if (tex->need_flush_after_depth_decompression) { 424 need_flush = true; 425 tex->need_flush_after_depth_decompression = false; 426 } 427 } 428 429 return need_flush; 430} 431 432static void si_blit_decompress_color(struct si_context *sctx, struct si_texture *tex, 433 unsigned first_level, unsigned last_level, 434 unsigned first_layer, unsigned last_layer, 435 bool need_dcc_decompress, bool need_fmask_expand) 436{ 437 void *custom_blend; 438 unsigned layer, checked_last_layer, max_layer; 439 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1); 440 441 if (!need_dcc_decompress) 442 level_mask &= tex->dirty_level_mask; 443 if (!level_mask) 444 goto expand_fmask; 445 446 if (unlikely(sctx->log)) 447 u_log_printf(sctx->log, 448 "\n------------------------------------------------\n" 449 "Decompress Color (levels %u - %u, mask 0x%x)\n\n", 450 first_level, last_level, level_mask); 451 452 if (need_dcc_decompress) { 453 assert(sctx->chip_class == GFX8 || tex->buffer.b.b.nr_storage_samples >= 2); 454 custom_blend = sctx->custom_blend_dcc_decompress; 455 456 assert(vi_dcc_enabled(tex, first_level)); 457 458 /* disable levels without DCC */ 459 for (int i = first_level; i <= last_level; i++) { 460 if (!vi_dcc_enabled(tex, i)) 461 level_mask &= ~(1 << i); 462 } 463 } else if (tex->surface.fmask_size) { 464 custom_blend = sctx->custom_blend_fmask_decompress; 465 } else { 466 custom_blend = sctx->custom_blend_eliminate_fastclear; 467 } 468 469 sctx->decompression_enabled = true; 470 471 while (level_mask) { 472 unsigned level = u_bit_scan(&level_mask); 473 474 /* The smaller the mipmap level, the less layers there are 475 * as far as 3D textures are concerned. */ 476 max_layer = util_max_layer(&tex->buffer.b.b, level); 477 checked_last_layer = MIN2(last_layer, max_layer); 478 479 for (layer = first_layer; layer <= checked_last_layer; layer++) { 480 struct pipe_surface *cbsurf, surf_tmpl; 481 482 surf_tmpl.format = tex->buffer.b.b.format; 483 surf_tmpl.u.tex.level = level; 484 surf_tmpl.u.tex.first_layer = layer; 485 surf_tmpl.u.tex.last_layer = layer; 486 cbsurf = sctx->b.create_surface(&sctx->b, &tex->buffer.b.b, &surf_tmpl); 487 488 /* Required before and after FMASK and DCC_DECOMPRESS. */ 489 if (custom_blend == sctx->custom_blend_fmask_decompress || 490 custom_blend == sctx->custom_blend_dcc_decompress) 491 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB; 492 493 si_blitter_begin(sctx, SI_DECOMPRESS); 494 util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend); 495 si_blitter_end(sctx); 496 497 if (custom_blend == sctx->custom_blend_fmask_decompress || 498 custom_blend == sctx->custom_blend_dcc_decompress) 499 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB; 500 501 /* When running FMASK decompresion with DCC, we need to run the "eliminate fast clear" pass 502 * separately because FMASK decompression doesn't eliminate DCC fast clear. This makes 503 * render->texture transitions more expensive. It can be disabled by 504 * allow_dcc_msaa_clear_to_reg_for_bpp. 505 * 506 * TODO: When we get here, change the compression to TC-compatible on the next clear 507 * to disable both the FMASK decompression and fast clear elimination passes. 508 */ 509 if (sctx->screen->allow_dcc_msaa_clear_to_reg_for_bpp[util_logbase2(tex->surface.bpe)] && 510 custom_blend == sctx->custom_blend_fmask_decompress && 511 vi_dcc_enabled(tex, level)) { 512 si_blitter_begin(sctx, SI_DECOMPRESS); 513 util_blitter_custom_color(sctx->blitter, cbsurf, sctx->custom_blend_eliminate_fastclear); 514 si_blitter_end(sctx); 515 } 516 517 pipe_surface_reference(&cbsurf, NULL); 518 } 519 520 /* The texture will always be dirty if some layers aren't flushed. 521 * I don't think this case occurs often though. */ 522 if (first_layer == 0 && last_layer >= max_layer) { 523 tex->dirty_level_mask &= ~(1 << level); 524 } 525 } 526 527 sctx->decompression_enabled = false; 528 si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples, vi_dcc_enabled(tex, first_level), 529 tex->surface.u.gfx9.color.dcc.pipe_aligned); 530 531expand_fmask: 532 if (need_fmask_expand && tex->surface.fmask_offset && !tex->fmask_is_identity) { 533 si_compute_expand_fmask(&sctx->b, &tex->buffer.b.b); 534 tex->fmask_is_identity = true; 535 } 536} 537 538static void si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex, 539 unsigned first_level, unsigned last_level, 540 bool need_fmask_expand) 541{ 542 /* CMASK or DCC can be discarded and we can still end up here. */ 543 if (!tex->cmask_buffer && !tex->surface.fmask_size && 544 !vi_dcc_enabled(tex, first_level)) 545 return; 546 547 si_blit_decompress_color(sctx, tex, first_level, last_level, 0, 548 util_max_layer(&tex->buffer.b.b, first_level), false, 549 need_fmask_expand); 550} 551 552static void si_decompress_sampler_color_textures(struct si_context *sctx, 553 struct si_samplers *textures) 554{ 555 unsigned i; 556 unsigned mask = textures->needs_color_decompress_mask; 557 558 while (mask) { 559 struct pipe_sampler_view *view; 560 struct si_texture *tex; 561 562 i = u_bit_scan(&mask); 563 564 view = textures->views[i]; 565 assert(view); 566 567 tex = (struct si_texture *)view->texture; 568 569 si_decompress_color_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level, 570 false); 571 } 572} 573 574static void si_decompress_image_color_textures(struct si_context *sctx, struct si_images *images) 575{ 576 unsigned i; 577 unsigned mask = images->needs_color_decompress_mask; 578 579 while (mask) { 580 const struct pipe_image_view *view; 581 struct si_texture *tex; 582 583 i = u_bit_scan(&mask); 584 585 view = &images->views[i]; 586 assert(view->resource->target != PIPE_BUFFER); 587 588 tex = (struct si_texture *)view->resource; 589 590 si_decompress_color_texture(sctx, tex, view->u.tex.level, view->u.tex.level, 591 view->access & PIPE_IMAGE_ACCESS_WRITE); 592 } 593} 594 595static void si_check_render_feedback_texture(struct si_context *sctx, struct si_texture *tex, 596 unsigned first_level, unsigned last_level, 597 unsigned first_layer, unsigned last_layer) 598{ 599 bool render_feedback = false; 600 601 if (!vi_dcc_enabled(tex, first_level)) 602 return; 603 604 for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) { 605 struct si_surface *surf; 606 607 if (!sctx->framebuffer.state.cbufs[j]) 608 continue; 609 610 surf = (struct si_surface *)sctx->framebuffer.state.cbufs[j]; 611 612 if (tex == (struct si_texture *)surf->base.texture && surf->base.u.tex.level >= first_level && 613 surf->base.u.tex.level <= last_level && surf->base.u.tex.first_layer <= last_layer && 614 surf->base.u.tex.last_layer >= first_layer) { 615 render_feedback = true; 616 break; 617 } 618 } 619 620 if (render_feedback) 621 si_texture_disable_dcc(sctx, tex); 622} 623 624static void si_check_render_feedback_textures(struct si_context *sctx, struct si_samplers *textures, 625 uint32_t in_use_mask) 626{ 627 uint32_t mask = textures->enabled_mask & in_use_mask; 628 629 while (mask) { 630 const struct pipe_sampler_view *view; 631 struct si_texture *tex; 632 633 unsigned i = u_bit_scan(&mask); 634 635 view = textures->views[i]; 636 if (view->texture->target == PIPE_BUFFER) 637 continue; 638 639 tex = (struct si_texture *)view->texture; 640 641 si_check_render_feedback_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level, 642 view->u.tex.first_layer, view->u.tex.last_layer); 643 } 644} 645 646static void si_check_render_feedback_images(struct si_context *sctx, struct si_images *images, 647 uint32_t in_use_mask) 648{ 649 uint32_t mask = images->enabled_mask & in_use_mask; 650 651 while (mask) { 652 const struct pipe_image_view *view; 653 struct si_texture *tex; 654 655 unsigned i = u_bit_scan(&mask); 656 657 view = &images->views[i]; 658 if (view->resource->target == PIPE_BUFFER) 659 continue; 660 661 tex = (struct si_texture *)view->resource; 662 663 si_check_render_feedback_texture(sctx, tex, view->u.tex.level, view->u.tex.level, 664 view->u.tex.first_layer, view->u.tex.last_layer); 665 } 666} 667 668static void si_check_render_feedback_resident_textures(struct si_context *sctx) 669{ 670 util_dynarray_foreach (&sctx->resident_tex_handles, struct si_texture_handle *, tex_handle) { 671 struct pipe_sampler_view *view; 672 struct si_texture *tex; 673 674 view = (*tex_handle)->view; 675 if (view->texture->target == PIPE_BUFFER) 676 continue; 677 678 tex = (struct si_texture *)view->texture; 679 680 si_check_render_feedback_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level, 681 view->u.tex.first_layer, view->u.tex.last_layer); 682 } 683} 684 685static void si_check_render_feedback_resident_images(struct si_context *sctx) 686{ 687 util_dynarray_foreach (&sctx->resident_img_handles, struct si_image_handle *, img_handle) { 688 struct pipe_image_view *view; 689 struct si_texture *tex; 690 691 view = &(*img_handle)->view; 692 if (view->resource->target == PIPE_BUFFER) 693 continue; 694 695 tex = (struct si_texture *)view->resource; 696 697 si_check_render_feedback_texture(sctx, tex, view->u.tex.level, view->u.tex.level, 698 view->u.tex.first_layer, view->u.tex.last_layer); 699 } 700} 701 702static void si_check_render_feedback(struct si_context *sctx) 703{ 704 if (!sctx->need_check_render_feedback) 705 return; 706 707 /* There is no render feedback if color writes are disabled. 708 * (e.g. a pixel shader with image stores) 709 */ 710 if (!si_get_total_colormask(sctx)) 711 return; 712 713 for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; ++i) { 714 if (!sctx->shaders[i].cso) 715 continue; 716 717 struct si_shader_info *info = &sctx->shaders[i].cso->info; 718 si_check_render_feedback_images(sctx, &sctx->images[i], 719 u_bit_consecutive(0, info->base.num_images)); 720 si_check_render_feedback_textures(sctx, &sctx->samplers[i], 721 info->base.textures_used[0]); 722 } 723 724 si_check_render_feedback_resident_images(sctx); 725 si_check_render_feedback_resident_textures(sctx); 726 727 sctx->need_check_render_feedback = false; 728} 729 730static void si_decompress_resident_textures(struct si_context *sctx) 731{ 732 util_dynarray_foreach (&sctx->resident_tex_needs_color_decompress, struct si_texture_handle *, 733 tex_handle) { 734 struct pipe_sampler_view *view = (*tex_handle)->view; 735 struct si_texture *tex = (struct si_texture *)view->texture; 736 737 si_decompress_color_texture(sctx, tex, view->u.tex.first_level, view->u.tex.last_level, 738 false); 739 } 740 741 util_dynarray_foreach (&sctx->resident_tex_needs_depth_decompress, struct si_texture_handle *, 742 tex_handle) { 743 struct pipe_sampler_view *view = (*tex_handle)->view; 744 struct si_sampler_view *sview = (struct si_sampler_view *)view; 745 struct si_texture *tex = (struct si_texture *)view->texture; 746 747 si_decompress_depth(sctx, tex, sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z, 748 view->u.tex.first_level, view->u.tex.last_level, 0, 749 util_max_layer(&tex->buffer.b.b, view->u.tex.first_level)); 750 } 751} 752 753static void si_decompress_resident_images(struct si_context *sctx) 754{ 755 util_dynarray_foreach (&sctx->resident_img_needs_color_decompress, struct si_image_handle *, 756 img_handle) { 757 struct pipe_image_view *view = &(*img_handle)->view; 758 struct si_texture *tex = (struct si_texture *)view->resource; 759 760 si_decompress_color_texture(sctx, tex, view->u.tex.level, view->u.tex.level, 761 view->access & PIPE_IMAGE_ACCESS_WRITE); 762 } 763} 764 765void si_decompress_textures(struct si_context *sctx, unsigned shader_mask) 766{ 767 unsigned compressed_colortex_counter, mask; 768 bool need_flush = false; 769 770 if (sctx->blitter_running) 771 return; 772 773 /* Update the compressed_colortex_mask if necessary. */ 774 compressed_colortex_counter = p_atomic_read(&sctx->screen->compressed_colortex_counter); 775 if (compressed_colortex_counter != sctx->last_compressed_colortex_counter) { 776 sctx->last_compressed_colortex_counter = compressed_colortex_counter; 777 si_update_needs_color_decompress_masks(sctx); 778 } 779 780 /* Decompress color & depth textures if needed. */ 781 mask = sctx->shader_needs_decompress_mask & shader_mask; 782 while (mask) { 783 unsigned i = u_bit_scan(&mask); 784 785 if (sctx->samplers[i].needs_depth_decompress_mask) { 786 need_flush |= si_decompress_sampler_depth_textures(sctx, &sctx->samplers[i]); 787 } 788 if (sctx->samplers[i].needs_color_decompress_mask) { 789 si_decompress_sampler_color_textures(sctx, &sctx->samplers[i]); 790 } 791 if (sctx->images[i].needs_color_decompress_mask) { 792 si_decompress_image_color_textures(sctx, &sctx->images[i]); 793 } 794 } 795 796 if (sctx->chip_class == GFX10_3 && need_flush) { 797 /* This fixes a corruption with the following sequence: 798 * - fast clear depth 799 * - decompress depth 800 * - draw 801 * (see https://gitlab.freedesktop.org/drm/amd/-/issues/1810#note_1170171) 802 */ 803 sctx->b.flush(&sctx->b, NULL, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW); 804 } 805 806 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) { 807 if (sctx->uses_bindless_samplers) 808 si_decompress_resident_textures(sctx); 809 if (sctx->uses_bindless_images) 810 si_decompress_resident_images(sctx); 811 812 if (sctx->ps_uses_fbfetch) { 813 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0]; 814 si_decompress_color_texture(sctx, (struct si_texture *)cb0->texture, 815 cb0->u.tex.first_layer, cb0->u.tex.last_layer, false); 816 } 817 818 si_check_render_feedback(sctx); 819 } else if (shader_mask & (1 << PIPE_SHADER_COMPUTE)) { 820 if (sctx->cs_shader_state.program->sel.info.uses_bindless_samplers) 821 si_decompress_resident_textures(sctx); 822 if (sctx->cs_shader_state.program->sel.info.uses_bindless_images) 823 si_decompress_resident_images(sctx); 824 } 825} 826 827/* Helper for decompressing a portion of a color or depth resource before 828 * blitting if any decompression is needed. 829 * The driver doesn't decompress resources automatically while u_blitter is 830 * rendering. */ 831void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes, 832 unsigned level, unsigned first_layer, unsigned last_layer) 833{ 834 struct si_context *sctx = (struct si_context *)ctx; 835 struct si_texture *stex = (struct si_texture *)tex; 836 837 if (stex->db_compatible) { 838 planes &= PIPE_MASK_Z | PIPE_MASK_S; 839 840 if (!stex->surface.has_stencil) 841 planes &= ~PIPE_MASK_S; 842 843 /* If we've rendered into the framebuffer and it's a blitting 844 * source, make sure the decompression pass is invoked 845 * by dirtying the framebuffer. 846 */ 847 if (sctx->framebuffer.state.zsbuf && sctx->framebuffer.state.zsbuf->u.tex.level == level && 848 sctx->framebuffer.state.zsbuf->texture == tex) 849 si_update_fb_dirtiness_after_rendering(sctx); 850 851 si_decompress_depth(sctx, stex, planes, level, level, first_layer, last_layer); 852 } else if (stex->surface.fmask_size || stex->cmask_buffer || 853 vi_dcc_enabled(stex, level)) { 854 /* If we've rendered into the framebuffer and it's a blitting 855 * source, make sure the decompression pass is invoked 856 * by dirtying the framebuffer. 857 */ 858 for (unsigned i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) { 859 if (sctx->framebuffer.state.cbufs[i] && 860 sctx->framebuffer.state.cbufs[i]->u.tex.level == level && 861 sctx->framebuffer.state.cbufs[i]->texture == tex) { 862 si_update_fb_dirtiness_after_rendering(sctx); 863 break; 864 } 865 } 866 867 si_blit_decompress_color(sctx, stex, level, level, first_layer, last_layer, false, false); 868 } 869} 870 871struct texture_orig_info { 872 unsigned format; 873 unsigned width0; 874 unsigned height0; 875 unsigned npix_x; 876 unsigned npix_y; 877 unsigned npix0_x; 878 unsigned npix0_y; 879}; 880 881static void si_use_compute_copy_for_float_formats(struct si_context *sctx, 882 struct pipe_resource *texture, 883 unsigned level) { 884 struct si_texture *tex = (struct si_texture *)texture; 885 886 /* If we are uploading into FP16 or R11G11B10_FLOAT via a blit, CB clobbers NaNs, 887 * so in order to preserve them exactly, we have to use the compute blit. 888 * The compute blit is used only when the destination doesn't have DCC, so 889 * disable it here, which is kinda a hack. 890 * If we are uploading into 32-bit floats with DCC via a blit, NaNs will also get 891 * lost so we need to disable DCC as well. 892 * 893 * This makes KHR-GL45.texture_view.view_classes pass on gfx9. 894 */ 895 if (vi_dcc_enabled(tex, level) && 896 util_format_is_float(texture->format) && 897 sctx->chip_class < GFX10) { 898 si_texture_disable_dcc(sctx, tex); 899 } 900} 901 902void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst, 903 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz, 904 struct pipe_resource *src, unsigned src_level, 905 const struct pipe_box *src_box) 906{ 907 struct si_context *sctx = (struct si_context *)ctx; 908 struct si_texture *ssrc = (struct si_texture *)src; 909 struct si_texture *sdst = (struct si_texture *)dst; 910 struct pipe_surface *dst_view, dst_templ; 911 struct pipe_sampler_view src_templ, *src_view; 912 unsigned dst_width, dst_height, src_width0, src_height0; 913 unsigned dst_width0, dst_height0, src_force_level = 0; 914 struct pipe_box sbox, dstbox; 915 916 /* Handle buffers first. */ 917 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { 918 si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, SI_OP_SYNC_BEFORE_AFTER); 919 return; 920 } 921 922 si_use_compute_copy_for_float_formats(sctx, dst, dst_level); 923 924 if (!util_format_is_compressed(src->format) && !util_format_is_compressed(dst->format) && 925 !util_format_is_depth_or_stencil(src->format) && src->nr_samples <= 1 && 926 /* DCC compression from image store is enabled for GFX10+. */ 927 (!vi_dcc_enabled(sdst, dst_level) || sctx->chip_class >= GFX10) && 928 !(dst->target != src->target && 929 (src->target == PIPE_TEXTURE_1D_ARRAY || dst->target == PIPE_TEXTURE_1D_ARRAY))) { 930 si_compute_copy_image(sctx, dst, dst_level, src, src_level, dstx, dsty, dstz, 931 src_box, false, SI_OP_SYNC_BEFORE_AFTER); 932 return; 933 } 934 935 assert(u_max_sample(dst) == u_max_sample(src)); 936 937 /* The driver doesn't decompress resources automatically while 938 * u_blitter is rendering. */ 939 si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level, src_box->z, 940 src_box->z + src_box->depth - 1); 941 942 dst_width = u_minify(dst->width0, dst_level); 943 dst_height = u_minify(dst->height0, dst_level); 944 dst_width0 = dst->width0; 945 dst_height0 = dst->height0; 946 src_width0 = src->width0; 947 src_height0 = src->height0; 948 949 util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz); 950 util_blitter_default_src_texture(sctx->blitter, &src_templ, src, src_level); 951 952 if (util_format_is_compressed(src->format) || util_format_is_compressed(dst->format)) { 953 unsigned blocksize = ssrc->surface.bpe; 954 955 if (blocksize == 8) 956 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */ 957 else 958 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */ 959 dst_templ.format = src_templ.format; 960 961 dst_width = util_format_get_nblocksx(dst->format, dst_width); 962 dst_height = util_format_get_nblocksy(dst->format, dst_height); 963 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0); 964 dst_height0 = util_format_get_nblocksy(dst->format, dst_height0); 965 src_width0 = util_format_get_nblocksx(src->format, src_width0); 966 src_height0 = util_format_get_nblocksy(src->format, src_height0); 967 968 dstx = util_format_get_nblocksx(dst->format, dstx); 969 dsty = util_format_get_nblocksy(dst->format, dsty); 970 971 sbox.x = util_format_get_nblocksx(src->format, src_box->x); 972 sbox.y = util_format_get_nblocksy(src->format, src_box->y); 973 sbox.z = src_box->z; 974 sbox.width = util_format_get_nblocksx(src->format, src_box->width); 975 sbox.height = util_format_get_nblocksy(src->format, src_box->height); 976 sbox.depth = src_box->depth; 977 src_box = &sbox; 978 979 src_force_level = src_level; 980 } else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) { 981 if (util_format_is_subsampled_422(src->format)) { 982 src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT; 983 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT; 984 985 dst_width = util_format_get_nblocksx(dst->format, dst_width); 986 dst_width0 = util_format_get_nblocksx(dst->format, dst_width0); 987 src_width0 = util_format_get_nblocksx(src->format, src_width0); 988 989 dstx = util_format_get_nblocksx(dst->format, dstx); 990 991 sbox = *src_box; 992 sbox.x = util_format_get_nblocksx(src->format, src_box->x); 993 sbox.width = util_format_get_nblocksx(src->format, src_box->width); 994 src_box = &sbox; 995 } else { 996 unsigned blocksize = ssrc->surface.bpe; 997 998 switch (blocksize) { 999 case 1: 1000 dst_templ.format = PIPE_FORMAT_R8_UNORM; 1001 src_templ.format = PIPE_FORMAT_R8_UNORM; 1002 break; 1003 case 2: 1004 dst_templ.format = PIPE_FORMAT_R8G8_UNORM; 1005 src_templ.format = PIPE_FORMAT_R8G8_UNORM; 1006 break; 1007 case 4: 1008 dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM; 1009 src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM; 1010 break; 1011 case 8: 1012 dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; 1013 src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; 1014 break; 1015 case 16: 1016 dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; 1017 src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; 1018 break; 1019 default: 1020 fprintf(stderr, "Unhandled format %s with blocksize %u\n", 1021 util_format_short_name(src->format), blocksize); 1022 assert(0); 1023 } 1024 } 1025 } 1026 1027 /* SNORM8 blitting has precision issues on some chips. Use the SINT 1028 * equivalent instead, which doesn't force DCC decompression. 1029 */ 1030 if (util_format_is_snorm8(dst_templ.format)) { 1031 dst_templ.format = src_templ.format = util_format_snorm8_to_sint8(dst_templ.format); 1032 } 1033 1034 vi_disable_dcc_if_incompatible_format(sctx, dst, dst_level, dst_templ.format); 1035 vi_disable_dcc_if_incompatible_format(sctx, src, src_level, src_templ.format); 1036 1037 /* Initialize the surface. */ 1038 dst_view = si_create_surface_custom(ctx, dst, &dst_templ, dst_width0, dst_height0, dst_width, 1039 dst_height); 1040 1041 /* Initialize the sampler view. */ 1042 src_view = 1043 si_create_sampler_view_custom(ctx, src, &src_templ, src_width0, src_height0, src_force_level); 1044 1045 u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height), abs(src_box->depth), 1046 &dstbox); 1047 1048 /* Copy. */ 1049 si_blitter_begin(sctx, SI_COPY); 1050 util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox, src_view, src_box, src_width0, 1051 src_height0, PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL, false, false); 1052 si_blitter_end(sctx); 1053 1054 pipe_surface_reference(&dst_view, NULL); 1055 pipe_sampler_view_reference(&src_view, NULL); 1056} 1057 1058static void si_do_CB_resolve(struct si_context *sctx, const struct pipe_blit_info *info, 1059 struct pipe_resource *dst, unsigned dst_level, unsigned dst_z, 1060 enum pipe_format format) 1061{ 1062 /* Required before and after CB_RESOLVE. */ 1063 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB; 1064 1065 si_blitter_begin( 1066 sctx, SI_COLOR_RESOLVE | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND)); 1067 util_blitter_custom_resolve_color(sctx->blitter, dst, dst_level, dst_z, info->src.resource, 1068 info->src.box.z, ~0, sctx->custom_blend_resolve, format); 1069 si_blitter_end(sctx); 1070 1071 /* Flush caches for possible texturing. */ 1072 si_make_CB_shader_coherent(sctx, 1, false, true /* no DCC */); 1073} 1074 1075static bool resolve_formats_compatible(enum pipe_format src, enum pipe_format dst, 1076 bool src_swaps_rgb_to_bgr, bool *need_rgb_to_bgr) 1077{ 1078 *need_rgb_to_bgr = false; 1079 1080 if (src_swaps_rgb_to_bgr) { 1081 /* We must only check the swapped format. */ 1082 enum pipe_format swapped_src = util_format_rgb_to_bgr(src); 1083 assert(swapped_src); 1084 return util_is_format_compatible(util_format_description(swapped_src), 1085 util_format_description(dst)); 1086 } 1087 1088 if (util_is_format_compatible(util_format_description(src), util_format_description(dst))) 1089 return true; 1090 1091 enum pipe_format swapped_src = util_format_rgb_to_bgr(src); 1092 *need_rgb_to_bgr = util_is_format_compatible(util_format_description(swapped_src), 1093 util_format_description(dst)); 1094 return *need_rgb_to_bgr; 1095} 1096 1097static bool do_hardware_msaa_resolve(struct pipe_context *ctx, const struct pipe_blit_info *info) 1098{ 1099 struct si_context *sctx = (struct si_context *)ctx; 1100 struct si_texture *src = (struct si_texture *)info->src.resource; 1101 struct si_texture *dst = (struct si_texture *)info->dst.resource; 1102 ASSERTED struct si_texture *stmp; 1103 unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level); 1104 unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level); 1105 enum pipe_format format = info->src.format; 1106 struct pipe_resource *tmp, templ; 1107 struct pipe_blit_info blit; 1108 1109 /* Check basic requirements for hw resolve. */ 1110 if (!(info->src.resource->nr_samples > 1 && info->dst.resource->nr_samples <= 1 && 1111 !util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format) && 1112 util_max_layer(info->src.resource, 0) == 0)) 1113 return false; 1114 1115 /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and 1116 * the format is R16G16. Use R16A16, which does work. 1117 */ 1118 if (format == PIPE_FORMAT_R16G16_UNORM) 1119 format = PIPE_FORMAT_R16A16_UNORM; 1120 if (format == PIPE_FORMAT_R16G16_SNORM) 1121 format = PIPE_FORMAT_R16A16_SNORM; 1122 1123 bool need_rgb_to_bgr = false; 1124 1125 /* Check the remaining requirements for hw resolve. */ 1126 if (util_max_layer(info->dst.resource, info->dst.level) == 0 && !info->scissor_enable && 1127 (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA && 1128 resolve_formats_compatible(info->src.format, info->dst.format, 1129 src->swap_rgb_to_bgr, &need_rgb_to_bgr) && 1130 dst_width == info->src.resource->width0 && dst_height == info->src.resource->height0 && 1131 info->dst.box.x == 0 && info->dst.box.y == 0 && info->dst.box.width == dst_width && 1132 info->dst.box.height == dst_height && info->dst.box.depth == 1 && info->src.box.x == 0 && 1133 info->src.box.y == 0 && info->src.box.width == dst_width && 1134 info->src.box.height == dst_height && info->src.box.depth == 1 && !dst->surface.is_linear && 1135 (!dst->cmask_buffer || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */ 1136 /* Check the remaining constraints. */ 1137 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode || 1138 need_rgb_to_bgr) { 1139 /* The next fast clear will switch to this mode to 1140 * get direct hw resolve next time if the mode is 1141 * different now. 1142 * 1143 * TODO-GFX10: This does not work in GFX10 because MSAA 1144 * is restricted to 64KB_R_X and 64KB_Z_X swizzle modes. 1145 * In some cases we could change the swizzle of the 1146 * destination texture instead, but the more general 1147 * solution is to implement compute shader resolve. 1148 */ 1149 if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) 1150 src->last_msaa_resolve_target_micro_mode = dst->surface.micro_tile_mode; 1151 if (need_rgb_to_bgr) 1152 src->swap_rgb_to_bgr_on_next_clear = true; 1153 1154 goto resolve_to_temp; 1155 } 1156 1157 /* Resolving into a surface with DCC is unsupported. Since 1158 * it's being overwritten anyway, clear it to uncompressed. 1159 * This is still the fastest codepath even with this clear. 1160 */ 1161 if (vi_dcc_enabled(dst, info->dst.level)) { 1162 struct si_clear_info clear_info; 1163 1164 if (!vi_dcc_get_clear_info(sctx, dst, info->dst.level, DCC_UNCOMPRESSED, &clear_info)) 1165 goto resolve_to_temp; 1166 1167 si_execute_clears(sctx, &clear_info, 1, SI_CLEAR_TYPE_DCC); 1168 dst->dirty_level_mask &= ~(1 << info->dst.level); 1169 } 1170 1171 /* Resolve directly from src to dst. */ 1172 si_do_CB_resolve(sctx, info, info->dst.resource, info->dst.level, info->dst.box.z, format); 1173 return true; 1174 } 1175 1176resolve_to_temp: 1177 /* Shader-based resolve is VERY SLOW. Instead, resolve into 1178 * a temporary texture and blit. 1179 */ 1180 memset(&templ, 0, sizeof(templ)); 1181 templ.target = PIPE_TEXTURE_2D; 1182 templ.format = info->src.resource->format; 1183 templ.width0 = info->src.resource->width0; 1184 templ.height0 = info->src.resource->height0; 1185 templ.depth0 = 1; 1186 templ.array_size = 1; 1187 templ.usage = PIPE_USAGE_DEFAULT; 1188 templ.flags = SI_RESOURCE_FLAG_FORCE_MSAA_TILING | SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE | 1189 SI_RESOURCE_FLAG_MICRO_TILE_MODE_SET(src->surface.micro_tile_mode) | 1190 SI_RESOURCE_FLAG_DISABLE_DCC | SI_RESOURCE_FLAG_DRIVER_INTERNAL; 1191 1192 /* The src and dst microtile modes must be the same. */ 1193 if (sctx->chip_class <= GFX8 && src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY) 1194 templ.bind = PIPE_BIND_SCANOUT; 1195 else 1196 templ.bind = 0; 1197 1198 tmp = ctx->screen->resource_create(ctx->screen, &templ); 1199 if (!tmp) 1200 return false; 1201 stmp = (struct si_texture *)tmp; 1202 /* Match the channel order of src. */ 1203 stmp->swap_rgb_to_bgr = src->swap_rgb_to_bgr; 1204 1205 assert(!stmp->surface.is_linear); 1206 assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode); 1207 1208 /* resolve */ 1209 si_do_CB_resolve(sctx, info, tmp, 0, 0, format); 1210 1211 /* blit */ 1212 blit = *info; 1213 blit.src.resource = tmp; 1214 blit.src.box.z = 0; 1215 1216 si_blitter_begin(sctx, SI_BLIT | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND)); 1217 util_blitter_blit(sctx->blitter, &blit); 1218 si_blitter_end(sctx); 1219 1220 pipe_resource_reference(&tmp, NULL); 1221 return true; 1222} 1223 1224static void si_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) 1225{ 1226 struct si_context *sctx = (struct si_context *)ctx; 1227 struct si_texture *sdst = (struct si_texture *)info->dst.resource; 1228 1229 if (do_hardware_msaa_resolve(ctx, info)) { 1230 return; 1231 } 1232 1233 if (info->is_dri_blit_image && sdst->surface.is_linear && 1234 sctx->chip_class >= GFX7 && sdst->surface.flags & RADEON_SURF_IMPORTED) { 1235 struct si_texture *ssrc = (struct si_texture *)info->src.resource; 1236 /* Use SDMA or async compute when copying to a DRI_PRIME imported linear surface. */ 1237 bool async_copy = info->dst.box.x == 0 && info->dst.box.y == 0 && info->dst.box.z == 0 && 1238 info->src.box.x == 0 && info->src.box.y == 0 && info->src.box.z == 0 && 1239 info->dst.level == 0 && info->src.level == 0 && 1240 info->src.box.width == info->dst.resource->width0 && 1241 info->src.box.height == info->dst.resource->height0 && 1242 info->src.box.depth == 1 && util_can_blit_via_copy_region(info, true); 1243 /* Try SDMA first... */ 1244 /* TODO: figure out why SDMA copies are slow on GFX10_3 */ 1245 if (async_copy && sctx->chip_class < GFX10_3 && si_sdma_copy_image(sctx, sdst, ssrc)) 1246 return; 1247 1248 /* ... and use async compute as the fallback. */ 1249 if (async_copy) { 1250 struct si_screen *sscreen = sctx->screen; 1251 1252 simple_mtx_lock(&sscreen->async_compute_context_lock); 1253 if (!sscreen->async_compute_context) 1254 si_init_aux_async_compute_ctx(sscreen); 1255 1256 if (sscreen->async_compute_context) { 1257 si_compute_copy_image((struct si_context*)sctx->screen->async_compute_context, 1258 info->dst.resource, 0, info->src.resource, 0, 0, 0, 0, 1259 &info->src.box, false, 0); 1260 si_flush_gfx_cs((struct si_context*)sctx->screen->async_compute_context, 0, NULL); 1261 simple_mtx_unlock(&sscreen->async_compute_context_lock); 1262 return; 1263 } 1264 1265 simple_mtx_unlock(&sscreen->async_compute_context_lock); 1266 } 1267 } 1268 1269 if (unlikely(sctx->thread_trace_enabled)) 1270 sctx->sqtt_next_event = EventCmdCopyImage; 1271 1272 /* Using compute for copying to a linear texture in GTT is much faster than 1273 * going through RBs (render backends). This improves DRI PRIME performance. 1274 */ 1275 if (util_can_blit_via_copy_region(info, false)) { 1276 si_resource_copy_region(ctx, info->dst.resource, info->dst.level, 1277 info->dst.box.x, info->dst.box.y, info->dst.box.z, 1278 info->src.resource, info->src.level, &info->src.box); 1279 return; 1280 } 1281 1282 assert(util_blitter_is_blit_supported(sctx->blitter, info)); 1283 1284 /* The driver doesn't decompress resources automatically while 1285 * u_blitter is rendering. */ 1286 vi_disable_dcc_if_incompatible_format(sctx, info->src.resource, info->src.level, 1287 info->src.format); 1288 vi_disable_dcc_if_incompatible_format(sctx, info->dst.resource, info->dst.level, 1289 info->dst.format); 1290 si_decompress_subresource(ctx, info->src.resource, PIPE_MASK_RGBAZS, info->src.level, 1291 info->src.box.z, info->src.box.z + info->src.box.depth - 1); 1292 1293 if (unlikely(sctx->thread_trace_enabled)) 1294 sctx->sqtt_next_event = EventCmdBlitImage; 1295 1296 si_blitter_begin(sctx, SI_BLIT | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND)); 1297 util_blitter_blit(sctx->blitter, info); 1298 si_blitter_end(sctx); 1299} 1300 1301static bool si_generate_mipmap(struct pipe_context *ctx, struct pipe_resource *tex, 1302 enum pipe_format format, unsigned base_level, unsigned last_level, 1303 unsigned first_layer, unsigned last_layer) 1304{ 1305 struct si_context *sctx = (struct si_context *)ctx; 1306 struct si_texture *stex = (struct si_texture *)tex; 1307 1308 if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex)) 1309 return false; 1310 1311 /* The driver doesn't decompress resources automatically while 1312 * u_blitter is rendering. */ 1313 vi_disable_dcc_if_incompatible_format(sctx, tex, base_level, format); 1314 si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS, base_level, first_layer, last_layer); 1315 1316 /* Clear dirty_level_mask for the levels that will be overwritten. */ 1317 assert(base_level < last_level); 1318 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1, last_level - base_level); 1319 1320 sctx->generate_mipmap_for_depth = stex->is_depth; 1321 1322 si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND); 1323 util_blitter_generate_mipmap(sctx->blitter, tex, format, base_level, last_level, first_layer, 1324 last_layer); 1325 si_blitter_end(sctx); 1326 1327 sctx->generate_mipmap_for_depth = false; 1328 return true; 1329} 1330 1331static void si_flush_resource(struct pipe_context *ctx, struct pipe_resource *res) 1332{ 1333 struct si_context *sctx = (struct si_context *)ctx; 1334 struct si_texture *tex = (struct si_texture *)res; 1335 1336 assert(res->target != PIPE_BUFFER); 1337 1338 if (!tex->is_depth && (tex->cmask_buffer || vi_dcc_enabled(tex, 0))) { 1339 si_blit_decompress_color(sctx, tex, 0, res->last_level, 0, util_max_layer(res, 0), 1340 false, false); 1341 1342 if (tex->surface.display_dcc_offset && tex->displayable_dcc_dirty) { 1343 si_retile_dcc(sctx, tex); 1344 tex->displayable_dcc_dirty = false; 1345 } 1346 } 1347} 1348 1349void si_flush_implicit_resources(struct si_context *sctx) 1350{ 1351 hash_table_foreach(sctx->dirty_implicit_resources, entry) { 1352 si_flush_resource(&sctx->b, entry->data); 1353 pipe_resource_reference((struct pipe_resource **)&entry->data, NULL); 1354 } 1355 _mesa_hash_table_clear(sctx->dirty_implicit_resources, NULL); 1356} 1357 1358void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex) 1359{ 1360 assert(!tex->is_depth); 1361 1362 /* If graphics is disabled, we can't decompress DCC, but it shouldn't 1363 * be compressed either. The caller should simply discard it. 1364 */ 1365 if (!tex->surface.meta_offset || !sctx->has_graphics) 1366 return; 1367 1368 if (sctx->chip_class == GFX8 || tex->buffer.b.b.nr_storage_samples >= 2) { 1369 si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level, 0, 1370 util_max_layer(&tex->buffer.b.b, 0), true, false); 1371 } else { 1372 struct pipe_resource *ptex = &tex->buffer.b.b; 1373 assert(ptex->nr_storage_samples <= 1); 1374 1375 /* DCC decompression using a compute shader. */ 1376 for (unsigned level = 0; level < tex->surface.num_meta_levels; level++) { 1377 struct pipe_box box; 1378 1379 u_box_3d(0, 0, 0, u_minify(ptex->width0, level), 1380 u_minify(ptex->height0, level), 1381 util_num_layers(ptex, level), &box); 1382 si_compute_copy_image(sctx, ptex, level, ptex, level, 0, 0, 0, &box, true, 1383 /* Sync before the first copy and after the last copy */ 1384 (level == 0 ? SI_OP_SYNC_BEFORE : 0) | 1385 (level == tex->surface.num_meta_levels - 1 ? SI_OP_SYNC_AFTER : 0)); 1386 } 1387 1388 /* Now clear DCC metadata to uncompressed. 1389 * 1390 * This uses SI_COMPUTE_CLEAR_METHOD to avoid a failure when running this 1391 * deqp caselist on gfx10: 1392 * dEQP-GLES31.functional.image_load_store.2d.format_reinterpret.rgba32f_rgba32ui 1393 * dEQP-GLES31.functional.image_load_store.2d.format_reinterpret.rgba32f_rgba32i 1394 */ 1395 uint32_t clear_value = DCC_UNCOMPRESSED; 1396 si_clear_buffer(sctx, ptex, tex->surface.meta_offset, 1397 tex->surface.meta_size, &clear_value, 4, SI_OP_SYNC_AFTER, 1398 SI_COHERENCY_CB_META, SI_COMPUTE_CLEAR_METHOD); 1399 si_mark_display_dcc_dirty(sctx, tex); 1400 1401 /* Clearing DCC metadata requires flushing L2 and invalidating L2 metadata to make 1402 * the metadata visible to L2 caches. This is because clear_buffer uses plain stores 1403 * that can go to different L2 channels than where L2 metadata caches expect them. 1404 * This is not done for fast clears because plain stores are visible to CB/DB. Only 1405 * L2 metadata caches have the problem. 1406 */ 1407 sctx->flags |= SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_L2_METADATA; 1408 } 1409} 1410 1411void si_init_blit_functions(struct si_context *sctx) 1412{ 1413 sctx->b.resource_copy_region = si_resource_copy_region; 1414 1415 if (sctx->has_graphics) { 1416 sctx->b.blit = si_blit; 1417 sctx->b.flush_resource = si_flush_resource; 1418 sctx->b.generate_mipmap = si_generate_mipmap; 1419 } 1420} 1421