si_pipe.c revision 993e1d59
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * Copyright 2018 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * on the rights to use, copy, modify, merge, publish, distribute, sub 10 * license, and/or sell copies of the Software, and to permit persons to whom 11 * the Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 23 * USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#include "si_pipe.h" 27#include "si_public.h" 28#include "si_shader_internal.h" 29#include "sid.h" 30 31#include "ac_llvm_util.h" 32#include "radeon/radeon_uvd.h" 33#include "gallivm/lp_bld_misc.h" 34#include "util/disk_cache.h" 35#include "util/u_log.h" 36#include "util/u_memory.h" 37#include "util/u_suballoc.h" 38#include "util/u_tests.h" 39#include "util/u_upload_mgr.h" 40#include "util/xmlconfig.h" 41#include "vl/vl_decoder.h" 42#include "driver_ddebug/dd_util.h" 43 44static const struct debug_named_value debug_options[] = { 45 /* Shader logging options: */ 46 { "vs", DBG(VS), "Print vertex shaders" }, 47 { "ps", DBG(PS), "Print pixel shaders" }, 48 { "gs", DBG(GS), "Print geometry shaders" }, 49 { "tcs", DBG(TCS), "Print tessellation control shaders" }, 50 { "tes", DBG(TES), "Print tessellation evaluation shaders" }, 51 { "cs", DBG(CS), "Print compute shaders" }, 52 { "noir", DBG(NO_IR), "Don't print the LLVM IR"}, 53 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"}, 54 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"}, 55 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" }, 56 57 /* Shader compiler options the shader cache should be aware of: */ 58 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" }, 59 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." }, 60 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." }, 61 62 /* Shader compiler options (with no effect on the shader cache): */ 63 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" }, 64 { "nir", DBG(NIR), "Enable experimental NIR shaders" }, 65 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" }, 66 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." }, 67 68 /* Information logging options: */ 69 { "info", DBG(INFO), "Print driver information" }, 70 { "tex", DBG(TEX), "Print texture info" }, 71 { "compute", DBG(COMPUTE), "Print compute info" }, 72 { "vm", DBG(VM), "Print virtual addresses when creating resources" }, 73 74 /* Driver options: */ 75 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." }, 76 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" }, 77 { "nowc", DBG(NO_WC), "Disable GTT write combining" }, 78 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." }, 79 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." }, 80 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." }, 81 82 /* 3D engine options: */ 83 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." }, 84 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" }, 85 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." }, 86 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." }, 87 { "dpbb", DBG(DPBB), "Enable DPBB." }, 88 { "dfsm", DBG(DFSM), "Enable DFSM." }, 89 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" }, 90 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." }, 91 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" }, 92 { "notiling", DBG(NO_TILING), "Disable tiling" }, 93 { "nodcc", DBG(NO_DCC), "Disable DCC." }, 94 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." }, 95 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" }, 96 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" }, 97 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" }, 98 99 /* Tests: */ 100 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." }, 101 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." }, 102 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." }, 103 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." }, 104 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" }, 105 { "testgds", DBG(TEST_GDS), "Test GDS." }, 106 107 DEBUG_NAMED_VALUE_END /* must be last */ 108}; 109 110static void si_init_compiler(struct si_screen *sscreen, 111 struct ac_llvm_compiler *compiler) 112{ 113 /* Only create the less-optimizing version of the compiler on APUs 114 * predating Ryzen (Raven). */ 115 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram && 116 sscreen->info.chip_class <= VI; 117 118 enum ac_target_machine_options tm_options = 119 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) | 120 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) | 121 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) | 122 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) | 123 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) | 124 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) | 125 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0); 126 127 ac_init_llvm_once(); 128 ac_init_llvm_compiler(compiler, true, sscreen->info.family, tm_options); 129 compiler->passes = ac_create_llvm_passes(compiler->tm); 130 131 if (compiler->low_opt_tm) 132 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm); 133} 134 135static void si_destroy_compiler(struct ac_llvm_compiler *compiler) 136{ 137 ac_destroy_llvm_passes(compiler->passes); 138 ac_destroy_llvm_passes(compiler->low_opt_passes); 139 ac_destroy_llvm_compiler(compiler); 140} 141 142/* 143 * pipe_context 144 */ 145static void si_destroy_context(struct pipe_context *context) 146{ 147 struct si_context *sctx = (struct si_context *)context; 148 int i; 149 150 /* Unreference the framebuffer normally to disable related logic 151 * properly. 152 */ 153 struct pipe_framebuffer_state fb = {}; 154 if (context->set_framebuffer_state) 155 context->set_framebuffer_state(context, &fb); 156 157 si_release_all_descriptors(sctx); 158 159 pipe_resource_reference(&sctx->esgs_ring, NULL); 160 pipe_resource_reference(&sctx->gsvs_ring, NULL); 161 pipe_resource_reference(&sctx->tess_rings, NULL); 162 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL); 163 pipe_resource_reference(&sctx->sample_pos_buffer, NULL); 164 r600_resource_reference(&sctx->border_color_buffer, NULL); 165 free(sctx->border_color_table); 166 r600_resource_reference(&sctx->scratch_buffer, NULL); 167 r600_resource_reference(&sctx->compute_scratch_buffer, NULL); 168 r600_resource_reference(&sctx->wait_mem_scratch, NULL); 169 170 si_pm4_free_state(sctx, sctx->init_config, ~0); 171 if (sctx->init_config_gs_rings) 172 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0); 173 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++) 174 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]); 175 176 if (sctx->fixed_func_tcs_shader.cso) 177 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso); 178 if (sctx->custom_dsa_flush) 179 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush); 180 if (sctx->custom_blend_resolve) 181 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve); 182 if (sctx->custom_blend_fmask_decompress) 183 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress); 184 if (sctx->custom_blend_eliminate_fastclear) 185 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear); 186 if (sctx->custom_blend_dcc_decompress) 187 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress); 188 if (sctx->vs_blit_pos) 189 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos); 190 if (sctx->vs_blit_pos_layered) 191 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered); 192 if (sctx->vs_blit_color) 193 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color); 194 if (sctx->vs_blit_color_layered) 195 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered); 196 if (sctx->vs_blit_texcoord) 197 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord); 198 if (sctx->cs_clear_buffer) 199 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer); 200 if (sctx->cs_copy_buffer) 201 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer); 202 203 if (sctx->blitter) 204 util_blitter_destroy(sctx->blitter); 205 206 /* Release DCC stats. */ 207 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) { 208 assert(!sctx->dcc_stats[i].query_active); 209 210 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++) 211 if (sctx->dcc_stats[i].ps_stats[j]) 212 sctx->b.destroy_query(&sctx->b, 213 sctx->dcc_stats[i].ps_stats[j]); 214 215 si_texture_reference(&sctx->dcc_stats[i].tex, NULL); 216 } 217 218 if (sctx->query_result_shader) 219 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader); 220 221 if (sctx->gfx_cs) 222 sctx->ws->cs_destroy(sctx->gfx_cs); 223 if (sctx->dma_cs) 224 sctx->ws->cs_destroy(sctx->dma_cs); 225 if (sctx->ctx) 226 sctx->ws->ctx_destroy(sctx->ctx); 227 228 if (sctx->b.stream_uploader) 229 u_upload_destroy(sctx->b.stream_uploader); 230 if (sctx->b.const_uploader) 231 u_upload_destroy(sctx->b.const_uploader); 232 if (sctx->cached_gtt_allocator) 233 u_upload_destroy(sctx->cached_gtt_allocator); 234 235 slab_destroy_child(&sctx->pool_transfers); 236 slab_destroy_child(&sctx->pool_transfers_unsync); 237 238 if (sctx->allocator_zeroed_memory) 239 u_suballocator_destroy(sctx->allocator_zeroed_memory); 240 241 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL); 242 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL); 243 r600_resource_reference(&sctx->eop_bug_scratch, NULL); 244 245 si_destroy_compiler(&sctx->compiler); 246 247 si_saved_cs_reference(&sctx->current_saved_cs, NULL); 248 249 _mesa_hash_table_destroy(sctx->tex_handles, NULL); 250 _mesa_hash_table_destroy(sctx->img_handles, NULL); 251 252 util_dynarray_fini(&sctx->resident_tex_handles); 253 util_dynarray_fini(&sctx->resident_img_handles); 254 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress); 255 util_dynarray_fini(&sctx->resident_img_needs_color_decompress); 256 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress); 257 FREE(sctx); 258} 259 260static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx) 261{ 262 struct si_context *sctx = (struct si_context *)ctx; 263 264 if (sctx->screen->info.has_gpu_reset_status_query) 265 return sctx->ws->ctx_query_reset_status(sctx->ctx); 266 267 if (sctx->screen->info.has_gpu_reset_counter_query) { 268 unsigned latest = sctx->ws->query_value(sctx->ws, 269 RADEON_GPU_RESET_COUNTER); 270 271 if (sctx->gpu_reset_counter == latest) 272 return PIPE_NO_RESET; 273 274 sctx->gpu_reset_counter = latest; 275 return PIPE_UNKNOWN_CONTEXT_RESET; 276 } 277 278 return PIPE_NO_RESET; 279} 280 281static void si_set_device_reset_callback(struct pipe_context *ctx, 282 const struct pipe_device_reset_callback *cb) 283{ 284 struct si_context *sctx = (struct si_context *)ctx; 285 286 if (cb) 287 sctx->device_reset_callback = *cb; 288 else 289 memset(&sctx->device_reset_callback, 0, 290 sizeof(sctx->device_reset_callback)); 291} 292 293bool si_check_device_reset(struct si_context *sctx) 294{ 295 enum pipe_reset_status status; 296 297 if (!sctx->device_reset_callback.reset) 298 return false; 299 300 if (!sctx->b.get_device_reset_status) 301 return false; 302 303 status = sctx->b.get_device_reset_status(&sctx->b); 304 if (status == PIPE_NO_RESET) 305 return false; 306 307 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status); 308 return true; 309} 310 311/* Apitrace profiling: 312 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times 313 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call 314 * and remember its number. 315 * 3) In Mesa, enable queries and performance counters around that draw 316 * call and print the results. 317 * 4) glretrace --benchmark --markers .. 318 */ 319static void si_emit_string_marker(struct pipe_context *ctx, 320 const char *string, int len) 321{ 322 struct si_context *sctx = (struct si_context *)ctx; 323 324 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number); 325 326 if (sctx->log) 327 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string); 328} 329 330static void si_set_debug_callback(struct pipe_context *ctx, 331 const struct pipe_debug_callback *cb) 332{ 333 struct si_context *sctx = (struct si_context *)ctx; 334 struct si_screen *screen = sctx->screen; 335 336 util_queue_finish(&screen->shader_compiler_queue); 337 util_queue_finish(&screen->shader_compiler_queue_low_priority); 338 339 if (cb) 340 sctx->debug = *cb; 341 else 342 memset(&sctx->debug, 0, sizeof(sctx->debug)); 343} 344 345static void si_set_log_context(struct pipe_context *ctx, 346 struct u_log_context *log) 347{ 348 struct si_context *sctx = (struct si_context *)ctx; 349 sctx->log = log; 350 351 if (log) 352 u_log_add_auto_logger(log, si_auto_log_cs, sctx); 353} 354 355static void si_set_context_param(struct pipe_context *ctx, 356 enum pipe_context_param param, 357 unsigned value) 358{ 359 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws; 360 361 switch (param) { 362 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE: 363 ws->pin_threads_to_L3_cache(ws, value); 364 break; 365 default:; 366 } 367} 368 369static struct pipe_context *si_create_context(struct pipe_screen *screen, 370 unsigned flags) 371{ 372 struct si_context *sctx = CALLOC_STRUCT(si_context); 373 struct si_screen* sscreen = (struct si_screen *)screen; 374 struct radeon_winsys *ws = sscreen->ws; 375 int shader, i; 376 377 if (!sctx) 378 return NULL; 379 380 if (flags & PIPE_CONTEXT_DEBUG) 381 sscreen->record_llvm_ir = true; /* racy but not critical */ 382 383 sctx->b.screen = screen; /* this must be set first */ 384 sctx->b.priv = NULL; 385 sctx->b.destroy = si_destroy_context; 386 sctx->b.emit_string_marker = si_emit_string_marker; 387 sctx->b.set_debug_callback = si_set_debug_callback; 388 sctx->b.set_log_context = si_set_log_context; 389 sctx->b.set_context_param = si_set_context_param; 390 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */ 391 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0; 392 393 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers); 394 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers); 395 396 sctx->ws = sscreen->ws; 397 sctx->family = sscreen->info.family; 398 sctx->chip_class = sscreen->info.chip_class; 399 400 if (sscreen->info.has_gpu_reset_counter_query) { 401 sctx->gpu_reset_counter = 402 sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER); 403 } 404 405 sctx->b.get_device_reset_status = si_get_reset_status; 406 sctx->b.set_device_reset_callback = si_set_device_reset_callback; 407 408 si_init_context_texture_functions(sctx); 409 si_init_query_functions(sctx); 410 411 if (sctx->chip_class == CIK || 412 sctx->chip_class == VI || 413 sctx->chip_class == GFX9) { 414 sctx->eop_bug_scratch = r600_resource( 415 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 416 16 * sscreen->info.num_render_backends)); 417 if (!sctx->eop_bug_scratch) 418 goto fail; 419 } 420 421 sctx->allocator_zeroed_memory = 422 u_suballocator_create(&sctx->b, sscreen->info.gart_page_size, 423 0, PIPE_USAGE_DEFAULT, 424 SI_RESOURCE_FLAG_SO_FILLED_SIZE, true); 425 if (!sctx->allocator_zeroed_memory) 426 goto fail; 427 428 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024, 429 0, PIPE_USAGE_STREAM, 430 SI_RESOURCE_FLAG_READ_ONLY); 431 if (!sctx->b.stream_uploader) 432 goto fail; 433 434 sctx->b.const_uploader = u_upload_create(&sctx->b, 128 * 1024, 435 0, PIPE_USAGE_DEFAULT, 436 SI_RESOURCE_FLAG_32BIT | 437 (sscreen->cpdma_prefetch_writes_memory ? 438 0 : SI_RESOURCE_FLAG_READ_ONLY)); 439 if (!sctx->b.const_uploader) 440 goto fail; 441 442 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024, 443 0, PIPE_USAGE_STAGING, 0); 444 if (!sctx->cached_gtt_allocator) 445 goto fail; 446 447 sctx->ctx = sctx->ws->ctx_create(sctx->ws); 448 if (!sctx->ctx) 449 goto fail; 450 451 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) { 452 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA, 453 (void*)si_flush_dma_cs, 454 sctx); 455 } 456 457 si_init_buffer_functions(sctx); 458 si_init_clear_functions(sctx); 459 si_init_blit_functions(sctx); 460 si_init_compute_functions(sctx); 461 si_init_compute_blit_functions(sctx); 462 si_init_debug_functions(sctx); 463 si_init_msaa_functions(sctx); 464 si_init_streamout_functions(sctx); 465 466 if (sscreen->info.has_hw_decode) { 467 sctx->b.create_video_codec = si_uvd_create_decoder; 468 sctx->b.create_video_buffer = si_video_buffer_create; 469 } else { 470 sctx->b.create_video_codec = vl_create_decoder; 471 sctx->b.create_video_buffer = vl_video_buffer_create; 472 } 473 474 sctx->gfx_cs = ws->cs_create(sctx->ctx, RING_GFX, 475 (void*)si_flush_gfx_cs, sctx); 476 477 /* Border colors. */ 478 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS * 479 sizeof(*sctx->border_color_table)); 480 if (!sctx->border_color_table) 481 goto fail; 482 483 sctx->border_color_buffer = r600_resource( 484 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 485 SI_MAX_BORDER_COLORS * 486 sizeof(*sctx->border_color_table))); 487 if (!sctx->border_color_buffer) 488 goto fail; 489 490 sctx->border_color_map = 491 ws->buffer_map(sctx->border_color_buffer->buf, 492 NULL, PIPE_TRANSFER_WRITE); 493 if (!sctx->border_color_map) 494 goto fail; 495 496 si_init_all_descriptors(sctx); 497 si_init_fence_functions(sctx); 498 si_init_state_functions(sctx); 499 si_init_shader_functions(sctx); 500 si_init_viewport_functions(sctx); 501 si_init_ia_multi_vgt_param_table(sctx); 502 503 if (sctx->chip_class >= CIK) 504 cik_init_sdma_functions(sctx); 505 else 506 si_init_dma_functions(sctx); 507 508 if (sscreen->debug_flags & DBG(FORCE_DMA)) 509 sctx->b.resource_copy_region = sctx->dma_copy; 510 511 sctx->blitter = util_blitter_create(&sctx->b); 512 if (sctx->blitter == NULL) 513 goto fail; 514 sctx->blitter->draw_rectangle = si_draw_rectangle; 515 sctx->blitter->skip_viewport_restore = true; 516 517 sctx->sample_mask = 0xffff; 518 519 if (sctx->chip_class >= GFX9) { 520 sctx->wait_mem_scratch = r600_resource( 521 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4)); 522 if (!sctx->wait_mem_scratch) 523 goto fail; 524 525 /* Initialize the memory. */ 526 struct radeon_cmdbuf *cs = sctx->gfx_cs; 527 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); 528 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) | 529 S_370_WR_CONFIRM(1) | 530 S_370_ENGINE_SEL(V_370_ME)); 531 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address); 532 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32); 533 radeon_emit(cs, sctx->wait_mem_number); 534 radeon_add_to_buffer_list(sctx, cs, sctx->wait_mem_scratch, 535 RADEON_USAGE_WRITE, RADEON_PRIO_FENCE); 536 } 537 538 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads 539 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */ 540 if (sctx->chip_class == CIK) { 541 sctx->null_const_buf.buffer = 542 pipe_aligned_buffer_create(screen, 543 SI_RESOURCE_FLAG_32BIT, 544 PIPE_USAGE_DEFAULT, 16, 545 sctx->screen->info.tcc_cache_line_size); 546 if (!sctx->null_const_buf.buffer) 547 goto fail; 548 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0; 549 550 for (shader = 0; shader < SI_NUM_SHADERS; shader++) { 551 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) { 552 sctx->b.set_constant_buffer(&sctx->b, shader, i, 553 &sctx->null_const_buf); 554 } 555 } 556 557 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, 558 &sctx->null_const_buf); 559 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, 560 &sctx->null_const_buf); 561 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, 562 &sctx->null_const_buf); 563 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, 564 &sctx->null_const_buf); 565 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, 566 &sctx->null_const_buf); 567 } 568 569 uint64_t max_threads_per_block; 570 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI, 571 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, 572 &max_threads_per_block); 573 574 /* The maximum number of scratch waves. Scratch space isn't divided 575 * evenly between CUs. The number is only a function of the number of CUs. 576 * We can decrease the constant to decrease the scratch buffer size. 577 * 578 * sctx->scratch_waves must be >= the maximum posible size of 579 * 1 threadgroup, so that the hw doesn't hang from being unable 580 * to start any. 581 * 582 * The recommended value is 4 per CU at most. Higher numbers don't 583 * bring much benefit, but they still occupy chip resources (think 584 * async compute). I've seen ~2% performance difference between 4 and 32. 585 */ 586 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units, 587 max_threads_per_block / 64); 588 589 si_init_compiler(sscreen, &sctx->compiler); 590 591 /* Bindless handles. */ 592 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, 593 _mesa_key_pointer_equal); 594 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, 595 _mesa_key_pointer_equal); 596 597 util_dynarray_init(&sctx->resident_tex_handles, NULL); 598 util_dynarray_init(&sctx->resident_img_handles, NULL); 599 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL); 600 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL); 601 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL); 602 603 sctx->sample_pos_buffer = 604 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT, 605 sizeof(sctx->sample_positions)); 606 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0, 607 sizeof(sctx->sample_positions), &sctx->sample_positions); 608 609 /* this must be last */ 610 si_begin_new_gfx_cs(sctx); 611 612 if (sctx->chip_class == CIK) { 613 /* Clear the NULL constant buffer, because loads should return zeros. */ 614 uint32_t clear_value = 0; 615 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, 616 sctx->null_const_buf.buffer->width0, 617 &clear_value, 4, SI_COHERENCY_SHADER); 618 } 619 return &sctx->b; 620fail: 621 fprintf(stderr, "radeonsi: Failed to create a context.\n"); 622 si_destroy_context(&sctx->b); 623 return NULL; 624} 625 626static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, 627 void *priv, unsigned flags) 628{ 629 struct si_screen *sscreen = (struct si_screen *)screen; 630 struct pipe_context *ctx; 631 632 if (sscreen->debug_flags & DBG(CHECK_VM)) 633 flags |= PIPE_CONTEXT_DEBUG; 634 635 ctx = si_create_context(screen, flags); 636 637 if (!(flags & PIPE_CONTEXT_PREFER_THREADED)) 638 return ctx; 639 640 /* Clover (compute-only) is unsupported. */ 641 if (flags & PIPE_CONTEXT_COMPUTE_ONLY) 642 return ctx; 643 644 /* When shaders are logged to stderr, asynchronous compilation is 645 * disabled too. */ 646 if (sscreen->debug_flags & DBG_ALL_SHADERS) 647 return ctx; 648 649 /* Use asynchronous flushes only on amdgpu, since the radeon 650 * implementation for fence_server_sync is incomplete. */ 651 return threaded_context_create(ctx, &sscreen->pool_transfers, 652 si_replace_buffer_storage, 653 sscreen->info.drm_major >= 3 ? si_create_fence : NULL, 654 &((struct si_context*)ctx)->tc); 655} 656 657/* 658 * pipe_screen 659 */ 660static void si_destroy_screen(struct pipe_screen* pscreen) 661{ 662 struct si_screen *sscreen = (struct si_screen *)pscreen; 663 struct si_shader_part *parts[] = { 664 sscreen->vs_prologs, 665 sscreen->tcs_epilogs, 666 sscreen->gs_prologs, 667 sscreen->ps_prologs, 668 sscreen->ps_epilogs 669 }; 670 unsigned i; 671 672 if (!sscreen->ws->unref(sscreen->ws)) 673 return; 674 675 util_queue_destroy(&sscreen->shader_compiler_queue); 676 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority); 677 678 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++) 679 si_destroy_compiler(&sscreen->compiler[i]); 680 681 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++) 682 si_destroy_compiler(&sscreen->compiler_lowp[i]); 683 684 /* Free shader parts. */ 685 for (i = 0; i < ARRAY_SIZE(parts); i++) { 686 while (parts[i]) { 687 struct si_shader_part *part = parts[i]; 688 689 parts[i] = part->next; 690 ac_shader_binary_clean(&part->binary); 691 FREE(part); 692 } 693 } 694 mtx_destroy(&sscreen->shader_parts_mutex); 695 si_destroy_shader_cache(sscreen); 696 697 si_perfcounters_destroy(sscreen); 698 si_gpu_load_kill_thread(sscreen); 699 700 mtx_destroy(&sscreen->gpu_load_mutex); 701 mtx_destroy(&sscreen->aux_context_lock); 702 sscreen->aux_context->destroy(sscreen->aux_context); 703 704 slab_destroy_parent(&sscreen->pool_transfers); 705 706 disk_cache_destroy(sscreen->disk_shader_cache); 707 sscreen->ws->destroy(sscreen->ws); 708 FREE(sscreen); 709} 710 711static void si_init_gs_info(struct si_screen *sscreen) 712{ 713 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class, 714 sscreen->info.family); 715} 716 717static void si_handle_env_var_force_family(struct si_screen *sscreen) 718{ 719 const char *family = debug_get_option("SI_FORCE_FAMILY", NULL); 720 unsigned i; 721 722 if (!family) 723 return; 724 725 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) { 726 if (!strcmp(family, ac_get_llvm_processor_name(i))) { 727 /* Override family and chip_class. */ 728 sscreen->info.family = i; 729 sscreen->info.name = "GCN-NOOP"; 730 731 if (i >= CHIP_VEGA10) 732 sscreen->info.chip_class = GFX9; 733 else if (i >= CHIP_TONGA) 734 sscreen->info.chip_class = VI; 735 else if (i >= CHIP_BONAIRE) 736 sscreen->info.chip_class = CIK; 737 else 738 sscreen->info.chip_class = SI; 739 740 /* Don't submit any IBs. */ 741 setenv("RADEON_NOOP", "1", 1); 742 return; 743 } 744 } 745 746 fprintf(stderr, "radeonsi: Unknown family: %s\n", family); 747 exit(1); 748} 749 750static void si_test_vmfault(struct si_screen *sscreen) 751{ 752 struct pipe_context *ctx = sscreen->aux_context; 753 struct si_context *sctx = (struct si_context *)ctx; 754 struct pipe_resource *buf = 755 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64); 756 757 if (!buf) { 758 puts("Buffer allocation failed."); 759 exit(1); 760 } 761 762 r600_resource(buf)->gpu_address = 0; /* cause a VM fault */ 763 764 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) { 765 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0, 766 SI_COHERENCY_NONE, L2_BYPASS); 767 ctx->flush(ctx, NULL, 0); 768 puts("VM fault test: CP - done."); 769 } 770 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) { 771 si_sdma_clear_buffer(sctx, buf, 0, 4, 0); 772 ctx->flush(ctx, NULL, 0); 773 puts("VM fault test: SDMA - done."); 774 } 775 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) { 776 util_test_constant_buffer(ctx, buf); 777 puts("VM fault test: Shader - done."); 778 } 779 exit(0); 780} 781 782static void si_disk_cache_create(struct si_screen *sscreen) 783{ 784 /* Don't use the cache if shader dumping is enabled. */ 785 if (sscreen->debug_flags & DBG_ALL_SHADERS) 786 return; 787 788 struct mesa_sha1 ctx; 789 unsigned char sha1[20]; 790 char cache_id[20 * 2 + 1]; 791 792 _mesa_sha1_init(&ctx); 793 794 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) || 795 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, 796 &ctx)) 797 return; 798 799 _mesa_sha1_final(&ctx, sha1); 800 disk_cache_format_hex_id(cache_id, sha1, 20 * 2); 801 802 /* These flags affect shader compilation. */ 803 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \ 804 DBG(SI_SCHED) | \ 805 DBG(GISEL) | \ 806 DBG(UNSAFE_MATH) | \ 807 DBG(NIR)) 808 uint64_t shader_debug_flags = sscreen->debug_flags & 809 ALL_FLAGS; 810 811 /* Add the high bits of 32-bit addresses, which affects 812 * how 32-bit addresses are expanded to 64 bits. 813 */ 814 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX); 815 shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32; 816 817 sscreen->disk_shader_cache = 818 disk_cache_create(sscreen->info.name, 819 cache_id, 820 shader_debug_flags); 821} 822 823struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, 824 const struct pipe_screen_config *config) 825{ 826 struct si_screen *sscreen = CALLOC_STRUCT(si_screen); 827 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i; 828 829 if (!sscreen) { 830 return NULL; 831 } 832 833 sscreen->ws = ws; 834 ws->query_info(ws, &sscreen->info); 835 si_handle_env_var_force_family(sscreen); 836 837 if (sscreen->info.chip_class >= GFX9) { 838 sscreen->se_tile_repeat = 32 * sscreen->info.max_se; 839 } else { 840 ac_get_raster_config(&sscreen->info, 841 &sscreen->pa_sc_raster_config, 842 &sscreen->pa_sc_raster_config_1, 843 &sscreen->se_tile_repeat); 844 } 845 846 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", 847 debug_options, 0); 848 849 /* Set functions first. */ 850 sscreen->b.context_create = si_pipe_create_context; 851 sscreen->b.destroy = si_destroy_screen; 852 853 si_init_screen_get_functions(sscreen); 854 si_init_screen_buffer_functions(sscreen); 855 si_init_screen_fence_functions(sscreen); 856 si_init_screen_state_functions(sscreen); 857 si_init_screen_texture_functions(sscreen); 858 si_init_screen_query_functions(sscreen); 859 860 /* Set these flags in debug_flags early, so that the shader cache takes 861 * them into account. 862 */ 863 if (driQueryOptionb(config->options, 864 "glsl_correct_derivatives_after_discard")) 865 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL); 866 if (driQueryOptionb(config->options, "radeonsi_enable_sisched")) 867 sscreen->debug_flags |= DBG(SI_SCHED); 868 if (driQueryOptionb(config->options, "radeonsi_enable_nir")) 869 sscreen->debug_flags |= DBG(NIR); 870 871 if (sscreen->debug_flags & DBG(INFO)) 872 ac_print_gpu_info(&sscreen->info); 873 874 slab_create_parent(&sscreen->pool_transfers, 875 sizeof(struct si_transfer), 64); 876 877 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1)); 878 if (sscreen->force_aniso >= 0) { 879 printf("radeonsi: Forcing anisotropy filter to %ix\n", 880 /* round down to a power of two */ 881 1 << util_logbase2(sscreen->force_aniso)); 882 } 883 884 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain); 885 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain); 886 887 si_init_gs_info(sscreen); 888 if (!si_init_shader_cache(sscreen)) { 889 FREE(sscreen); 890 return NULL; 891 } 892 893 si_disk_cache_create(sscreen); 894 895 /* Determine the number of shader compiler threads. */ 896 hw_threads = sysconf(_SC_NPROCESSORS_ONLN); 897 898 if (hw_threads >= 12) { 899 num_comp_hi_threads = hw_threads * 3 / 4; 900 num_comp_lo_threads = hw_threads / 3; 901 } else if (hw_threads >= 6) { 902 num_comp_hi_threads = hw_threads - 2; 903 num_comp_lo_threads = hw_threads / 2; 904 } else if (hw_threads >= 2) { 905 num_comp_hi_threads = hw_threads - 1; 906 num_comp_lo_threads = hw_threads / 2; 907 } else { 908 num_comp_hi_threads = 1; 909 num_comp_lo_threads = 1; 910 } 911 912 num_comp_hi_threads = MIN2(num_comp_hi_threads, 913 ARRAY_SIZE(sscreen->compiler)); 914 num_comp_lo_threads = MIN2(num_comp_lo_threads, 915 ARRAY_SIZE(sscreen->compiler_lowp)); 916 917 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh", 918 64, num_comp_hi_threads, 919 UTIL_QUEUE_INIT_RESIZE_IF_FULL | 920 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) { 921 si_destroy_shader_cache(sscreen); 922 FREE(sscreen); 923 return NULL; 924 } 925 926 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority, 927 "shlo", 928 64, num_comp_lo_threads, 929 UTIL_QUEUE_INIT_RESIZE_IF_FULL | 930 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY | 931 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) { 932 si_destroy_shader_cache(sscreen); 933 FREE(sscreen); 934 return NULL; 935 } 936 937 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false)) 938 si_init_perfcounters(sscreen); 939 940 /* Determine tessellation ring info. */ 941 bool double_offchip_buffers = sscreen->info.chip_class >= CIK && 942 sscreen->info.family != CHIP_CARRIZO && 943 sscreen->info.family != CHIP_STONEY; 944 /* This must be one less than the maximum number due to a hw limitation. 945 * Various hardware bugs in SI, CIK, and GFX9 need this. 946 */ 947 unsigned max_offchip_buffers_per_se; 948 949 /* Only certain chips can use the maximum value. */ 950 if (sscreen->info.family == CHIP_VEGA12 || 951 sscreen->info.family == CHIP_VEGA20) 952 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64; 953 else 954 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63; 955 956 unsigned max_offchip_buffers = max_offchip_buffers_per_se * 957 sscreen->info.max_se; 958 unsigned offchip_granularity; 959 960 /* Hawaii has a bug with offchip buffers > 256 that can be worked 961 * around by setting 4K granularity. 962 */ 963 if (sscreen->info.family == CHIP_HAWAII) { 964 sscreen->tess_offchip_block_dw_size = 4096; 965 offchip_granularity = V_03093C_X_4K_DWORDS; 966 } else { 967 sscreen->tess_offchip_block_dw_size = 8192; 968 offchip_granularity = V_03093C_X_8K_DWORDS; 969 } 970 971 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se; 972 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0); 973 sscreen->tess_offchip_ring_size = max_offchip_buffers * 974 sscreen->tess_offchip_block_dw_size * 4; 975 976 if (sscreen->info.chip_class >= CIK) { 977 if (sscreen->info.chip_class >= VI) 978 --max_offchip_buffers; 979 sscreen->vgt_hs_offchip_param = 980 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) | 981 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity); 982 } else { 983 assert(offchip_granularity == V_03093C_X_8K_DWORDS); 984 sscreen->vgt_hs_offchip_param = 985 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers); 986 } 987 988 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs 989 * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc. 990 * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/ 991 sscreen->has_clear_state = sscreen->info.chip_class >= CIK && 992 sscreen->info.drm_major == 3; 993 994 sscreen->has_distributed_tess = 995 sscreen->info.chip_class >= VI && 996 sscreen->info.max_se >= 2; 997 998 sscreen->has_draw_indirect_multi = 999 (sscreen->info.family >= CHIP_POLARIS10) || 1000 (sscreen->info.chip_class == VI && 1001 sscreen->info.pfp_fw_version >= 121 && 1002 sscreen->info.me_fw_version >= 87) || 1003 (sscreen->info.chip_class == CIK && 1004 sscreen->info.pfp_fw_version >= 211 && 1005 sscreen->info.me_fw_version >= 173) || 1006 (sscreen->info.chip_class == SI && 1007 sscreen->info.pfp_fw_version >= 79 && 1008 sscreen->info.me_fw_version >= 142); 1009 1010 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI && 1011 sscreen->info.max_se >= 2 && 1012 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER)); 1013 sscreen->assume_no_z_fights = 1014 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights"); 1015 sscreen->commutative_blend_add = 1016 driQueryOptionb(config->options, "radeonsi_commutative_blend_add"); 1017 sscreen->clear_db_cache_before_clear = 1018 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear"); 1019 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 && 1020 sscreen->info.family <= CHIP_POLARIS12) || 1021 sscreen->info.family == CHIP_VEGA10 || 1022 sscreen->info.family == CHIP_RAVEN; 1023 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 || 1024 sscreen->info.family == CHIP_RAVEN; 1025 1026 if (sscreen->debug_flags & DBG(DPBB)) { 1027 sscreen->dpbb_allowed = true; 1028 } else { 1029 /* Only enable primitive binning on APUs by default. */ 1030 /* TODO: Investigate if binning is profitable on Vega12. */ 1031 sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB)) && 1032 (sscreen->info.family == CHIP_RAVEN || 1033 sscreen->info.family == CHIP_RAVEN2); 1034 } 1035 1036 if (sscreen->debug_flags & DBG(DFSM)) { 1037 sscreen->dfsm_allowed = sscreen->dpbb_allowed; 1038 } else { 1039 sscreen->dfsm_allowed = sscreen->dpbb_allowed && 1040 !(sscreen->debug_flags & DBG(NO_DFSM)); 1041 } 1042 1043 /* While it would be nice not to have this flag, we are constrained 1044 * by the reality that LLVM 5.0 doesn't have working VGPR indexing 1045 * on GFX9. 1046 */ 1047 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI; 1048 1049 /* Some chips have RB+ registers, but don't support RB+. Those must 1050 * always disable it. 1051 */ 1052 if (sscreen->info.family == CHIP_STONEY || 1053 sscreen->info.chip_class >= GFX9) { 1054 sscreen->has_rbplus = true; 1055 1056 sscreen->rbplus_allowed = 1057 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) && 1058 (sscreen->info.family == CHIP_STONEY || 1059 sscreen->info.family == CHIP_VEGA12 || 1060 sscreen->info.family == CHIP_RAVEN || 1061 sscreen->info.family == CHIP_RAVEN2); 1062 } 1063 1064 sscreen->dcc_msaa_allowed = 1065 !(sscreen->debug_flags & DBG(NO_DCC_MSAA)); 1066 1067 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI; 1068 1069 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain); 1070 sscreen->use_monolithic_shaders = 1071 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0; 1072 1073 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 | 1074 SI_CONTEXT_INV_VMEM_L1; 1075 if (sscreen->info.chip_class <= VI) { 1076 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2; 1077 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; 1078 } 1079 1080 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false)) 1081 sscreen->debug_flags |= DBG_ALL_SHADERS; 1082 1083 /* Syntax: 1084 * EQAA=s,z,c 1085 * Example: 1086 * EQAA=8,4,2 1087 1088 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples. 1089 * Constraints: 1090 * s >= z >= c (ignoring this only wastes memory) 1091 * s = [2..16] 1092 * z = [2..8] 1093 * c = [2..8] 1094 * 1095 * Only MSAA color and depth buffers are overriden. 1096 */ 1097 if (sscreen->info.has_eqaa_surface_allocator) { 1098 const char *eqaa = debug_get_option("EQAA", NULL); 1099 unsigned s,z,f; 1100 1101 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) { 1102 sscreen->eqaa_force_coverage_samples = s; 1103 sscreen->eqaa_force_z_samples = z; 1104 sscreen->eqaa_force_color_samples = f; 1105 } 1106 } 1107 1108 for (i = 0; i < num_comp_hi_threads; i++) 1109 si_init_compiler(sscreen, &sscreen->compiler[i]); 1110 for (i = 0; i < num_comp_lo_threads; i++) 1111 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]); 1112 1113 /* Create the auxiliary context. This must be done last. */ 1114 sscreen->aux_context = si_create_context(&sscreen->b, 0); 1115 1116 if (sscreen->debug_flags & DBG(TEST_DMA)) 1117 si_test_dma(sscreen); 1118 1119 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) { 1120 si_test_dma_perf(sscreen); 1121 } 1122 1123 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) | 1124 DBG(TEST_VMFAULT_SDMA) | 1125 DBG(TEST_VMFAULT_SHADER))) 1126 si_test_vmfault(sscreen); 1127 1128 if (sscreen->debug_flags & DBG(TEST_GDS)) 1129 si_test_gds((struct si_context*)sscreen->aux_context); 1130 1131 return &sscreen->b; 1132} 1133