101e04c3fSmrg/*
201e04c3fSmrg * Copyright © 2014-2018 NVIDIA Corporation
301e04c3fSmrg *
401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a
501e04c3fSmrg * copy of this software and associated documentation files (the "Software"),
601e04c3fSmrg * to deal in the Software without restriction, including without limitation
701e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
801e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the
901e04c3fSmrg * Software is furnished to do so, subject to the following conditions:
1001e04c3fSmrg *
1101e04c3fSmrg * The above copyright notice and this permission notice (including the next
1201e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the
1301e04c3fSmrg * Software.
1401e04c3fSmrg *
1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1801e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1901e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2001e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2101e04c3fSmrg * IN THE SOFTWARE.
2201e04c3fSmrg */
2301e04c3fSmrg
2401e04c3fSmrg#ifndef TEGRA_CONTEXT_H
2501e04c3fSmrg#define TEGRA_CONTEXT_H
2601e04c3fSmrg
2701e04c3fSmrg#include "pipe/p_context.h"
2801e04c3fSmrg#include "pipe/p_state.h"
2901e04c3fSmrg
3001e04c3fSmrgstruct tegra_screen;
3101e04c3fSmrg
3201e04c3fSmrgstruct tegra_context {
3301e04c3fSmrg   struct pipe_context base;
3401e04c3fSmrg   struct pipe_context *gpu;
3501e04c3fSmrg};
3601e04c3fSmrg
3701e04c3fSmrgstatic inline struct tegra_context *
3801e04c3fSmrgto_tegra_context(struct pipe_context *context)
3901e04c3fSmrg{
4001e04c3fSmrg   return (struct tegra_context *)context;
4101e04c3fSmrg}
4201e04c3fSmrg
4301e04c3fSmrgstruct pipe_context *
4401e04c3fSmrgtegra_screen_context_create(struct pipe_screen *pscreen, void *priv,
4501e04c3fSmrg                            unsigned int flags);
4601e04c3fSmrg
4701e04c3fSmrgstruct tegra_sampler_view {
4801e04c3fSmrg   struct pipe_sampler_view base;
4901e04c3fSmrg   struct pipe_sampler_view *gpu;
507ec681f3Smrg   unsigned int refcount;
5101e04c3fSmrg};
5201e04c3fSmrg
5301e04c3fSmrgstatic inline struct tegra_sampler_view *
5401e04c3fSmrgto_tegra_sampler_view(struct pipe_sampler_view *view)
5501e04c3fSmrg{
5601e04c3fSmrg   return (struct tegra_sampler_view *)view;
5701e04c3fSmrg}
5801e04c3fSmrg
5901e04c3fSmrgstatic inline struct pipe_sampler_view *
6001e04c3fSmrgtegra_sampler_view_unwrap(struct pipe_sampler_view *view)
6101e04c3fSmrg{
6201e04c3fSmrg   if (!view)
6301e04c3fSmrg      return NULL;
6401e04c3fSmrg
6501e04c3fSmrg   return to_tegra_sampler_view(view)->gpu;
6601e04c3fSmrg}
6701e04c3fSmrg
6801e04c3fSmrgstruct tegra_transfer {
6901e04c3fSmrg   struct pipe_transfer base;
7001e04c3fSmrg   struct pipe_transfer *gpu;
7101e04c3fSmrg
7201e04c3fSmrg   unsigned int count;
7301e04c3fSmrg   void *map;
7401e04c3fSmrg};
7501e04c3fSmrg
7601e04c3fSmrgstatic inline struct tegra_transfer *
7701e04c3fSmrgto_tegra_transfer(struct pipe_transfer *transfer)
7801e04c3fSmrg{
7901e04c3fSmrg   return (struct tegra_transfer *)transfer;
8001e04c3fSmrg}
8101e04c3fSmrg
8201e04c3fSmrg#endif /* TEGRA_SCREEN_H */
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