vc4_qpu.h revision af69d88d 
1/*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#ifndef VC4_QPU_H
25#define VC4_QPU_H
26
27#include <stdint.h>
28
29#include "util/u_math.h"
30
31#include "vc4_qpu_defines.h"
32
33struct qpu_reg {
34        enum qpu_mux mux;
35        uint8_t addr;
36};
37
38static inline struct qpu_reg
39qpu_rn(int n)
40{
41        struct qpu_reg r = {
42                QPU_MUX_R0 + n,
43                0,
44        };
45
46        return r;
47}
48
49static inline struct qpu_reg
50qpu_ra(int addr)
51{
52        struct qpu_reg r = {
53                QPU_MUX_A,
54                addr,
55        };
56
57        return r;
58}
59
60static inline struct qpu_reg
61qpu_rb(int addr)
62{
63        struct qpu_reg r = {
64                QPU_MUX_B,
65                addr,
66        };
67
68        return r;
69}
70
71static inline struct qpu_reg
72qpu_vary()
73{
74        struct qpu_reg r = {
75                QPU_MUX_A,
76                QPU_R_VARY,
77        };
78
79        return r;
80}
81
82static inline struct qpu_reg
83qpu_unif()
84{
85        struct qpu_reg r = {
86                QPU_MUX_A,
87                QPU_R_UNIF,
88        };
89
90        return r;
91}
92
93static inline struct qpu_reg
94qpu_vrsetup()
95{
96        return qpu_ra(QPU_W_VPMVCD_SETUP);
97}
98
99static inline struct qpu_reg
100qpu_vwsetup()
101{
102        return qpu_rb(QPU_W_VPMVCD_SETUP);
103}
104
105static inline struct qpu_reg
106qpu_tlbc()
107{
108        struct qpu_reg r = {
109                QPU_MUX_A,
110                QPU_W_TLB_COLOR_ALL,
111        };
112
113        return r;
114}
115
116static inline struct qpu_reg qpu_r0(void) { return qpu_rn(0); }
117static inline struct qpu_reg qpu_r1(void) { return qpu_rn(1); }
118static inline struct qpu_reg qpu_r2(void) { return qpu_rn(2); }
119static inline struct qpu_reg qpu_r3(void) { return qpu_rn(3); }
120static inline struct qpu_reg qpu_r4(void) { return qpu_rn(4); }
121static inline struct qpu_reg qpu_r5(void) { return qpu_rn(5); }
122
123uint64_t qpu_a_MOV(struct qpu_reg dst, struct qpu_reg src);
124uint64_t qpu_m_MOV(struct qpu_reg dst, struct qpu_reg src);
125uint64_t qpu_a_NOP(void);
126uint64_t qpu_m_NOP(void);
127uint64_t qpu_a_alu2(enum qpu_op_add op, struct qpu_reg dst,
128                    struct qpu_reg src0, struct qpu_reg src1);
129uint64_t qpu_m_alu2(enum qpu_op_mul op, struct qpu_reg dst,
130                    struct qpu_reg src0, struct qpu_reg src1);
131uint64_t qpu_inst(uint64_t add, uint64_t mul);
132uint64_t qpu_load_imm_ui(struct qpu_reg dst, uint32_t val);
133uint64_t qpu_set_sig(uint64_t inst, uint32_t sig);
134
135static inline uint64_t
136qpu_load_imm_f(struct qpu_reg dst, float val)
137{
138        return qpu_load_imm_ui(dst, fui(val));
139}
140
141#define A_ALU2(op)                                                       \
142static inline uint64_t                                                   \
143qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
144{                                                                        \
145        return qpu_a_alu2(QPU_A_##op, dst, src0, src1);                  \
146}
147
148#define M_ALU2(op)                                                       \
149static inline uint64_t                                                   \
150qpu_m_##op(struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) \
151{                                                                        \
152        return qpu_m_alu2(QPU_M_##op, dst, src0, src1);                  \
153}
154
155#define A_ALU1(op)                                                       \
156static inline uint64_t                                                   \
157qpu_a_##op(struct qpu_reg dst, struct qpu_reg src0)                      \
158{                                                                        \
159        return qpu_a_alu2(QPU_A_##op, dst, src0, src0);                  \
160}
161
162/*A_ALU2(NOP) */
163A_ALU2(FADD)
164A_ALU2(FSUB)
165A_ALU2(FMIN)
166A_ALU2(FMAX)
167A_ALU2(FMINABS)
168A_ALU2(FMAXABS)
169A_ALU1(FTOI)
170A_ALU1(ITOF)
171A_ALU2(ADD)
172A_ALU2(SUB)
173A_ALU2(SHR)
174A_ALU2(ASR)
175A_ALU2(ROR)
176A_ALU2(SHL)
177A_ALU2(MIN)
178A_ALU2(MAX)
179A_ALU2(AND)
180A_ALU2(OR)
181A_ALU2(XOR)
182A_ALU1(NOT)
183A_ALU1(CLZ)
184A_ALU2(V8ADDS)
185A_ALU2(V8SUBS)
186
187/* M_ALU2(NOP) */
188M_ALU2(FMUL)
189M_ALU2(MUL24)
190M_ALU2(V8MULD)
191M_ALU2(V8MIN)
192M_ALU2(V8MAX)
193M_ALU2(V8ADDS)
194M_ALU2(V8SUBS)
195
196void
197vc4_qpu_disasm(const uint64_t *instructions, int num_instructions);
198
199void
200vc4_qpu_validate(uint64_t *insts, uint32_t num_inst);
201
202#endif /* VC4_QPU_H */
203