101e04c3fSmrg/* 201e04c3fSmrg * Copyright 2014, 2015 Red Hat. 301e04c3fSmrg * 401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a 501e04c3fSmrg * copy of this software and associated documentation files (the "Software"), 601e04c3fSmrg * to deal in the Software without restriction, including without limitation 701e04c3fSmrg * on the rights to use, copy, modify, merge, publish, distribute, sub 801e04c3fSmrg * license, and/or sell copies of the Software, and to permit persons to whom 901e04c3fSmrg * the Software is furnished to do so, subject to the following conditions: 1001e04c3fSmrg * 1101e04c3fSmrg * The above copyright notice and this permission notice (including the next 1201e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the 1301e04c3fSmrg * Software. 1401e04c3fSmrg * 1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 1801e04c3fSmrg * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 1901e04c3fSmrg * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 2001e04c3fSmrg * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 2101e04c3fSmrg * USE OR OTHER DEALINGS IN THE SOFTWARE. 2201e04c3fSmrg */ 2301e04c3fSmrg#ifndef VIRGL_WINSYS_H 2401e04c3fSmrg#define VIRGL_WINSYS_H 2501e04c3fSmrg 2601e04c3fSmrg#include "pipe/p_defines.h" 277ec681f3Smrg#include "virtio-gpu/virgl_hw.h" 2801e04c3fSmrg 2901e04c3fSmrgstruct pipe_box; 3001e04c3fSmrgstruct pipe_fence_handle; 3101e04c3fSmrgstruct winsys_handle; 3201e04c3fSmrgstruct virgl_hw_res; 3301e04c3fSmrg 349f464c52Smaya#define VIRGL_MAX_TBUF_DWORDS 1024 359f464c52Smaya#define VIRGL_MAX_CMDBUF_DWORDS ((64 * 1024) + VIRGL_MAX_TBUF_DWORDS) 367ec681f3Smrg#define VIRGL_MAX_PLANE_COUNT 3 3701e04c3fSmrg 3801e04c3fSmrgstruct virgl_drm_caps { 3901e04c3fSmrg union virgl_caps caps; 4001e04c3fSmrg}; 4101e04c3fSmrg 4201e04c3fSmrgstruct virgl_cmd_buf { 4301e04c3fSmrg unsigned cdw; 4401e04c3fSmrg uint32_t *buf; 4501e04c3fSmrg}; 4601e04c3fSmrg 4701e04c3fSmrgstruct virgl_winsys { 4801e04c3fSmrg unsigned pci_id; 499f464c52Smaya int supports_fences; /* In/Out fences are supported */ 509f464c52Smaya int supports_encoded_transfers; /* Encoded transfers are supported */ 517ec681f3Smrg int supports_coherent; /* Coherent memory is supported */ 5201e04c3fSmrg 5301e04c3fSmrg void (*destroy)(struct virgl_winsys *vws); 5401e04c3fSmrg 5501e04c3fSmrg int (*transfer_put)(struct virgl_winsys *vws, 5601e04c3fSmrg struct virgl_hw_res *res, 5701e04c3fSmrg const struct pipe_box *box, 5801e04c3fSmrg uint32_t stride, uint32_t layer_stride, 5901e04c3fSmrg uint32_t buf_offset, uint32_t level); 6001e04c3fSmrg 6101e04c3fSmrg int (*transfer_get)(struct virgl_winsys *vws, 6201e04c3fSmrg struct virgl_hw_res *res, 6301e04c3fSmrg const struct pipe_box *box, 6401e04c3fSmrg uint32_t stride, uint32_t layer_stride, 6501e04c3fSmrg uint32_t buf_offset, uint32_t level); 6601e04c3fSmrg 6701e04c3fSmrg struct virgl_hw_res *(*resource_create)(struct virgl_winsys *vws, 6801e04c3fSmrg enum pipe_texture_target target, 6901e04c3fSmrg uint32_t format, uint32_t bind, 7001e04c3fSmrg uint32_t width, uint32_t height, 7101e04c3fSmrg uint32_t depth, uint32_t array_size, 7201e04c3fSmrg uint32_t last_level, uint32_t nr_samples, 737ec681f3Smrg uint32_t flags, uint32_t size); 7401e04c3fSmrg 757ec681f3Smrg void (*resource_reference)(struct virgl_winsys *qws, 767ec681f3Smrg struct virgl_hw_res **dres, 777ec681f3Smrg struct virgl_hw_res *sres); 7801e04c3fSmrg 7901e04c3fSmrg void *(*resource_map)(struct virgl_winsys *vws, struct virgl_hw_res *res); 8001e04c3fSmrg void (*resource_wait)(struct virgl_winsys *vws, struct virgl_hw_res *res); 817ec681f3Smrg boolean (*resource_is_busy)(struct virgl_winsys *vws, 827ec681f3Smrg struct virgl_hw_res *res); 8301e04c3fSmrg 8401e04c3fSmrg struct virgl_hw_res *(*resource_create_from_handle)(struct virgl_winsys *vws, 857ec681f3Smrg struct winsys_handle *whandle, 867ec681f3Smrg uint32_t *plane, 877ec681f3Smrg uint32_t *stride, 887ec681f3Smrg uint32_t *plane_offset, 897ec681f3Smrg uint64_t *modifier, 907ec681f3Smrg uint32_t *blob_mem); 917ec681f3Smrg void (*resource_set_type)(struct virgl_winsys *vws, 927ec681f3Smrg struct virgl_hw_res *res, 937ec681f3Smrg uint32_t format, uint32_t bind, 947ec681f3Smrg uint32_t width, uint32_t height, 957ec681f3Smrg uint32_t usage, uint64_t modifier, 967ec681f3Smrg uint32_t plane_count, 977ec681f3Smrg const uint32_t *plane_strides, 987ec681f3Smrg const uint32_t *plane_offsets); 997ec681f3Smrg 10001e04c3fSmrg boolean (*resource_get_handle)(struct virgl_winsys *vws, 10101e04c3fSmrg struct virgl_hw_res *res, 10201e04c3fSmrg uint32_t stride, 10301e04c3fSmrg struct winsys_handle *whandle); 10401e04c3fSmrg 1059f464c52Smaya struct virgl_cmd_buf *(*cmd_buf_create)(struct virgl_winsys *ws, uint32_t size); 10601e04c3fSmrg void (*cmd_buf_destroy)(struct virgl_cmd_buf *buf); 10701e04c3fSmrg 10801e04c3fSmrg void (*emit_res)(struct virgl_winsys *vws, struct virgl_cmd_buf *buf, struct virgl_hw_res *res, boolean write_buffer); 1099f464c52Smaya int (*submit_cmd)(struct virgl_winsys *vws, struct virgl_cmd_buf *buf, 1109f464c52Smaya struct pipe_fence_handle **fence); 11101e04c3fSmrg 11201e04c3fSmrg boolean (*res_is_referenced)(struct virgl_winsys *vws, 11301e04c3fSmrg struct virgl_cmd_buf *buf, 11401e04c3fSmrg struct virgl_hw_res *res); 11501e04c3fSmrg 11601e04c3fSmrg int (*get_caps)(struct virgl_winsys *vws, struct virgl_drm_caps *caps); 11701e04c3fSmrg 11801e04c3fSmrg /* fence */ 1199f464c52Smaya struct pipe_fence_handle *(*cs_create_fence)(struct virgl_winsys *vws, int fd); 12001e04c3fSmrg bool (*fence_wait)(struct virgl_winsys *vws, 12101e04c3fSmrg struct pipe_fence_handle *fence, 12201e04c3fSmrg uint64_t timeout); 12301e04c3fSmrg 12401e04c3fSmrg void (*fence_reference)(struct virgl_winsys *vws, 12501e04c3fSmrg struct pipe_fence_handle **dst, 12601e04c3fSmrg struct pipe_fence_handle *src); 12701e04c3fSmrg 12801e04c3fSmrg /* for sw paths */ 12901e04c3fSmrg void (*flush_frontbuffer)(struct virgl_winsys *vws, 13001e04c3fSmrg struct virgl_hw_res *res, 13101e04c3fSmrg unsigned level, unsigned layer, 13201e04c3fSmrg void *winsys_drawable_handle, 13301e04c3fSmrg struct pipe_box *sub_box); 1349f464c52Smaya void (*fence_server_sync)(struct virgl_winsys *vws, 1359f464c52Smaya struct virgl_cmd_buf *cbuf, 1369f464c52Smaya struct pipe_fence_handle *fence); 1379f464c52Smaya 1389f464c52Smaya int (*fence_get_fd)(struct virgl_winsys *vws, 1399f464c52Smaya struct pipe_fence_handle *fence); 14001e04c3fSmrg}; 14101e04c3fSmrg 14201e04c3fSmrg/* this defaults all newer caps, 14301e04c3fSmrg * the kernel will overwrite these if newer version is available. 14401e04c3fSmrg */ 14501e04c3fSmrgstatic inline void virgl_ws_fill_new_caps_defaults(struct virgl_drm_caps *caps) 14601e04c3fSmrg{ 14701e04c3fSmrg caps->caps.v2.min_aliased_point_size = 1.f; 14801e04c3fSmrg caps->caps.v2.max_aliased_point_size = 255.f; 14901e04c3fSmrg caps->caps.v2.min_smooth_point_size = 1.f; 15001e04c3fSmrg caps->caps.v2.max_smooth_point_size = 190.f; 15101e04c3fSmrg caps->caps.v2.min_aliased_line_width = 1.f; 15201e04c3fSmrg caps->caps.v2.max_aliased_line_width = 10.f; 15301e04c3fSmrg caps->caps.v2.min_smooth_line_width = 0.f; 15401e04c3fSmrg caps->caps.v2.max_smooth_line_width = 10.f; 15501e04c3fSmrg caps->caps.v2.max_texture_lod_bias = 15.0f; 15601e04c3fSmrg caps->caps.v2.max_geom_output_vertices = 256; 15701e04c3fSmrg caps->caps.v2.max_geom_total_output_components = 1024; 15801e04c3fSmrg caps->caps.v2.max_vertex_outputs = 32; 15901e04c3fSmrg caps->caps.v2.max_vertex_attribs = 16; 16001e04c3fSmrg caps->caps.v2.max_shader_patch_varyings = 30; 16101e04c3fSmrg caps->caps.v2.min_texel_offset = -8; 16201e04c3fSmrg caps->caps.v2.max_texel_offset = 7; 16301e04c3fSmrg caps->caps.v2.min_texture_gather_offset = -8; 16401e04c3fSmrg caps->caps.v2.max_texture_gather_offset = 7; 16501e04c3fSmrg caps->caps.v2.texture_buffer_offset_alignment = 0; 16601e04c3fSmrg caps->caps.v2.uniform_buffer_offset_alignment = 256; 16701e04c3fSmrg caps->caps.v2.shader_buffer_offset_alignment = 32; 16801e04c3fSmrg caps->caps.v2.capability_bits = 0; 16901e04c3fSmrg caps->caps.v2.max_vertex_attrib_stride = 0; 17001e04c3fSmrg caps->caps.v2.max_image_samples = 0; 17101e04c3fSmrg caps->caps.v2.max_compute_work_group_invocations = 0; 17201e04c3fSmrg caps->caps.v2.max_compute_shared_memory_size = 0; 1739f464c52Smaya caps->caps.v2.host_feature_check_version = 0; 17401e04c3fSmrg} 1757ec681f3Smrg 1767ec681f3Smrgextern enum virgl_formats pipe_to_virgl_format(enum pipe_format format); 1777ec681f3Smrg 17801e04c3fSmrg#endif 179