17ec681f3Smrg/* 27ec681f3Smrg * Copyright © 2020 Intel Corporation 37ec681f3Smrg * 47ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a 57ec681f3Smrg * copy of this software and associated documentation files (the "Software"), 67ec681f3Smrg * to deal in the Software without restriction, including without limitation 77ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the 97ec681f3Smrg * Software is furnished to do so, subject to the following conditions: 107ec681f3Smrg * 117ec681f3Smrg * The above copyright notice and this permission notice (including the next 127ec681f3Smrg * paragraph) shall be included in all copies or substantial portions of the 137ec681f3Smrg * Software. 147ec681f3Smrg * 157ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 167ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 177ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 187ec681f3Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 197ec681f3Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 207ec681f3Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 217ec681f3Smrg * IN THE SOFTWARE. 227ec681f3Smrg */ 237ec681f3Smrg 247ec681f3Smrg#include "intel_sample_positions.h" 257ec681f3Smrg 267ec681f3Smrg/** 277ec681f3Smrg * 1x MSAA has a single sample at the center: (0.5, 0.5) -> (0x8, 0x8). 287ec681f3Smrg */ 297ec681f3Smrgconst struct intel_sample_position intel_sample_positions_1x[] = { 307ec681f3Smrg { 0.5, 0.5, }, 317ec681f3Smrg}; 327ec681f3Smrg 337ec681f3Smrg/** 347ec681f3Smrg * 2x MSAA sample positions are (0.25, 0.25) and (0.75, 0.75): 357ec681f3Smrg * 4 c 367ec681f3Smrg * 4 0 377ec681f3Smrg * c 1 387ec681f3Smrg */ 397ec681f3Smrgconst struct intel_sample_position intel_sample_positions_2x[] = { 407ec681f3Smrg { 0.75, 0.75 }, 417ec681f3Smrg { 0.25, 0.25 }, 427ec681f3Smrg}; 437ec681f3Smrg 447ec681f3Smrg/** 457ec681f3Smrg * Sample positions: 467ec681f3Smrg * 2 6 a e 477ec681f3Smrg * 2 0 487ec681f3Smrg * 6 1 497ec681f3Smrg * a 2 507ec681f3Smrg * e 3 517ec681f3Smrg */ 527ec681f3Smrgconst struct intel_sample_position intel_sample_positions_4x[] = { 537ec681f3Smrg { 0.375, 0.125 }, 547ec681f3Smrg { 0.875, 0.375 }, 557ec681f3Smrg { 0.125, 0.625 }, 567ec681f3Smrg { 0.625, 0.875 }, 577ec681f3Smrg}; 587ec681f3Smrg 597ec681f3Smrg/** 607ec681f3Smrg * Sample positions: 617ec681f3Smrg * 627ec681f3Smrg * From the Ivy Bridge PRM, Vol2 Part1 p304 (3DSTATE_MULTISAMPLE: 637ec681f3Smrg * Programming Notes): 647ec681f3Smrg * "When programming the sample offsets (for NUMSAMPLES_4 or _8 and 657ec681f3Smrg * MSRASTMODE_xxx_PATTERN), the order of the samples 0 to 3 (or 7 667ec681f3Smrg * for 8X) must have monotonically increasing distance from the 677ec681f3Smrg * pixel center. This is required to get the correct centroid 687ec681f3Smrg * computation in the device." 697ec681f3Smrg * 707ec681f3Smrg * Sample positions: 717ec681f3Smrg * 1 3 5 7 9 b d f 727ec681f3Smrg * 1 7 737ec681f3Smrg * 3 3 747ec681f3Smrg * 5 0 757ec681f3Smrg * 7 5 767ec681f3Smrg * 9 2 777ec681f3Smrg * b 1 787ec681f3Smrg * d 4 797ec681f3Smrg * f 6 807ec681f3Smrg */ 817ec681f3Smrgconst struct intel_sample_position intel_sample_positions_8x[] = { 827ec681f3Smrg { 0.5625, 0.3125 }, 837ec681f3Smrg { 0.4375, 0.6875 }, 847ec681f3Smrg { 0.8125, 0.5625 }, 857ec681f3Smrg { 0.3125, 0.1875 }, 867ec681f3Smrg { 0.1875, 0.8125 }, 877ec681f3Smrg { 0.0625, 0.4375 }, 887ec681f3Smrg { 0.6875, 0.9375 }, 897ec681f3Smrg { 0.9375, 0.0625 }, 907ec681f3Smrg}; 917ec681f3Smrg 927ec681f3Smrg/** 937ec681f3Smrg * Sample positions: 947ec681f3Smrg * 957ec681f3Smrg * 0 1 2 3 4 5 6 7 8 9 a b c d e f 967ec681f3Smrg * 0 15 977ec681f3Smrg * 1 9 987ec681f3Smrg * 2 10 997ec681f3Smrg * 3 7 1007ec681f3Smrg * 4 13 1017ec681f3Smrg * 5 1 1027ec681f3Smrg * 6 4 1037ec681f3Smrg * 7 3 1047ec681f3Smrg * 8 12 1057ec681f3Smrg * 9 0 1067ec681f3Smrg * a 2 1077ec681f3Smrg * b 6 1087ec681f3Smrg * c 11 1097ec681f3Smrg * d 5 1107ec681f3Smrg * e 8 1117ec681f3Smrg * f 14 1127ec681f3Smrg */ 1137ec681f3Smrgconst struct intel_sample_position intel_sample_positions_16x[] = { 1147ec681f3Smrg { 0.5625, 0.5625 }, 1157ec681f3Smrg { 0.4375, 0.3125 }, 1167ec681f3Smrg { 0.3125, 0.6250 }, 1177ec681f3Smrg { 0.7500, 0.4375 }, 1187ec681f3Smrg { 0.1875, 0.3750 }, 1197ec681f3Smrg { 0.6250, 0.8125 }, 1207ec681f3Smrg { 0.8125, 0.6875 }, 1217ec681f3Smrg { 0.6875, 0.1875 }, 1227ec681f3Smrg { 0.3750, 0.8750 }, 1237ec681f3Smrg { 0.5000, 0.0625 }, 1247ec681f3Smrg { 0.2500, 0.1250 }, 1257ec681f3Smrg { 0.1250, 0.7500 }, 1267ec681f3Smrg { 0.0000, 0.5000 }, 1277ec681f3Smrg { 0.9375, 0.2500 }, 1287ec681f3Smrg { 0.8750, 0.9375 }, 1297ec681f3Smrg { 0.0625, 0.0000 }, 1307ec681f3Smrg}; 131