brw_eu_compact.c revision 01e04c3f 
1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24/** @file brw_eu_compact.c
25 *
26 * Instruction compaction is a feature of G45 and newer hardware that allows
27 * for a smaller instruction encoding.
28 *
29 * The instruction cache is on the order of 32KB, and many programs generate
30 * far more instructions than that.  The instruction cache is built to barely
31 * keep up with instruction dispatch ability in cache hit cases -- L1
32 * instruction cache misses that still hit in the next level could limit
33 * throughput by around 50%.
34 *
35 * The idea of instruction compaction is that most instructions use a tiny
36 * subset of the GPU functionality, so we can encode what would be a 16 byte
37 * instruction in 8 bytes using some lookup tables for various fields.
38 *
39 *
40 * Instruction compaction capabilities vary subtly by generation.
41 *
42 * G45's support for instruction compaction is very limited. Jump counts on
43 * this generation are in units of 16-byte uncompacted instructions. As such,
44 * all jump targets must be 16-byte aligned. Also, all instructions must be
45 * naturally aligned, i.e. uncompacted instructions must be 16-byte aligned.
46 * A G45-only instruction, NENOP, must be used to provide padding to align
47 * uncompacted instructions.
48 *
49 * Gen5 removes these restrictions and changes jump counts to be in units of
50 * 8-byte compacted instructions, allowing jump targets to be only 8-byte
51 * aligned. Uncompacted instructions can also be placed on 8-byte boundaries.
52 *
53 * Gen6 adds the ability to compact instructions with a limited range of
54 * immediate values. Compactable immediates have 12 unrestricted bits, and a
55 * 13th bit that's replicated through the high 20 bits, to create the 32-bit
56 * value of DW3 in the uncompacted instruction word.
57 *
58 * On Gen7 we can compact some control flow instructions with a small positive
59 * immediate in the low bits of DW3, like ENDIF with the JIP field. Other
60 * control flow instructions with UIP cannot be compacted, because of the
61 * replicated 13th bit. No control flow instructions can be compacted on Gen6
62 * since the jump count field is not in DW3.
63 *
64 *    break    JIP/UIP
65 *    cont     JIP/UIP
66 *    halt     JIP/UIP
67 *    if       JIP/UIP
68 *    else     JIP (plus UIP on BDW+)
69 *    endif    JIP
70 *    while    JIP (must be negative)
71 *
72 * Gen 8 adds support for compacting 3-src instructions.
73 */
74
75#include "brw_eu.h"
76#include "brw_shader.h"
77#include "brw_disasm_info.h"
78#include "common/gen_debug.h"
79
80static const uint32_t g45_control_index_table[32] = {
81   0b00000000000000000,
82   0b01000000000000000,
83   0b00110000000000000,
84   0b00000000000000010,
85   0b00100000000000000,
86   0b00010000000000000,
87   0b01000000000100000,
88   0b01000000100000000,
89   0b01010000000100000,
90   0b00000000100000010,
91   0b11000000000000000,
92   0b00001000100000010,
93   0b01001000100000000,
94   0b00000000100000000,
95   0b11000000000100000,
96   0b00001000100000000,
97   0b10110000000000000,
98   0b11010000000100000,
99   0b00110000100000000,
100   0b00100000100000000,
101   0b01000000000001000,
102   0b01000000000000100,
103   0b00111100000000000,
104   0b00101011000000000,
105   0b00110000000010000,
106   0b00010000100000000,
107   0b01000000000100100,
108   0b01000000000101000,
109   0b00110000000000110,
110   0b00000000000001010,
111   0b01010000000101000,
112   0b01010000000100100
113};
114
115static const uint32_t g45_datatype_table[32] = {
116   0b001000000000100001,
117   0b001011010110101101,
118   0b001000001000110001,
119   0b001111011110111101,
120   0b001011010110101100,
121   0b001000000110101101,
122   0b001000000000100000,
123   0b010100010110110001,
124   0b001100011000101101,
125   0b001000000000100010,
126   0b001000001000110110,
127   0b010000001000110001,
128   0b001000001000110010,
129   0b011000001000110010,
130   0b001111011110111100,
131   0b001000000100101000,
132   0b010100011000110001,
133   0b001010010100101001,
134   0b001000001000101001,
135   0b010000001000110110,
136   0b101000001000110001,
137   0b001011011000101101,
138   0b001000000100001001,
139   0b001011011000101100,
140   0b110100011000110001,
141   0b001000001110111101,
142   0b110000001000110001,
143   0b011000000100101010,
144   0b101000001000101001,
145   0b001011010110001100,
146   0b001000000110100001,
147   0b001010010100001000
148};
149
150static const uint16_t g45_subreg_table[32] = {
151   0b000000000000000,
152   0b000000010000000,
153   0b000001000000000,
154   0b000100000000000,
155   0b000000000100000,
156   0b100000000000000,
157   0b000000000010000,
158   0b001100000000000,
159   0b001010000000000,
160   0b000000100000000,
161   0b001000000000000,
162   0b000000000001000,
163   0b000000001000000,
164   0b000000000000001,
165   0b000010000000000,
166   0b000000010100000,
167   0b000000000000111,
168   0b000001000100000,
169   0b011000000000000,
170   0b000000110000000,
171   0b000000000000010,
172   0b000000000000100,
173   0b000000001100000,
174   0b000100000000010,
175   0b001110011000110,
176   0b001110100001000,
177   0b000110011000110,
178   0b000001000011000,
179   0b000110010000100,
180   0b001100000000110,
181   0b000000010000110,
182   0b000001000110000
183};
184
185static const uint16_t g45_src_index_table[32] = {
186   0b000000000000,
187   0b010001101000,
188   0b010110001000,
189   0b011010010000,
190   0b001101001000,
191   0b010110001010,
192   0b010101110000,
193   0b011001111000,
194   0b001000101000,
195   0b000000101000,
196   0b010001010000,
197   0b111101101100,
198   0b010110001100,
199   0b010001101100,
200   0b011010010100,
201   0b010001001100,
202   0b001100101000,
203   0b000000000010,
204   0b111101001100,
205   0b011001101000,
206   0b010101001000,
207   0b000000000100,
208   0b000000101100,
209   0b010001101010,
210   0b000000111000,
211   0b010101011000,
212   0b000100100000,
213   0b010110000000,
214   0b010000000100,
215   0b010000111000,
216   0b000101100000,
217   0b111101110100
218};
219
220static const uint32_t gen6_control_index_table[32] = {
221   0b00000000000000000,
222   0b01000000000000000,
223   0b00110000000000000,
224   0b00000000100000000,
225   0b00010000000000000,
226   0b00001000100000000,
227   0b00000000100000010,
228   0b00000000000000010,
229   0b01000000100000000,
230   0b01010000000000000,
231   0b10110000000000000,
232   0b00100000000000000,
233   0b11010000000000000,
234   0b11000000000000000,
235   0b01001000100000000,
236   0b01000000000001000,
237   0b01000000000000100,
238   0b00000000000001000,
239   0b00000000000000100,
240   0b00111000100000000,
241   0b00001000100000010,
242   0b00110000100000000,
243   0b00110000000000001,
244   0b00100000000000001,
245   0b00110000000000010,
246   0b00110000000000101,
247   0b00110000000001001,
248   0b00110000000010000,
249   0b00110000000000011,
250   0b00110000000000100,
251   0b00110000100001000,
252   0b00100000000001001
253};
254
255static const uint32_t gen6_datatype_table[32] = {
256   0b001001110000000000,
257   0b001000110000100000,
258   0b001001110000000001,
259   0b001000000001100000,
260   0b001010110100101001,
261   0b001000000110101101,
262   0b001100011000101100,
263   0b001011110110101101,
264   0b001000000111101100,
265   0b001000000001100001,
266   0b001000110010100101,
267   0b001000000001000001,
268   0b001000001000110001,
269   0b001000001000101001,
270   0b001000000000100000,
271   0b001000001000110010,
272   0b001010010100101001,
273   0b001011010010100101,
274   0b001000000110100101,
275   0b001100011000101001,
276   0b001011011000101100,
277   0b001011010110100101,
278   0b001011110110100101,
279   0b001111011110111101,
280   0b001111011110111100,
281   0b001111011110111101,
282   0b001111011110011101,
283   0b001111011110111110,
284   0b001000000000100001,
285   0b001000000000100010,
286   0b001001111111011101,
287   0b001000001110111110,
288};
289
290static const uint16_t gen6_subreg_table[32] = {
291   0b000000000000000,
292   0b000000000000100,
293   0b000000110000000,
294   0b111000000000000,
295   0b011110000001000,
296   0b000010000000000,
297   0b000000000010000,
298   0b000110000001100,
299   0b001000000000000,
300   0b000001000000000,
301   0b000001010010100,
302   0b000000001010110,
303   0b010000000000000,
304   0b110000000000000,
305   0b000100000000000,
306   0b000000010000000,
307   0b000000000001000,
308   0b100000000000000,
309   0b000001010000000,
310   0b001010000000000,
311   0b001100000000000,
312   0b000000001010100,
313   0b101101010010100,
314   0b010100000000000,
315   0b000000010001111,
316   0b011000000000000,
317   0b111110000000000,
318   0b101000000000000,
319   0b000000000001111,
320   0b000100010001111,
321   0b001000010001111,
322   0b000110000000000,
323};
324
325static const uint16_t gen6_src_index_table[32] = {
326   0b000000000000,
327   0b010110001000,
328   0b010001101000,
329   0b001000101000,
330   0b011010010000,
331   0b000100100000,
332   0b010001101100,
333   0b010101110000,
334   0b011001111000,
335   0b001100101000,
336   0b010110001100,
337   0b001000100000,
338   0b010110001010,
339   0b000000000010,
340   0b010101010000,
341   0b010101101000,
342   0b111101001100,
343   0b111100101100,
344   0b011001110000,
345   0b010110001001,
346   0b010101011000,
347   0b001101001000,
348   0b010000101100,
349   0b010000000000,
350   0b001101110000,
351   0b001100010000,
352   0b001100000000,
353   0b010001101010,
354   0b001101111000,
355   0b000001110000,
356   0b001100100000,
357   0b001101010000,
358};
359
360static const uint32_t gen7_control_index_table[32] = {
361   0b0000000000000000010,
362   0b0000100000000000000,
363   0b0000100000000000001,
364   0b0000100000000000010,
365   0b0000100000000000011,
366   0b0000100000000000100,
367   0b0000100000000000101,
368   0b0000100000000000111,
369   0b0000100000000001000,
370   0b0000100000000001001,
371   0b0000100000000001101,
372   0b0000110000000000000,
373   0b0000110000000000001,
374   0b0000110000000000010,
375   0b0000110000000000011,
376   0b0000110000000000100,
377   0b0000110000000000101,
378   0b0000110000000000111,
379   0b0000110000000001001,
380   0b0000110000000001101,
381   0b0000110000000010000,
382   0b0000110000100000000,
383   0b0001000000000000000,
384   0b0001000000000000010,
385   0b0001000000000000100,
386   0b0001000000100000000,
387   0b0010110000000000000,
388   0b0010110000000010000,
389   0b0011000000000000000,
390   0b0011000000100000000,
391   0b0101000000000000000,
392   0b0101000000100000000
393};
394
395static const uint32_t gen7_datatype_table[32] = {
396   0b001000000000000001,
397   0b001000000000100000,
398   0b001000000000100001,
399   0b001000000001100001,
400   0b001000000010111101,
401   0b001000001011111101,
402   0b001000001110100001,
403   0b001000001110100101,
404   0b001000001110111101,
405   0b001000010000100001,
406   0b001000110000100000,
407   0b001000110000100001,
408   0b001001010010100101,
409   0b001001110010100100,
410   0b001001110010100101,
411   0b001111001110111101,
412   0b001111011110011101,
413   0b001111011110111100,
414   0b001111011110111101,
415   0b001111111110111100,
416   0b000000001000001100,
417   0b001000000000111101,
418   0b001000000010100101,
419   0b001000010000100000,
420   0b001001010010100100,
421   0b001001110010000100,
422   0b001010010100001001,
423   0b001101111110111101,
424   0b001111111110111101,
425   0b001011110110101100,
426   0b001010010100101000,
427   0b001010110100101000
428};
429
430static const uint16_t gen7_subreg_table[32] = {
431   0b000000000000000,
432   0b000000000000001,
433   0b000000000001000,
434   0b000000000001111,
435   0b000000000010000,
436   0b000000010000000,
437   0b000000100000000,
438   0b000000110000000,
439   0b000001000000000,
440   0b000001000010000,
441   0b000010100000000,
442   0b001000000000000,
443   0b001000000000001,
444   0b001000010000001,
445   0b001000010000010,
446   0b001000010000011,
447   0b001000010000100,
448   0b001000010000111,
449   0b001000010001000,
450   0b001000010001110,
451   0b001000010001111,
452   0b001000110000000,
453   0b001000111101000,
454   0b010000000000000,
455   0b010000110000000,
456   0b011000000000000,
457   0b011110010000111,
458   0b100000000000000,
459   0b101000000000000,
460   0b110000000000000,
461   0b111000000000000,
462   0b111000000011100
463};
464
465static const uint16_t gen7_src_index_table[32] = {
466   0b000000000000,
467   0b000000000010,
468   0b000000010000,
469   0b000000010010,
470   0b000000011000,
471   0b000000100000,
472   0b000000101000,
473   0b000001001000,
474   0b000001010000,
475   0b000001110000,
476   0b000001111000,
477   0b001100000000,
478   0b001100000010,
479   0b001100001000,
480   0b001100010000,
481   0b001100010010,
482   0b001100100000,
483   0b001100101000,
484   0b001100111000,
485   0b001101000000,
486   0b001101000010,
487   0b001101001000,
488   0b001101010000,
489   0b001101100000,
490   0b001101101000,
491   0b001101110000,
492   0b001101110001,
493   0b001101111000,
494   0b010001101000,
495   0b010001101001,
496   0b010001101010,
497   0b010110001000
498};
499
500static const uint32_t gen8_control_index_table[32] = {
501   0b0000000000000000010,
502   0b0000100000000000000,
503   0b0000100000000000001,
504   0b0000100000000000010,
505   0b0000100000000000011,
506   0b0000100000000000100,
507   0b0000100000000000101,
508   0b0000100000000000111,
509   0b0000100000000001000,
510   0b0000100000000001001,
511   0b0000100000000001101,
512   0b0000110000000000000,
513   0b0000110000000000001,
514   0b0000110000000000010,
515   0b0000110000000000011,
516   0b0000110000000000100,
517   0b0000110000000000101,
518   0b0000110000000000111,
519   0b0000110000000001001,
520   0b0000110000000001101,
521   0b0000110000000010000,
522   0b0000110000100000000,
523   0b0001000000000000000,
524   0b0001000000000000010,
525   0b0001000000000000100,
526   0b0001000000100000000,
527   0b0010110000000000000,
528   0b0010110000000010000,
529   0b0011000000000000000,
530   0b0011000000100000000,
531   0b0101000000000000000,
532   0b0101000000100000000
533};
534
535static const uint32_t gen8_datatype_table[32] = {
536   0b001000000000000000001,
537   0b001000000000001000000,
538   0b001000000000001000001,
539   0b001000000000011000001,
540   0b001000000000101011101,
541   0b001000000010111011101,
542   0b001000000011101000001,
543   0b001000000011101000101,
544   0b001000000011101011101,
545   0b001000001000001000001,
546   0b001000011000001000000,
547   0b001000011000001000001,
548   0b001000101000101000101,
549   0b001000111000101000100,
550   0b001000111000101000101,
551   0b001011100011101011101,
552   0b001011101011100011101,
553   0b001011101011101011100,
554   0b001011101011101011101,
555   0b001011111011101011100,
556   0b000000000010000001100,
557   0b001000000000001011101,
558   0b001000000000101000101,
559   0b001000001000001000000,
560   0b001000101000101000100,
561   0b001000111000100000100,
562   0b001001001001000001001,
563   0b001010111011101011101,
564   0b001011111011101011101,
565   0b001001111001101001100,
566   0b001001001001001001000,
567   0b001001011001001001000
568};
569
570static const uint16_t gen8_subreg_table[32] = {
571   0b000000000000000,
572   0b000000000000001,
573   0b000000000001000,
574   0b000000000001111,
575   0b000000000010000,
576   0b000000010000000,
577   0b000000100000000,
578   0b000000110000000,
579   0b000001000000000,
580   0b000001000010000,
581   0b000001010000000,
582   0b001000000000000,
583   0b001000000000001,
584   0b001000010000001,
585   0b001000010000010,
586   0b001000010000011,
587   0b001000010000100,
588   0b001000010000111,
589   0b001000010001000,
590   0b001000010001110,
591   0b001000010001111,
592   0b001000110000000,
593   0b001000111101000,
594   0b010000000000000,
595   0b010000110000000,
596   0b011000000000000,
597   0b011110010000111,
598   0b100000000000000,
599   0b101000000000000,
600   0b110000000000000,
601   0b111000000000000,
602   0b111000000011100
603};
604
605static const uint16_t gen8_src_index_table[32] = {
606   0b000000000000,
607   0b000000000010,
608   0b000000010000,
609   0b000000010010,
610   0b000000011000,
611   0b000000100000,
612   0b000000101000,
613   0b000001001000,
614   0b000001010000,
615   0b000001110000,
616   0b000001111000,
617   0b001100000000,
618   0b001100000010,
619   0b001100001000,
620   0b001100010000,
621   0b001100010010,
622   0b001100100000,
623   0b001100101000,
624   0b001100111000,
625   0b001101000000,
626   0b001101000010,
627   0b001101001000,
628   0b001101010000,
629   0b001101100000,
630   0b001101101000,
631   0b001101110000,
632   0b001101110001,
633   0b001101111000,
634   0b010001101000,
635   0b010001101001,
636   0b010001101010,
637   0b010110001000
638};
639
640static const uint32_t gen11_datatype_table[32] = {
641   0b001000000000000000001,
642   0b001000000000001000000,
643   0b001000000000001000001,
644   0b001000000000011000001,
645   0b001000000000101100101,
646   0b001000000101111100101,
647   0b001000000100101000001,
648   0b001000000100101000101,
649   0b001000000100101100101,
650   0b001000001000001000001,
651   0b001000011000001000000,
652   0b001000011000001000001,
653   0b001000101000101000101,
654   0b001000111000101000100,
655   0b001000111000101000101,
656   0b001100100100101100101,
657   0b001100101100100100101,
658   0b001100101100101100100,
659   0b001100101100101100101,
660   0b001100111100101100100,
661   0b000000000010000001100,
662   0b001000000000001100101,
663   0b001000000000101000101,
664   0b001000001000001000000,
665   0b001000101000101000100,
666   0b001000111000100000100,
667   0b001001001001000001001,
668   0b001101111100101100101,
669   0b001100111100101100101,
670   0b001001111001101001100,
671   0b001001001001001001000,
672   0b001001011001001001000,
673};
674
675/* This is actually the control index table for Cherryview (26 bits), but the
676 * only difference from Broadwell (24 bits) is that it has two extra 0-bits at
677 * the start.
678 *
679 * The low 24 bits have the same mappings on both hardware.
680 */
681static const uint32_t gen8_3src_control_index_table[4] = {
682   0b00100000000110000000000001,
683   0b00000000000110000000000001,
684   0b00000000001000000000000001,
685   0b00000000001000000000100001
686};
687
688/* This is actually the control index table for Cherryview (49 bits), but the
689 * only difference from Broadwell (46 bits) is that it has three extra 0-bits
690 * at the start.
691 *
692 * The low 44 bits have the same mappings on both hardware, and since the high
693 * three bits on Broadwell are zero, we can reuse Cherryview's table.
694 */
695static const uint64_t gen8_3src_source_index_table[4] = {
696   0b0000001110010011100100111001000001111000000000000,
697   0b0000001110010011100100111001000001111000000000010,
698   0b0000001110010011100100111001000001111000000001000,
699   0b0000001110010011100100111001000001111000000100000
700};
701
702static const uint32_t *control_index_table;
703static const uint32_t *datatype_table;
704static const uint16_t *subreg_table;
705static const uint16_t *src_index_table;
706
707static bool
708set_control_index(const struct gen_device_info *devinfo,
709                  brw_compact_inst *dst, const brw_inst *src)
710{
711   uint32_t uncompacted = devinfo->gen >= 8  /* 17b/G45; 19b/IVB+ */
712      ? (brw_inst_bits(src, 33, 31) << 16) | /*  3b */
713        (brw_inst_bits(src, 23, 12) <<  4) | /* 12b */
714        (brw_inst_bits(src, 10,  9) <<  2) | /*  2b */
715        (brw_inst_bits(src, 34, 34) <<  1) | /*  1b */
716        (brw_inst_bits(src,  8,  8))         /*  1b */
717      : (brw_inst_bits(src, 31, 31) << 16) | /*  1b */
718        (brw_inst_bits(src, 23,  8));        /* 16b */
719
720   /* On gen7, the flag register and subregister numbers are integrated into
721    * the control index.
722    */
723   if (devinfo->gen == 7)
724      uncompacted |= brw_inst_bits(src, 90, 89) << 17; /* 2b */
725
726   for (int i = 0; i < 32; i++) {
727      if (control_index_table[i] == uncompacted) {
728         brw_compact_inst_set_control_index(devinfo, dst, i);
729	 return true;
730      }
731   }
732
733   return false;
734}
735
736static bool
737set_datatype_index(const struct gen_device_info *devinfo, brw_compact_inst *dst,
738                   const brw_inst *src)
739{
740   uint32_t uncompacted = devinfo->gen >= 8  /* 18b/G45+; 21b/BDW+ */
741      ? (brw_inst_bits(src, 63, 61) << 18) | /*  3b */
742        (brw_inst_bits(src, 94, 89) << 12) | /*  6b */
743        (brw_inst_bits(src, 46, 35))         /* 12b */
744      : (brw_inst_bits(src, 63, 61) << 15) | /*  3b */
745        (brw_inst_bits(src, 46, 32));        /* 15b */
746
747   for (int i = 0; i < 32; i++) {
748      if (datatype_table[i] == uncompacted) {
749         brw_compact_inst_set_datatype_index(devinfo, dst, i);
750	 return true;
751      }
752   }
753
754   return false;
755}
756
757static bool
758set_subreg_index(const struct gen_device_info *devinfo, brw_compact_inst *dst,
759                 const brw_inst *src, bool is_immediate)
760{
761   uint16_t uncompacted =                 /* 15b */
762      (brw_inst_bits(src, 52, 48) << 0) | /*  5b */
763      (brw_inst_bits(src, 68, 64) << 5);  /*  5b */
764
765   if (!is_immediate)
766      uncompacted |= brw_inst_bits(src, 100, 96) << 10; /* 5b */
767
768   for (int i = 0; i < 32; i++) {
769      if (subreg_table[i] == uncompacted) {
770         brw_compact_inst_set_subreg_index(devinfo, dst, i);
771	 return true;
772      }
773   }
774
775   return false;
776}
777
778static bool
779get_src_index(uint16_t uncompacted,
780              uint16_t *compacted)
781{
782   for (int i = 0; i < 32; i++) {
783      if (src_index_table[i] == uncompacted) {
784	 *compacted = i;
785	 return true;
786      }
787   }
788
789   return false;
790}
791
792static bool
793set_src0_index(const struct gen_device_info *devinfo,
794               brw_compact_inst *dst, const brw_inst *src)
795{
796   uint16_t compacted;
797   uint16_t uncompacted = brw_inst_bits(src, 88, 77); /* 12b */
798
799   if (!get_src_index(uncompacted, &compacted))
800      return false;
801
802   brw_compact_inst_set_src0_index(devinfo, dst, compacted);
803
804   return true;
805}
806
807static bool
808set_src1_index(const struct gen_device_info *devinfo, brw_compact_inst *dst,
809               const brw_inst *src, bool is_immediate)
810{
811   uint16_t compacted;
812
813   if (is_immediate) {
814      compacted = (brw_inst_imm_ud(devinfo, src) >> 8) & 0x1f;
815   } else {
816      uint16_t uncompacted = brw_inst_bits(src, 120, 109); /* 12b */
817
818      if (!get_src_index(uncompacted, &compacted))
819         return false;
820   }
821
822   brw_compact_inst_set_src1_index(devinfo, dst, compacted);
823
824   return true;
825}
826
827static bool
828set_3src_control_index(const struct gen_device_info *devinfo,
829                       brw_compact_inst *dst, const brw_inst *src)
830{
831   assert(devinfo->gen >= 8);
832
833   uint32_t uncompacted =                  /* 24b/BDW; 26b/CHV */
834      (brw_inst_bits(src, 34, 32) << 21) | /*  3b */
835      (brw_inst_bits(src, 28,  8));        /* 21b */
836
837   if (devinfo->gen >= 9 || devinfo->is_cherryview)
838      uncompacted |= brw_inst_bits(src, 36, 35) << 24; /* 2b */
839
840   for (unsigned i = 0; i < ARRAY_SIZE(gen8_3src_control_index_table); i++) {
841      if (gen8_3src_control_index_table[i] == uncompacted) {
842         brw_compact_inst_set_3src_control_index(devinfo, dst, i);
843	 return true;
844      }
845   }
846
847   return false;
848}
849
850static bool
851set_3src_source_index(const struct gen_device_info *devinfo,
852                      brw_compact_inst *dst, const brw_inst *src)
853{
854   assert(devinfo->gen >= 8);
855
856   uint64_t uncompacted =                    /* 46b/BDW; 49b/CHV */
857      (brw_inst_bits(src,  83,  83) << 43) | /*  1b */
858      (brw_inst_bits(src, 114, 107) << 35) | /*  8b */
859      (brw_inst_bits(src,  93,  86) << 27) | /*  8b */
860      (brw_inst_bits(src,  72,  65) << 19) | /*  8b */
861      (brw_inst_bits(src,  55,  37));        /* 19b */
862
863   if (devinfo->gen >= 9 || devinfo->is_cherryview) {
864      uncompacted |=
865         (brw_inst_bits(src, 126, 125) << 47) | /* 2b */
866         (brw_inst_bits(src, 105, 104) << 45) | /* 2b */
867         (brw_inst_bits(src,  84,  84) << 44);  /* 1b */
868   } else {
869      uncompacted |=
870         (brw_inst_bits(src, 125, 125) << 45) | /* 1b */
871         (brw_inst_bits(src, 104, 104) << 44);  /* 1b */
872   }
873
874   for (unsigned i = 0; i < ARRAY_SIZE(gen8_3src_source_index_table); i++) {
875      if (gen8_3src_source_index_table[i] == uncompacted) {
876         brw_compact_inst_set_3src_source_index(devinfo, dst, i);
877	 return true;
878      }
879   }
880
881   return false;
882}
883
884static bool
885has_unmapped_bits(const struct gen_device_info *devinfo, const brw_inst *src)
886{
887   /* EOT can only be mapped on a send if the src1 is an immediate */
888   if ((brw_inst_opcode(devinfo, src) == BRW_OPCODE_SENDC ||
889        brw_inst_opcode(devinfo, src) == BRW_OPCODE_SEND) &&
890       brw_inst_eot(devinfo, src))
891      return true;
892
893   /* Check for instruction bits that don't map to any of the fields of the
894    * compacted instruction.  The instruction cannot be compacted if any of
895    * them are set.  They overlap with:
896    *  - NibCtrl (bit 47 on Gen7, bit 11 on Gen8)
897    *  - Dst.AddrImm[9] (bit 47 on Gen8)
898    *  - Src0.AddrImm[9] (bit 95 on Gen8)
899    *  - Imm64[27:31] (bits 91-95 on Gen7, bit 95 on Gen8)
900    *  - UIP[31] (bit 95 on Gen8)
901    */
902   if (devinfo->gen >= 8) {
903      assert(!brw_inst_bits(src, 7,  7));
904      return brw_inst_bits(src, 95, 95) ||
905             brw_inst_bits(src, 47, 47) ||
906             brw_inst_bits(src, 11, 11);
907   } else {
908      assert(!brw_inst_bits(src, 7,  7) &&
909             !(devinfo->gen < 7 && brw_inst_bits(src, 90, 90)));
910      return brw_inst_bits(src, 95, 91) ||
911             brw_inst_bits(src, 47, 47);
912   }
913}
914
915static bool
916has_3src_unmapped_bits(const struct gen_device_info *devinfo,
917                       const brw_inst *src)
918{
919   /* Check for three-source instruction bits that don't map to any of the
920    * fields of the compacted instruction.  All of them seem to be reserved
921    * bits currently.
922    */
923   if (devinfo->gen >= 9 || devinfo->is_cherryview) {
924      assert(!brw_inst_bits(src, 127, 127) &&
925             !brw_inst_bits(src, 7,  7));
926   } else {
927      assert(devinfo->gen >= 8);
928      assert(!brw_inst_bits(src, 127, 126) &&
929             !brw_inst_bits(src, 105, 105) &&
930             !brw_inst_bits(src, 84, 84) &&
931             !brw_inst_bits(src, 36, 35) &&
932             !brw_inst_bits(src, 7,  7));
933   }
934
935   return false;
936}
937
938static bool
939brw_try_compact_3src_instruction(const struct gen_device_info *devinfo,
940                                 brw_compact_inst *dst, const brw_inst *src)
941{
942   assert(devinfo->gen >= 8);
943
944   if (has_3src_unmapped_bits(devinfo, src))
945      return false;
946
947#define compact(field) \
948   brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_##field(devinfo, src))
949#define compact_a16(field) \
950   brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_a16_##field(devinfo, src))
951
952   compact(opcode);
953
954   if (!set_3src_control_index(devinfo, dst, src))
955      return false;
956
957   if (!set_3src_source_index(devinfo, dst, src))
958      return false;
959
960   compact(dst_reg_nr);
961   compact_a16(src0_rep_ctrl);
962   brw_compact_inst_set_3src_cmpt_control(devinfo, dst, true);
963   compact(debug_control);
964   compact(saturate);
965   compact_a16(src1_rep_ctrl);
966   compact_a16(src2_rep_ctrl);
967   compact(src0_reg_nr);
968   compact(src1_reg_nr);
969   compact(src2_reg_nr);
970   compact_a16(src0_subreg_nr);
971   compact_a16(src1_subreg_nr);
972   compact_a16(src2_subreg_nr);
973
974#undef compact
975#undef compact_a16
976
977   return true;
978}
979
980/* Compacted instructions have 12-bits for immediate sources, and a 13th bit
981 * that's replicated through the high 20 bits.
982 *
983 * Effectively this means we get 12-bit integers, 0.0f, and some limited uses
984 * of packed vectors as compactable immediates.
985 */
986static bool
987is_compactable_immediate(unsigned imm)
988{
989   /* We get the low 12 bits as-is. */
990   imm &= ~0xfff;
991
992   /* We get one bit replicated through the top 20 bits. */
993   return imm == 0 || imm == 0xfffff000;
994}
995
996/**
997 * Applies some small changes to instruction types to increase chances of
998 * compaction.
999 */
1000static brw_inst
1001precompact(const struct gen_device_info *devinfo, brw_inst inst)
1002{
1003   if (brw_inst_src0_reg_file(devinfo, &inst) != BRW_IMMEDIATE_VALUE)
1004      return inst;
1005
1006   /* The Bspec's section titled "Non-present Operands" claims that if src0
1007    * is an immediate that src1's type must be the same as that of src0.
1008    *
1009    * The SNB+ DataTypeIndex instruction compaction tables contain mappings
1010    * that do not follow this rule. E.g., from the IVB/HSW table:
1011    *
1012    *  DataTypeIndex   18-Bit Mapping       Mapped Meaning
1013    *        3         001000001011111101   r:f | i:vf | a:ud | <1> | dir |
1014    *
1015    * And from the SNB table:
1016    *
1017    *  DataTypeIndex   18-Bit Mapping       Mapped Meaning
1018    *        8         001000000111101100   a:w | i:w | a:ud | <1> | dir |
1019    *
1020    * Neither of these cause warnings from the simulator when used,
1021    * compacted or otherwise. In fact, all compaction mappings that have an
1022    * immediate in src0 use a:ud for src1.
1023    *
1024    * The GM45 instruction compaction tables do not contain mapped meanings
1025    * so it's not clear whether it has the restriction. We'll assume it was
1026    * lifted on SNB. (FINISHME: decode the GM45 tables and check.)
1027    *
1028    * Don't do any of this for 64-bit immediates, since the src1 fields
1029    * overlap with the immediate and setting them would overwrite the
1030    * immediate we set.
1031    */
1032   if (devinfo->gen >= 6 &&
1033       !(devinfo->is_haswell &&
1034         brw_inst_opcode(devinfo, &inst) == BRW_OPCODE_DIM) &&
1035       !(devinfo->gen >= 8 &&
1036         (brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_DF ||
1037          brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_UQ ||
1038          brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_Q))) {
1039      enum brw_reg_file file = brw_inst_src1_reg_file(devinfo, &inst);
1040      brw_inst_set_src1_file_type(devinfo, &inst, file, BRW_REGISTER_TYPE_UD);
1041   }
1042
1043   /* Compacted instructions only have 12-bits (plus 1 for the other 20)
1044    * for immediate values. Presumably the hardware engineers realized
1045    * that the only useful floating-point value that could be represented
1046    * in this format is 0.0, which can also be represented as a VF-typed
1047    * immediate, so they gave us the previously mentioned mapping on IVB+.
1048    *
1049    * Strangely, we do have a mapping for imm:f in src1, so we don't need
1050    * to do this there.
1051    *
1052    * If we see a 0.0:F, change the type to VF so that it can be compacted.
1053    */
1054   if (brw_inst_imm_ud(devinfo, &inst) == 0x0 &&
1055       brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_F &&
1056       brw_inst_dst_type(devinfo, &inst) == BRW_REGISTER_TYPE_F &&
1057       brw_inst_dst_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
1058      enum brw_reg_file file = brw_inst_src0_reg_file(devinfo, &inst);
1059      brw_inst_set_src0_file_type(devinfo, &inst, file, BRW_REGISTER_TYPE_VF);
1060   }
1061
1062   /* There are no mappings for dst:d | i:d, so if the immediate is suitable
1063    * set the types to :UD so the instruction can be compacted.
1064    */
1065   if (is_compactable_immediate(brw_inst_imm_ud(devinfo, &inst)) &&
1066       brw_inst_cond_modifier(devinfo, &inst) == BRW_CONDITIONAL_NONE &&
1067       brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_D &&
1068       brw_inst_dst_type(devinfo, &inst) == BRW_REGISTER_TYPE_D) {
1069      enum brw_reg_file src_file = brw_inst_src0_reg_file(devinfo, &inst);
1070      enum brw_reg_file dst_file = brw_inst_dst_reg_file(devinfo, &inst);
1071
1072      brw_inst_set_src0_file_type(devinfo, &inst, src_file, BRW_REGISTER_TYPE_UD);
1073      brw_inst_set_dst_file_type(devinfo, &inst, dst_file, BRW_REGISTER_TYPE_UD);
1074   }
1075
1076   return inst;
1077}
1078
1079/**
1080 * Tries to compact instruction src into dst.
1081 *
1082 * It doesn't modify dst unless src is compactable, which is relied on by
1083 * brw_compact_instructions().
1084 */
1085bool
1086brw_try_compact_instruction(const struct gen_device_info *devinfo,
1087                            brw_compact_inst *dst, const brw_inst *src)
1088{
1089   brw_compact_inst temp;
1090
1091   assert(brw_inst_cmpt_control(devinfo, src) == 0);
1092
1093   if (is_3src(devinfo, brw_inst_opcode(devinfo, src))) {
1094      if (devinfo->gen >= 8) {
1095         memset(&temp, 0, sizeof(temp));
1096         if (brw_try_compact_3src_instruction(devinfo, &temp, src)) {
1097            *dst = temp;
1098            return true;
1099         } else {
1100            return false;
1101         }
1102      } else {
1103         return false;
1104      }
1105   }
1106
1107   bool is_immediate =
1108      brw_inst_src0_reg_file(devinfo, src) == BRW_IMMEDIATE_VALUE ||
1109      brw_inst_src1_reg_file(devinfo, src) == BRW_IMMEDIATE_VALUE;
1110   if (is_immediate &&
1111       (devinfo->gen < 6 ||
1112        !is_compactable_immediate(brw_inst_imm_ud(devinfo, src)))) {
1113      return false;
1114   }
1115
1116   if (has_unmapped_bits(devinfo, src))
1117      return false;
1118
1119   memset(&temp, 0, sizeof(temp));
1120
1121#define compact(field) \
1122   brw_compact_inst_set_##field(devinfo, &temp, brw_inst_##field(devinfo, src))
1123
1124   compact(opcode);
1125   compact(debug_control);
1126
1127   if (!set_control_index(devinfo, &temp, src))
1128      return false;
1129   if (!set_datatype_index(devinfo, &temp, src))
1130      return false;
1131   if (!set_subreg_index(devinfo, &temp, src, is_immediate))
1132      return false;
1133
1134   if (devinfo->gen >= 6) {
1135      compact(acc_wr_control);
1136   } else {
1137      compact(mask_control_ex);
1138   }
1139
1140   compact(cond_modifier);
1141
1142   if (devinfo->gen <= 6)
1143      compact(flag_subreg_nr);
1144
1145   brw_compact_inst_set_cmpt_control(devinfo, &temp, true);
1146
1147   if (!set_src0_index(devinfo, &temp, src))
1148      return false;
1149   if (!set_src1_index(devinfo, &temp, src, is_immediate))
1150      return false;
1151
1152   brw_compact_inst_set_dst_reg_nr(devinfo, &temp,
1153                                   brw_inst_dst_da_reg_nr(devinfo, src));
1154   brw_compact_inst_set_src0_reg_nr(devinfo, &temp,
1155                                    brw_inst_src0_da_reg_nr(devinfo, src));
1156
1157   if (is_immediate) {
1158      brw_compact_inst_set_src1_reg_nr(devinfo, &temp,
1159                                       brw_inst_imm_ud(devinfo, src) & 0xff);
1160   } else {
1161      brw_compact_inst_set_src1_reg_nr(devinfo, &temp,
1162                                       brw_inst_src1_da_reg_nr(devinfo, src));
1163   }
1164
1165#undef compact
1166
1167   *dst = temp;
1168
1169   return true;
1170}
1171
1172static void
1173set_uncompacted_control(const struct gen_device_info *devinfo, brw_inst *dst,
1174                        brw_compact_inst *src)
1175{
1176   uint32_t uncompacted =
1177      control_index_table[brw_compact_inst_control_index(devinfo, src)];
1178
1179   if (devinfo->gen >= 8) {
1180      brw_inst_set_bits(dst, 33, 31, (uncompacted >> 16));
1181      brw_inst_set_bits(dst, 23, 12, (uncompacted >>  4) & 0xfff);
1182      brw_inst_set_bits(dst, 10,  9, (uncompacted >>  2) & 0x3);
1183      brw_inst_set_bits(dst, 34, 34, (uncompacted >>  1) & 0x1);
1184      brw_inst_set_bits(dst,  8,  8, (uncompacted >>  0) & 0x1);
1185   } else {
1186      brw_inst_set_bits(dst, 31, 31, (uncompacted >> 16) & 0x1);
1187      brw_inst_set_bits(dst, 23,  8, (uncompacted & 0xffff));
1188
1189      if (devinfo->gen == 7)
1190         brw_inst_set_bits(dst, 90, 89, uncompacted >> 17);
1191   }
1192}
1193
1194static void
1195set_uncompacted_datatype(const struct gen_device_info *devinfo, brw_inst *dst,
1196                         brw_compact_inst *src)
1197{
1198   uint32_t uncompacted =
1199      datatype_table[brw_compact_inst_datatype_index(devinfo, src)];
1200
1201   if (devinfo->gen >= 8) {
1202      brw_inst_set_bits(dst, 63, 61, (uncompacted >> 18));
1203      brw_inst_set_bits(dst, 94, 89, (uncompacted >> 12) & 0x3f);
1204      brw_inst_set_bits(dst, 46, 35, (uncompacted >>  0) & 0xfff);
1205   } else {
1206      brw_inst_set_bits(dst, 63, 61, (uncompacted >> 15));
1207      brw_inst_set_bits(dst, 46, 32, (uncompacted & 0x7fff));
1208   }
1209}
1210
1211static void
1212set_uncompacted_subreg(const struct gen_device_info *devinfo, brw_inst *dst,
1213                       brw_compact_inst *src)
1214{
1215   uint16_t uncompacted =
1216      subreg_table[brw_compact_inst_subreg_index(devinfo, src)];
1217
1218   brw_inst_set_bits(dst, 100, 96, (uncompacted >> 10));
1219   brw_inst_set_bits(dst,  68, 64, (uncompacted >>  5) & 0x1f);
1220   brw_inst_set_bits(dst,  52, 48, (uncompacted >>  0) & 0x1f);
1221}
1222
1223static void
1224set_uncompacted_src0(const struct gen_device_info *devinfo, brw_inst *dst,
1225                     brw_compact_inst *src)
1226{
1227   uint32_t compacted = brw_compact_inst_src0_index(devinfo, src);
1228   uint16_t uncompacted = src_index_table[compacted];
1229
1230   brw_inst_set_bits(dst, 88, 77, uncompacted);
1231}
1232
1233static void
1234set_uncompacted_src1(const struct gen_device_info *devinfo, brw_inst *dst,
1235                     brw_compact_inst *src, bool is_immediate)
1236{
1237   if (is_immediate) {
1238      signed high5 = brw_compact_inst_src1_index(devinfo, src);
1239      /* Replicate top bit of src1_index into high 20 bits of the immediate. */
1240      brw_inst_set_imm_ud(devinfo, dst, (high5 << 27) >> 19);
1241   } else {
1242      uint16_t uncompacted =
1243         src_index_table[brw_compact_inst_src1_index(devinfo, src)];
1244
1245      brw_inst_set_bits(dst, 120, 109, uncompacted);
1246   }
1247}
1248
1249static void
1250set_uncompacted_3src_control_index(const struct gen_device_info *devinfo,
1251                                   brw_inst *dst, brw_compact_inst *src)
1252{
1253   assert(devinfo->gen >= 8);
1254
1255   uint32_t compacted = brw_compact_inst_3src_control_index(devinfo, src);
1256   uint32_t uncompacted = gen8_3src_control_index_table[compacted];
1257
1258   brw_inst_set_bits(dst, 34, 32, (uncompacted >> 21) & 0x7);
1259   brw_inst_set_bits(dst, 28,  8, (uncompacted >>  0) & 0x1fffff);
1260
1261   if (devinfo->gen >= 9 || devinfo->is_cherryview)
1262      brw_inst_set_bits(dst, 36, 35, (uncompacted >> 24) & 0x3);
1263}
1264
1265static void
1266set_uncompacted_3src_source_index(const struct gen_device_info *devinfo,
1267                                  brw_inst *dst, brw_compact_inst *src)
1268{
1269   assert(devinfo->gen >= 8);
1270
1271   uint32_t compacted = brw_compact_inst_3src_source_index(devinfo, src);
1272   uint64_t uncompacted = gen8_3src_source_index_table[compacted];
1273
1274   brw_inst_set_bits(dst,  83,  83, (uncompacted >> 43) & 0x1);
1275   brw_inst_set_bits(dst, 114, 107, (uncompacted >> 35) & 0xff);
1276   brw_inst_set_bits(dst,  93,  86, (uncompacted >> 27) & 0xff);
1277   brw_inst_set_bits(dst,  72,  65, (uncompacted >> 19) & 0xff);
1278   brw_inst_set_bits(dst,  55,  37, (uncompacted >>  0) & 0x7ffff);
1279
1280   if (devinfo->gen >= 9 || devinfo->is_cherryview) {
1281      brw_inst_set_bits(dst, 126, 125, (uncompacted >> 47) & 0x3);
1282      brw_inst_set_bits(dst, 105, 104, (uncompacted >> 45) & 0x3);
1283      brw_inst_set_bits(dst,  84,  84, (uncompacted >> 44) & 0x1);
1284   } else {
1285      brw_inst_set_bits(dst, 125, 125, (uncompacted >> 45) & 0x1);
1286      brw_inst_set_bits(dst, 104, 104, (uncompacted >> 44) & 0x1);
1287   }
1288}
1289
1290static void
1291brw_uncompact_3src_instruction(const struct gen_device_info *devinfo,
1292                               brw_inst *dst, brw_compact_inst *src)
1293{
1294   assert(devinfo->gen >= 8);
1295
1296#define uncompact(field) \
1297   brw_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
1298#define uncompact_a16(field) \
1299   brw_inst_set_3src_a16_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
1300
1301   uncompact(opcode);
1302
1303   set_uncompacted_3src_control_index(devinfo, dst, src);
1304   set_uncompacted_3src_source_index(devinfo, dst, src);
1305
1306   uncompact(dst_reg_nr);
1307   uncompact_a16(src0_rep_ctrl);
1308   brw_inst_set_3src_cmpt_control(devinfo, dst, false);
1309   uncompact(debug_control);
1310   uncompact(saturate);
1311   uncompact_a16(src1_rep_ctrl);
1312   uncompact_a16(src2_rep_ctrl);
1313   uncompact(src0_reg_nr);
1314   uncompact(src1_reg_nr);
1315   uncompact(src2_reg_nr);
1316   uncompact_a16(src0_subreg_nr);
1317   uncompact_a16(src1_subreg_nr);
1318   uncompact_a16(src2_subreg_nr);
1319
1320#undef uncompact
1321#undef uncompact_a16
1322}
1323
1324void
1325brw_uncompact_instruction(const struct gen_device_info *devinfo, brw_inst *dst,
1326                          brw_compact_inst *src)
1327{
1328   memset(dst, 0, sizeof(*dst));
1329
1330   if (devinfo->gen >= 8 &&
1331       is_3src(devinfo, brw_compact_inst_3src_opcode(devinfo, src))) {
1332      brw_uncompact_3src_instruction(devinfo, dst, src);
1333      return;
1334   }
1335
1336#define uncompact(field) \
1337   brw_inst_set_##field(devinfo, dst, brw_compact_inst_##field(devinfo, src))
1338
1339   uncompact(opcode);
1340   uncompact(debug_control);
1341
1342   set_uncompacted_control(devinfo, dst, src);
1343   set_uncompacted_datatype(devinfo, dst, src);
1344
1345   /* src0/1 register file fields are in the datatype table. */
1346   bool is_immediate = brw_inst_src0_reg_file(devinfo, dst) == BRW_IMMEDIATE_VALUE ||
1347                       brw_inst_src1_reg_file(devinfo, dst) == BRW_IMMEDIATE_VALUE;
1348
1349   set_uncompacted_subreg(devinfo, dst, src);
1350
1351   if (devinfo->gen >= 6) {
1352      uncompact(acc_wr_control);
1353   } else {
1354      uncompact(mask_control_ex);
1355   }
1356
1357   uncompact(cond_modifier);
1358
1359   if (devinfo->gen <= 6)
1360      uncompact(flag_subreg_nr);
1361
1362   set_uncompacted_src0(devinfo, dst, src);
1363   set_uncompacted_src1(devinfo, dst, src, is_immediate);
1364
1365   brw_inst_set_dst_da_reg_nr(devinfo, dst,
1366                              brw_compact_inst_dst_reg_nr(devinfo, src));
1367   brw_inst_set_src0_da_reg_nr(devinfo, dst,
1368                               brw_compact_inst_src0_reg_nr(devinfo, src));
1369
1370   if (is_immediate) {
1371      brw_inst_set_imm_ud(devinfo, dst,
1372                          brw_inst_imm_ud(devinfo, dst) |
1373                          brw_compact_inst_src1_reg_nr(devinfo, src));
1374   } else {
1375      brw_inst_set_src1_da_reg_nr(devinfo, dst,
1376                                  brw_compact_inst_src1_reg_nr(devinfo, src));
1377   }
1378
1379#undef uncompact
1380}
1381
1382void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
1383                                 brw_inst *orig,
1384                                 brw_inst *uncompacted)
1385{
1386   fprintf(stderr, "Instruction compact/uncompact changed (gen%d):\n",
1387           devinfo->gen);
1388
1389   fprintf(stderr, "  before: ");
1390   brw_disassemble_inst(stderr, devinfo, orig, true);
1391
1392   fprintf(stderr, "  after:  ");
1393   brw_disassemble_inst(stderr, devinfo, uncompacted, false);
1394
1395   uint32_t *before_bits = (uint32_t *)orig;
1396   uint32_t *after_bits = (uint32_t *)uncompacted;
1397   fprintf(stderr, "  changed bits:\n");
1398   for (int i = 0; i < 128; i++) {
1399      uint32_t before = before_bits[i / 32] & (1 << (i & 31));
1400      uint32_t after = after_bits[i / 32] & (1 << (i & 31));
1401
1402      if (before != after) {
1403         fprintf(stderr, "  bit %d, %s to %s\n", i,
1404                 before ? "set" : "unset",
1405                 after ? "set" : "unset");
1406      }
1407   }
1408}
1409
1410static int
1411compacted_between(int old_ip, int old_target_ip, int *compacted_counts)
1412{
1413   int this_compacted_count = compacted_counts[old_ip];
1414   int target_compacted_count = compacted_counts[old_target_ip];
1415   return target_compacted_count - this_compacted_count;
1416}
1417
1418static void
1419update_uip_jip(const struct gen_device_info *devinfo, brw_inst *insn,
1420               int this_old_ip, int *compacted_counts)
1421{
1422   /* JIP and UIP are in units of:
1423    *    - bytes on Gen8+; and
1424    *    - compacted instructions on Gen6+.
1425    */
1426   int shift = devinfo->gen >= 8 ? 3 : 0;
1427
1428   int32_t jip_compacted = brw_inst_jip(devinfo, insn) >> shift;
1429   jip_compacted -= compacted_between(this_old_ip,
1430                                      this_old_ip + (jip_compacted / 2),
1431                                      compacted_counts);
1432   brw_inst_set_jip(devinfo, insn, jip_compacted << shift);
1433
1434   if (brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ENDIF ||
1435       brw_inst_opcode(devinfo, insn) == BRW_OPCODE_WHILE ||
1436       (brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ELSE && devinfo->gen <= 7))
1437      return;
1438
1439   int32_t uip_compacted = brw_inst_uip(devinfo, insn) >> shift;
1440   uip_compacted -= compacted_between(this_old_ip,
1441                                      this_old_ip + (uip_compacted / 2),
1442                                      compacted_counts);
1443   brw_inst_set_uip(devinfo, insn, uip_compacted << shift);
1444}
1445
1446static void
1447update_gen4_jump_count(const struct gen_device_info *devinfo, brw_inst *insn,
1448                       int this_old_ip, int *compacted_counts)
1449{
1450   assert(devinfo->gen == 5 || devinfo->is_g4x);
1451
1452   /* Jump Count is in units of:
1453    *    - uncompacted instructions on G45; and
1454    *    - compacted instructions on Gen5.
1455    */
1456   int shift = devinfo->is_g4x ? 1 : 0;
1457
1458   int jump_count_compacted = brw_inst_gen4_jump_count(devinfo, insn) << shift;
1459
1460   int target_old_ip = this_old_ip + (jump_count_compacted / 2);
1461
1462   int this_compacted_count = compacted_counts[this_old_ip];
1463   int target_compacted_count = compacted_counts[target_old_ip];
1464
1465   jump_count_compacted -= (target_compacted_count - this_compacted_count);
1466   brw_inst_set_gen4_jump_count(devinfo, insn, jump_count_compacted >> shift);
1467}
1468
1469void
1470brw_init_compaction_tables(const struct gen_device_info *devinfo)
1471{
1472   assert(g45_control_index_table[ARRAY_SIZE(g45_control_index_table) - 1] != 0);
1473   assert(g45_datatype_table[ARRAY_SIZE(g45_datatype_table) - 1] != 0);
1474   assert(g45_subreg_table[ARRAY_SIZE(g45_subreg_table) - 1] != 0);
1475   assert(g45_src_index_table[ARRAY_SIZE(g45_src_index_table) - 1] != 0);
1476   assert(gen6_control_index_table[ARRAY_SIZE(gen6_control_index_table) - 1] != 0);
1477   assert(gen6_datatype_table[ARRAY_SIZE(gen6_datatype_table) - 1] != 0);
1478   assert(gen6_subreg_table[ARRAY_SIZE(gen6_subreg_table) - 1] != 0);
1479   assert(gen6_src_index_table[ARRAY_SIZE(gen6_src_index_table) - 1] != 0);
1480   assert(gen7_control_index_table[ARRAY_SIZE(gen7_control_index_table) - 1] != 0);
1481   assert(gen7_datatype_table[ARRAY_SIZE(gen7_datatype_table) - 1] != 0);
1482   assert(gen7_subreg_table[ARRAY_SIZE(gen7_subreg_table) - 1] != 0);
1483   assert(gen7_src_index_table[ARRAY_SIZE(gen7_src_index_table) - 1] != 0);
1484   assert(gen8_control_index_table[ARRAY_SIZE(gen8_control_index_table) - 1] != 0);
1485   assert(gen8_datatype_table[ARRAY_SIZE(gen8_datatype_table) - 1] != 0);
1486   assert(gen8_subreg_table[ARRAY_SIZE(gen8_subreg_table) - 1] != 0);
1487   assert(gen8_src_index_table[ARRAY_SIZE(gen8_src_index_table) - 1] != 0);
1488   assert(gen11_datatype_table[ARRAY_SIZE(gen11_datatype_table) - 1] != 0);
1489
1490   switch (devinfo->gen) {
1491   case 11:
1492      control_index_table = gen8_control_index_table;
1493      datatype_table = gen11_datatype_table;
1494      subreg_table = gen8_subreg_table;
1495      src_index_table = gen8_src_index_table;
1496      break;
1497   case 10:
1498   case 9:
1499   case 8:
1500      control_index_table = gen8_control_index_table;
1501      datatype_table = gen8_datatype_table;
1502      subreg_table = gen8_subreg_table;
1503      src_index_table = gen8_src_index_table;
1504      break;
1505   case 7:
1506      control_index_table = gen7_control_index_table;
1507      datatype_table = gen7_datatype_table;
1508      subreg_table = gen7_subreg_table;
1509      src_index_table = gen7_src_index_table;
1510      break;
1511   case 6:
1512      control_index_table = gen6_control_index_table;
1513      datatype_table = gen6_datatype_table;
1514      subreg_table = gen6_subreg_table;
1515      src_index_table = gen6_src_index_table;
1516      break;
1517   case 5:
1518   case 4:
1519      control_index_table = g45_control_index_table;
1520      datatype_table = g45_datatype_table;
1521      subreg_table = g45_subreg_table;
1522      src_index_table = g45_src_index_table;
1523      break;
1524   default:
1525      unreachable("unknown generation");
1526   }
1527}
1528
1529void
1530brw_compact_instructions(struct brw_codegen *p, int start_offset,
1531                         struct disasm_info *disasm)
1532{
1533   if (unlikely(INTEL_DEBUG & DEBUG_NO_COMPACTION))
1534      return;
1535
1536   const struct gen_device_info *devinfo = p->devinfo;
1537   void *store = p->store + start_offset / 16;
1538   /* For an instruction at byte offset 16*i before compaction, this is the
1539    * number of compacted instructions minus the number of padding NOP/NENOPs
1540    * that preceded it.
1541    */
1542   int compacted_counts[(p->next_insn_offset - start_offset) / sizeof(brw_inst)];
1543   /* For an instruction at byte offset 8*i after compaction, this was its IP
1544    * (in 16-byte units) before compaction.
1545    */
1546   int old_ip[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst) + 1];
1547
1548   if (devinfo->gen == 4 && !devinfo->is_g4x)
1549      return;
1550
1551   int offset = 0;
1552   int compacted_count = 0;
1553   for (int src_offset = 0; src_offset < p->next_insn_offset - start_offset;
1554        src_offset += sizeof(brw_inst)) {
1555      brw_inst *src = store + src_offset;
1556      void *dst = store + offset;
1557
1558      old_ip[offset / sizeof(brw_compact_inst)] = src_offset / sizeof(brw_inst);
1559      compacted_counts[src_offset / sizeof(brw_inst)] = compacted_count;
1560
1561      brw_inst inst = precompact(devinfo, *src);
1562      brw_inst saved = inst;
1563
1564      if (brw_try_compact_instruction(devinfo, dst, &inst)) {
1565         compacted_count++;
1566
1567         if (INTEL_DEBUG) {
1568            brw_inst uncompacted;
1569            brw_uncompact_instruction(devinfo, &uncompacted, dst);
1570            if (memcmp(&saved, &uncompacted, sizeof(uncompacted))) {
1571               brw_debug_compact_uncompact(devinfo, &saved, &uncompacted);
1572            }
1573         }
1574
1575         offset += sizeof(brw_compact_inst);
1576      } else {
1577         /* All uncompacted instructions need to be aligned on G45. */
1578         if ((offset & sizeof(brw_compact_inst)) != 0 && devinfo->is_g4x){
1579            brw_compact_inst *align = store + offset;
1580            memset(align, 0, sizeof(*align));
1581            brw_compact_inst_set_opcode(devinfo, align, BRW_OPCODE_NENOP);
1582            brw_compact_inst_set_cmpt_control(devinfo, align, true);
1583            offset += sizeof(brw_compact_inst);
1584            compacted_count--;
1585            compacted_counts[src_offset / sizeof(brw_inst)] = compacted_count;
1586            old_ip[offset / sizeof(brw_compact_inst)] = src_offset / sizeof(brw_inst);
1587
1588            dst = store + offset;
1589         }
1590
1591         /* If we didn't compact this intruction, we need to move it down into
1592          * place.
1593          */
1594         if (offset != src_offset) {
1595            memmove(dst, src, sizeof(brw_inst));
1596         }
1597         offset += sizeof(brw_inst);
1598      }
1599   }
1600
1601   /* Add an entry for the ending offset of the program. This greatly
1602    * simplifies the linked list walk at the end of the function.
1603    */
1604   old_ip[offset / sizeof(brw_compact_inst)] =
1605      (p->next_insn_offset - start_offset) / sizeof(brw_inst);
1606
1607   /* Fix up control flow offsets. */
1608   p->next_insn_offset = start_offset + offset;
1609   for (offset = 0; offset < p->next_insn_offset - start_offset;
1610        offset = next_offset(devinfo, store, offset)) {
1611      brw_inst *insn = store + offset;
1612      int this_old_ip = old_ip[offset / sizeof(brw_compact_inst)];
1613      int this_compacted_count = compacted_counts[this_old_ip];
1614
1615      switch (brw_inst_opcode(devinfo, insn)) {
1616      case BRW_OPCODE_BREAK:
1617      case BRW_OPCODE_CONTINUE:
1618      case BRW_OPCODE_HALT:
1619         if (devinfo->gen >= 6) {
1620            update_uip_jip(devinfo, insn, this_old_ip, compacted_counts);
1621         } else {
1622            update_gen4_jump_count(devinfo, insn, this_old_ip,
1623                                   compacted_counts);
1624         }
1625         break;
1626
1627      case BRW_OPCODE_IF:
1628      case BRW_OPCODE_IFF:
1629      case BRW_OPCODE_ELSE:
1630      case BRW_OPCODE_ENDIF:
1631      case BRW_OPCODE_WHILE:
1632         if (devinfo->gen >= 7) {
1633            if (brw_inst_cmpt_control(devinfo, insn)) {
1634               brw_inst uncompacted;
1635               brw_uncompact_instruction(devinfo, &uncompacted,
1636                                         (brw_compact_inst *)insn);
1637
1638               update_uip_jip(devinfo, &uncompacted, this_old_ip,
1639                              compacted_counts);
1640
1641               bool ret = brw_try_compact_instruction(devinfo,
1642                                                      (brw_compact_inst *)insn,
1643                                                      &uncompacted);
1644               assert(ret); (void)ret;
1645            } else {
1646               update_uip_jip(devinfo, insn, this_old_ip, compacted_counts);
1647            }
1648         } else if (devinfo->gen == 6) {
1649            assert(!brw_inst_cmpt_control(devinfo, insn));
1650
1651            /* Jump Count is in units of compacted instructions on Gen6. */
1652            int jump_count_compacted = brw_inst_gen6_jump_count(devinfo, insn);
1653
1654            int target_old_ip = this_old_ip + (jump_count_compacted / 2);
1655            int target_compacted_count = compacted_counts[target_old_ip];
1656            jump_count_compacted -= (target_compacted_count - this_compacted_count);
1657            brw_inst_set_gen6_jump_count(devinfo, insn, jump_count_compacted);
1658         } else {
1659            update_gen4_jump_count(devinfo, insn, this_old_ip,
1660                                   compacted_counts);
1661         }
1662         break;
1663
1664      case BRW_OPCODE_ADD:
1665         /* Add instructions modifying the IP register use an immediate src1,
1666          * and Gens that use this cannot compact instructions with immediate
1667          * operands.
1668          */
1669         if (brw_inst_cmpt_control(devinfo, insn))
1670            break;
1671
1672         if (brw_inst_dst_reg_file(devinfo, insn) == BRW_ARCHITECTURE_REGISTER_FILE &&
1673             brw_inst_dst_da_reg_nr(devinfo, insn) == BRW_ARF_IP) {
1674            assert(brw_inst_src1_reg_file(devinfo, insn) == BRW_IMMEDIATE_VALUE);
1675
1676            int shift = 3;
1677            int jump_compacted = brw_inst_imm_d(devinfo, insn) >> shift;
1678
1679            int target_old_ip = this_old_ip + (jump_compacted / 2);
1680            int target_compacted_count = compacted_counts[target_old_ip];
1681            jump_compacted -= (target_compacted_count - this_compacted_count);
1682            brw_inst_set_imm_ud(devinfo, insn, jump_compacted << shift);
1683         }
1684         break;
1685      }
1686   }
1687
1688   /* p->nr_insn is counting the number of uncompacted instructions still, so
1689    * divide.  We do want to be sure there's a valid instruction in any
1690    * alignment padding, so that the next compression pass (for the FS 8/16
1691    * compile passes) parses correctly.
1692    */
1693   if (p->next_insn_offset & sizeof(brw_compact_inst)) {
1694      brw_compact_inst *align = store + offset;
1695      memset(align, 0, sizeof(*align));
1696      brw_compact_inst_set_opcode(devinfo, align, BRW_OPCODE_NOP);
1697      brw_compact_inst_set_cmpt_control(devinfo, align, true);
1698      p->next_insn_offset += sizeof(brw_compact_inst);
1699   }
1700   p->nr_insn = p->next_insn_offset / sizeof(brw_inst);
1701
1702   /* Update the instruction offsets for each group. */
1703   if (disasm) {
1704      int offset = 0;
1705
1706      foreach_list_typed(struct inst_group, group, link, &disasm->group_list) {
1707         while (start_offset + old_ip[offset / sizeof(brw_compact_inst)] *
1708                sizeof(brw_inst) != group->offset) {
1709            assert(start_offset + old_ip[offset / sizeof(brw_compact_inst)] *
1710                   sizeof(brw_inst) < group->offset);
1711            offset = next_offset(devinfo, store, offset);
1712         }
1713
1714         group->offset = start_offset + offset;
1715
1716         offset = next_offset(devinfo, store, offset);
1717      }
1718   }
1719}
1720