17ec681f3Smrg/* 27ec681f3Smrg * Copyright © 2020 Intel Corporation 37ec681f3Smrg * 47ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a 57ec681f3Smrg * copy of this software and associated documentation files (the "Software"), 67ec681f3Smrg * to deal in the Software without restriction, including without limitation 77ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the 97ec681f3Smrg * Software is furnished to do so, subject to the following conditions: 107ec681f3Smrg * 117ec681f3Smrg * The above copyright notice and this permission notice (including the next 127ec681f3Smrg * paragraph) shall be included in all copies or substantial portions of the 137ec681f3Smrg * Software. 147ec681f3Smrg * 157ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 167ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 177ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 187ec681f3Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 197ec681f3Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 207ec681f3Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 217ec681f3Smrg * IN THE SOFTWARE. 227ec681f3Smrg */ 237ec681f3Smrg 247ec681f3Smrg#ifndef BRW_NIR_RT_H 257ec681f3Smrg#define BRW_NIR_RT_H 267ec681f3Smrg 277ec681f3Smrg#include "brw_nir.h" 287ec681f3Smrg#include "brw_rt.h" 297ec681f3Smrg 307ec681f3Smrg#ifdef __cplusplus 317ec681f3Smrgextern "C" { 327ec681f3Smrg#endif 337ec681f3Smrg 347ec681f3Smrgvoid brw_nir_lower_raygen(nir_shader *nir); 357ec681f3Smrgvoid brw_nir_lower_any_hit(nir_shader *nir, 367ec681f3Smrg const struct intel_device_info *devinfo); 377ec681f3Smrgvoid brw_nir_lower_closest_hit(nir_shader *nir); 387ec681f3Smrgvoid brw_nir_lower_miss(nir_shader *nir); 397ec681f3Smrgvoid brw_nir_lower_callable(nir_shader *nir); 407ec681f3Smrgvoid brw_nir_lower_combined_intersection_any_hit(nir_shader *intersection, 417ec681f3Smrg const nir_shader *any_hit, 427ec681f3Smrg const struct intel_device_info *devinfo); 437ec681f3Smrg 447ec681f3Smrg/* We reserve the first 16B of the stack for callee data pointers */ 457ec681f3Smrg#define BRW_BTD_STACK_RESUME_BSR_ADDR_OFFSET 0 467ec681f3Smrg#define BRW_BTD_STACK_CALL_DATA_PTR_OFFSET 8 477ec681f3Smrg#define BRW_BTD_STACK_CALLEE_DATA_SIZE 16 487ec681f3Smrg 497ec681f3Smrg/* We require the stack to be 8B aligned at the start of a shader */ 507ec681f3Smrg#define BRW_BTD_STACK_ALIGN 8 517ec681f3Smrg 527ec681f3Smrgvoid brw_nir_lower_shader_returns(nir_shader *shader); 537ec681f3Smrg 547ec681f3Smrgbool brw_nir_lower_shader_calls(nir_shader *shader); 557ec681f3Smrg 567ec681f3Smrgvoid brw_nir_lower_rt_intrinsics(nir_shader *shader, 577ec681f3Smrg const struct intel_device_info *devinfo); 587ec681f3Smrgvoid brw_nir_lower_intersection_shader(nir_shader *intersection, 597ec681f3Smrg const nir_shader *any_hit, 607ec681f3Smrg const struct intel_device_info *devinfo); 617ec681f3Smrg 627ec681f3Smrgnir_shader * 637ec681f3Smrgbrw_nir_create_raygen_trampoline(const struct brw_compiler *compiler, 647ec681f3Smrg void *mem_ctx); 657ec681f3Smrgnir_shader * 667ec681f3Smrgbrw_nir_create_trivial_return_shader(const struct brw_compiler *compiler, 677ec681f3Smrg void *mem_ctx); 687ec681f3Smrg 697ec681f3Smrg#ifdef __cplusplus 707ec681f3Smrg} 717ec681f3Smrg#endif 727ec681f3Smrg 737ec681f3Smrg#endif /* BRW_NIR_RT_H */ 74