17ec681f3Smrg/*
27ec681f3Smrg * Copyright © 2018 Intel Corporation
37ec681f3Smrg *
47ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a
57ec681f3Smrg * copy of this software and associated documentation files (the "Software"),
67ec681f3Smrg * to deal in the Software without restriction, including without limitation
77ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
87ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the
97ec681f3Smrg * Software is furnished to do so, subject to the following conditions:
107ec681f3Smrg *
117ec681f3Smrg * The above copyright notice and this permission notice (including the next
127ec681f3Smrg * paragraph) shall be included in all copies or substantial portions of the
137ec681f3Smrg * Software.
147ec681f3Smrg *
157ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
167ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
177ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
187ec681f3Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
197ec681f3Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
207ec681f3Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
217ec681f3Smrg * IN THE SOFTWARE.
227ec681f3Smrg */
237ec681f3Smrg
247ec681f3Smrg#include "intel_perf.h"
257ec681f3Smrg#include "intel_perf_mdapi.h"
267ec681f3Smrg#include "intel_perf_private.h"
277ec681f3Smrg#include "intel_perf_regs.h"
287ec681f3Smrg
297ec681f3Smrg#include "dev/intel_device_info.h"
307ec681f3Smrg
317ec681f3Smrg#include <drm-uapi/i915_drm.h>
327ec681f3Smrg
337ec681f3Smrg
347ec681f3Smrgint
357ec681f3Smrgintel_perf_query_result_write_mdapi(void *data, uint32_t data_size,
367ec681f3Smrg                                    const struct intel_device_info *devinfo,
377ec681f3Smrg                                    const struct intel_perf_query_info *query,
387ec681f3Smrg                                    const struct intel_perf_query_result *result)
397ec681f3Smrg{
407ec681f3Smrg   switch (devinfo->ver) {
417ec681f3Smrg   case 7: {
427ec681f3Smrg      struct gfx7_mdapi_metrics *mdapi_data = (struct gfx7_mdapi_metrics *) data;
437ec681f3Smrg
447ec681f3Smrg      if (data_size < sizeof(*mdapi_data))
457ec681f3Smrg         return 0;
467ec681f3Smrg
477ec681f3Smrg      assert(devinfo->is_haswell);
487ec681f3Smrg
497ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(mdapi_data->ACounters); i++)
507ec681f3Smrg         mdapi_data->ACounters[i] = result->accumulator[1 + i];
517ec681f3Smrg
527ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(mdapi_data->NOACounters); i++) {
537ec681f3Smrg         mdapi_data->NOACounters[i] =
547ec681f3Smrg            result->accumulator[1 + ARRAY_SIZE(mdapi_data->ACounters) + i];
557ec681f3Smrg      }
567ec681f3Smrg
577ec681f3Smrg      mdapi_data->PerfCounter1 = result->accumulator[query->perfcnt_offset + 0];
587ec681f3Smrg      mdapi_data->PerfCounter2 = result->accumulator[query->perfcnt_offset + 1];
597ec681f3Smrg
607ec681f3Smrg      mdapi_data->ReportsCount = result->reports_accumulated;
617ec681f3Smrg      mdapi_data->TotalTime =
627ec681f3Smrg         intel_device_info_timebase_scale(devinfo, result->accumulator[0]);
637ec681f3Smrg      mdapi_data->CoreFrequency = result->gt_frequency[1];
647ec681f3Smrg      mdapi_data->CoreFrequencyChanged = result->gt_frequency[1] != result->gt_frequency[0];
657ec681f3Smrg      mdapi_data->SplitOccured = result->query_disjoint;
667ec681f3Smrg      return sizeof(*mdapi_data);
677ec681f3Smrg   }
687ec681f3Smrg   case 8: {
697ec681f3Smrg      struct gfx8_mdapi_metrics *mdapi_data = (struct gfx8_mdapi_metrics *) data;
707ec681f3Smrg
717ec681f3Smrg      if (data_size < sizeof(*mdapi_data))
727ec681f3Smrg         return 0;
737ec681f3Smrg
747ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(mdapi_data->OaCntr); i++)
757ec681f3Smrg         mdapi_data->OaCntr[i] = result->accumulator[2 + i];
767ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(mdapi_data->NoaCntr); i++) {
777ec681f3Smrg         mdapi_data->NoaCntr[i] =
787ec681f3Smrg            result->accumulator[2 + ARRAY_SIZE(mdapi_data->OaCntr) + i];
797ec681f3Smrg      }
807ec681f3Smrg
817ec681f3Smrg      mdapi_data->PerfCounter1 = result->accumulator[query->perfcnt_offset + 0];
827ec681f3Smrg      mdapi_data->PerfCounter2 = result->accumulator[query->perfcnt_offset + 1];
837ec681f3Smrg
847ec681f3Smrg      mdapi_data->ReportId = result->hw_id;
857ec681f3Smrg      mdapi_data->ReportsCount = result->reports_accumulated;
867ec681f3Smrg      mdapi_data->TotalTime =
877ec681f3Smrg         intel_device_info_timebase_scale(devinfo, result->accumulator[0]);
887ec681f3Smrg      mdapi_data->BeginTimestamp =
897ec681f3Smrg         intel_device_info_timebase_scale(devinfo, result->begin_timestamp);
907ec681f3Smrg      mdapi_data->GPUTicks = result->accumulator[1];
917ec681f3Smrg      mdapi_data->CoreFrequency = result->gt_frequency[1];
927ec681f3Smrg      mdapi_data->CoreFrequencyChanged = result->gt_frequency[1] != result->gt_frequency[0];
937ec681f3Smrg      mdapi_data->SliceFrequency =
947ec681f3Smrg         (result->slice_frequency[0] + result->slice_frequency[1]) / 2ULL;
957ec681f3Smrg      mdapi_data->UnsliceFrequency =
967ec681f3Smrg         (result->unslice_frequency[0] + result->unslice_frequency[1]) / 2ULL;
977ec681f3Smrg      mdapi_data->SplitOccured = result->query_disjoint;
987ec681f3Smrg      return sizeof(*mdapi_data);
997ec681f3Smrg   }
1007ec681f3Smrg   case 9:
1017ec681f3Smrg   case 11:
1027ec681f3Smrg   case 12:{
1037ec681f3Smrg      struct gfx9_mdapi_metrics *mdapi_data = (struct gfx9_mdapi_metrics *) data;
1047ec681f3Smrg
1057ec681f3Smrg      if (data_size < sizeof(*mdapi_data))
1067ec681f3Smrg         return 0;
1077ec681f3Smrg
1087ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(mdapi_data->OaCntr); i++)
1097ec681f3Smrg         mdapi_data->OaCntr[i] = result->accumulator[2 + i];
1107ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(mdapi_data->NoaCntr); i++) {
1117ec681f3Smrg         mdapi_data->NoaCntr[i] =
1127ec681f3Smrg            result->accumulator[2 + ARRAY_SIZE(mdapi_data->OaCntr) + i];
1137ec681f3Smrg      }
1147ec681f3Smrg
1157ec681f3Smrg      mdapi_data->PerfCounter1 = result->accumulator[query->perfcnt_offset + 0];
1167ec681f3Smrg      mdapi_data->PerfCounter2 = result->accumulator[query->perfcnt_offset + 1];
1177ec681f3Smrg
1187ec681f3Smrg      mdapi_data->ReportId = result->hw_id;
1197ec681f3Smrg      mdapi_data->ReportsCount = result->reports_accumulated;
1207ec681f3Smrg      mdapi_data->TotalTime =
1217ec681f3Smrg         intel_device_info_timebase_scale(devinfo, result->accumulator[0]);
1227ec681f3Smrg      mdapi_data->BeginTimestamp =
1237ec681f3Smrg         intel_device_info_timebase_scale(devinfo, result->begin_timestamp);
1247ec681f3Smrg      mdapi_data->GPUTicks = result->accumulator[1];
1257ec681f3Smrg      mdapi_data->CoreFrequency = result->gt_frequency[1];
1267ec681f3Smrg      mdapi_data->CoreFrequencyChanged = result->gt_frequency[1] != result->gt_frequency[0];
1277ec681f3Smrg      mdapi_data->SliceFrequency =
1287ec681f3Smrg         (result->slice_frequency[0] + result->slice_frequency[1]) / 2ULL;
1297ec681f3Smrg      mdapi_data->UnsliceFrequency =
1307ec681f3Smrg         (result->unslice_frequency[0] + result->unslice_frequency[1]) / 2ULL;
1317ec681f3Smrg      mdapi_data->SplitOccured = result->query_disjoint;
1327ec681f3Smrg      return sizeof(*mdapi_data);
1337ec681f3Smrg   }
1347ec681f3Smrg   default:
1357ec681f3Smrg      unreachable("unexpected gen");
1367ec681f3Smrg   }
1377ec681f3Smrg}
1387ec681f3Smrg
1397ec681f3Smrgvoid
1407ec681f3Smrgintel_perf_register_mdapi_statistic_query(struct intel_perf_config *perf_cfg,
1417ec681f3Smrg                                          const struct intel_device_info *devinfo)
1427ec681f3Smrg{
1437ec681f3Smrg   if (!(devinfo->ver >= 7 && devinfo->ver <= 12))
1447ec681f3Smrg      return;
1457ec681f3Smrg
1467ec681f3Smrg   struct intel_perf_query_info *query =
1477ec681f3Smrg      intel_perf_append_query_info(perf_cfg, MAX_STAT_COUNTERS);
1487ec681f3Smrg
1497ec681f3Smrg   query->kind = INTEL_PERF_QUERY_TYPE_PIPELINE;
1507ec681f3Smrg   query->name = "Intel_Raw_Pipeline_Statistics_Query";
1517ec681f3Smrg
1527ec681f3Smrg   /* The order has to match mdapi_pipeline_metrics. */
1537ec681f3Smrg   intel_perf_query_add_basic_stat_reg(query, IA_VERTICES_COUNT,
1547ec681f3Smrg                                     "N vertices submitted");
1557ec681f3Smrg   intel_perf_query_add_basic_stat_reg(query, IA_PRIMITIVES_COUNT,
1567ec681f3Smrg                                     "N primitives submitted");
1577ec681f3Smrg   intel_perf_query_add_basic_stat_reg(query, VS_INVOCATION_COUNT,
1587ec681f3Smrg                                     "N vertex shader invocations");
1597ec681f3Smrg   intel_perf_query_add_basic_stat_reg(query, GS_INVOCATION_COUNT,
1607ec681f3Smrg                                     "N geometry shader invocations");
1617ec681f3Smrg   intel_perf_query_add_basic_stat_reg(query, GS_PRIMITIVES_COUNT,
1627ec681f3Smrg                                     "N geometry shader primitives emitted");
1637ec681f3Smrg   intel_perf_query_add_basic_stat_reg(query, CL_INVOCATION_COUNT,
1647ec681f3Smrg                                     "N primitives entering clipping");
1657ec681f3Smrg   intel_perf_query_add_basic_stat_reg(query, CL_PRIMITIVES_COUNT,
1667ec681f3Smrg                                     "N primitives leaving clipping");
1677ec681f3Smrg   if (devinfo->is_haswell || devinfo->ver == 8) {
1687ec681f3Smrg      intel_perf_query_add_stat_reg(query, PS_INVOCATION_COUNT, 1, 4,
1697ec681f3Smrg                                  "N fragment shader invocations",
1707ec681f3Smrg                                  "N fragment shader invocations");
1717ec681f3Smrg   } else {
1727ec681f3Smrg      intel_perf_query_add_basic_stat_reg(query, PS_INVOCATION_COUNT,
1737ec681f3Smrg                                        "N fragment shader invocations");
1747ec681f3Smrg   }
1757ec681f3Smrg   intel_perf_query_add_basic_stat_reg(query, HS_INVOCATION_COUNT,
1767ec681f3Smrg                                     "N TCS shader invocations");
1777ec681f3Smrg   intel_perf_query_add_basic_stat_reg(query, DS_INVOCATION_COUNT,
1787ec681f3Smrg                                     "N TES shader invocations");
1797ec681f3Smrg   if (devinfo->ver >= 7) {
1807ec681f3Smrg      intel_perf_query_add_basic_stat_reg(query, CS_INVOCATION_COUNT,
1817ec681f3Smrg                                        "N compute shader invocations");
1827ec681f3Smrg   }
1837ec681f3Smrg
1847ec681f3Smrg   if (devinfo->ver >= 10) {
1857ec681f3Smrg      /* Reuse existing CS invocation register until we can expose this new
1867ec681f3Smrg       * one.
1877ec681f3Smrg       */
1887ec681f3Smrg      intel_perf_query_add_basic_stat_reg(query, CS_INVOCATION_COUNT,
1897ec681f3Smrg                                        "Reserved1");
1907ec681f3Smrg   }
1917ec681f3Smrg
1927ec681f3Smrg   query->data_size = sizeof(uint64_t) * query->n_counters;
1937ec681f3Smrg}
1947ec681f3Smrg
1957ec681f3Smrgstatic void
1967ec681f3Smrgfill_mdapi_perf_query_counter(struct intel_perf_query_info *query,
1977ec681f3Smrg                              const char *name,
1987ec681f3Smrg                              uint32_t data_offset,
1997ec681f3Smrg                              uint32_t data_size,
2007ec681f3Smrg                              enum intel_perf_counter_data_type data_type)
2017ec681f3Smrg{
2027ec681f3Smrg   struct intel_perf_query_counter *counter = &query->counters[query->n_counters];
2037ec681f3Smrg
2047ec681f3Smrg   assert(query->n_counters <= query->max_counters);
2057ec681f3Smrg
2067ec681f3Smrg   counter->name = name;
2077ec681f3Smrg   counter->desc = "Raw counter value";
2087ec681f3Smrg   counter->type = INTEL_PERF_COUNTER_TYPE_RAW;
2097ec681f3Smrg   counter->data_type = data_type;
2107ec681f3Smrg   counter->offset = data_offset;
2117ec681f3Smrg
2127ec681f3Smrg   query->n_counters++;
2137ec681f3Smrg
2147ec681f3Smrg   assert(counter->offset + intel_perf_query_counter_get_size(counter) <= query->data_size);
2157ec681f3Smrg}
2167ec681f3Smrg
2177ec681f3Smrg#define MDAPI_QUERY_ADD_COUNTER(query, struct_name, field_name, type_name) \
2187ec681f3Smrg   fill_mdapi_perf_query_counter(query, #field_name,                    \
2197ec681f3Smrg                                 (uint8_t *) &struct_name.field_name -  \
2207ec681f3Smrg                                 (uint8_t *) &struct_name,              \
2217ec681f3Smrg                                 sizeof(struct_name.field_name),        \
2227ec681f3Smrg                                 INTEL_PERF_COUNTER_DATA_TYPE_##type_name)
2237ec681f3Smrg#define MDAPI_QUERY_ADD_ARRAY_COUNTER(ctx, query, struct_name, field_name, idx, type_name) \
2247ec681f3Smrg   fill_mdapi_perf_query_counter(query,                                 \
2257ec681f3Smrg                                 ralloc_asprintf(ctx, "%s%i", #field_name, idx), \
2267ec681f3Smrg                                 (uint8_t *) &struct_name.field_name[idx] - \
2277ec681f3Smrg                                 (uint8_t *) &struct_name,              \
2287ec681f3Smrg                                 sizeof(struct_name.field_name[0]),     \
2297ec681f3Smrg                                 INTEL_PERF_COUNTER_DATA_TYPE_##type_name)
2307ec681f3Smrg
2317ec681f3Smrgvoid
2327ec681f3Smrgintel_perf_register_mdapi_oa_query(struct intel_perf_config *perf,
2337ec681f3Smrg                                   const struct intel_device_info *devinfo)
2347ec681f3Smrg{
2357ec681f3Smrg   struct intel_perf_query_info *query = NULL;
2367ec681f3Smrg
2377ec681f3Smrg   /* MDAPI requires different structures for pretty much every generation
2387ec681f3Smrg    * (right now we have definitions for gen 7 to 12).
2397ec681f3Smrg    */
2407ec681f3Smrg   if (!(devinfo->ver >= 7 && devinfo->ver <= 12))
2417ec681f3Smrg      return;
2427ec681f3Smrg
2437ec681f3Smrg   switch (devinfo->ver) {
2447ec681f3Smrg   case 7: {
2457ec681f3Smrg      query = intel_perf_append_query_info(perf, 1 + 45 + 16 + 7);
2467ec681f3Smrg      query->oa_format = I915_OA_FORMAT_A45_B8_C8;
2477ec681f3Smrg
2487ec681f3Smrg      struct gfx7_mdapi_metrics metric_data;
2497ec681f3Smrg      query->data_size = sizeof(metric_data);
2507ec681f3Smrg
2517ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, TotalTime, UINT64);
2527ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(metric_data.ACounters); i++) {
2537ec681f3Smrg         MDAPI_QUERY_ADD_ARRAY_COUNTER(perf->queries, query,
2547ec681f3Smrg                                       metric_data, ACounters, i, UINT64);
2557ec681f3Smrg      }
2567ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(metric_data.NOACounters); i++) {
2577ec681f3Smrg         MDAPI_QUERY_ADD_ARRAY_COUNTER(perf->queries, query,
2587ec681f3Smrg                                       metric_data, NOACounters, i, UINT64);
2597ec681f3Smrg      }
2607ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, PerfCounter1, UINT64);
2617ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, PerfCounter2, UINT64);
2627ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, SplitOccured, BOOL32);
2637ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, CoreFrequencyChanged, BOOL32);
2647ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, CoreFrequency, UINT64);
2657ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, ReportId, UINT32);
2667ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, ReportsCount, UINT32);
2677ec681f3Smrg      break;
2687ec681f3Smrg   }
2697ec681f3Smrg   case 8: {
2707ec681f3Smrg      query = intel_perf_append_query_info(perf, 2 + 36 + 16 + 16);
2717ec681f3Smrg      query->oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8;
2727ec681f3Smrg
2737ec681f3Smrg      struct gfx8_mdapi_metrics metric_data;
2747ec681f3Smrg      query->data_size = sizeof(metric_data);
2757ec681f3Smrg
2767ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, TotalTime, UINT64);
2777ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, GPUTicks, UINT64);
2787ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(metric_data.OaCntr); i++) {
2797ec681f3Smrg         MDAPI_QUERY_ADD_ARRAY_COUNTER(perf->queries, query,
2807ec681f3Smrg                                       metric_data, OaCntr, i, UINT64);
2817ec681f3Smrg      }
2827ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(metric_data.NoaCntr); i++) {
2837ec681f3Smrg         MDAPI_QUERY_ADD_ARRAY_COUNTER(perf->queries, query,
2847ec681f3Smrg                                       metric_data, NoaCntr, i, UINT64);
2857ec681f3Smrg      }
2867ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, BeginTimestamp, UINT64);
2877ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, Reserved1, UINT64);
2887ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, Reserved2, UINT64);
2897ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, Reserved3, UINT32);
2907ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, OverrunOccured, BOOL32);
2917ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, MarkerUser, UINT64);
2927ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, MarkerDriver, UINT64);
2937ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, SliceFrequency, UINT64);
2947ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, UnsliceFrequency, UINT64);
2957ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, PerfCounter1, UINT64);
2967ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, PerfCounter2, UINT64);
2977ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, SplitOccured, BOOL32);
2987ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, CoreFrequencyChanged, BOOL32);
2997ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, CoreFrequency, UINT64);
3007ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, ReportId, UINT32);
3017ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, ReportsCount, UINT32);
3027ec681f3Smrg      break;
3037ec681f3Smrg   }
3047ec681f3Smrg   case 9:
3057ec681f3Smrg   case 11:
3067ec681f3Smrg   case 12: {
3077ec681f3Smrg      query = intel_perf_append_query_info(perf, 2 + 36 + 16 + 16 + 16 + 2);
3087ec681f3Smrg      query->oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8;
3097ec681f3Smrg
3107ec681f3Smrg      struct gfx9_mdapi_metrics metric_data;
3117ec681f3Smrg      query->data_size = sizeof(metric_data);
3127ec681f3Smrg
3137ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, TotalTime, UINT64);
3147ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, GPUTicks, UINT64);
3157ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(metric_data.OaCntr); i++) {
3167ec681f3Smrg         MDAPI_QUERY_ADD_ARRAY_COUNTER(perf->queries, query,
3177ec681f3Smrg                                       metric_data, OaCntr, i, UINT64);
3187ec681f3Smrg      }
3197ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(metric_data.NoaCntr); i++) {
3207ec681f3Smrg         MDAPI_QUERY_ADD_ARRAY_COUNTER(perf->queries, query,
3217ec681f3Smrg                                       metric_data, NoaCntr, i, UINT64);
3227ec681f3Smrg      }
3237ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, BeginTimestamp, UINT64);
3247ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, Reserved1, UINT64);
3257ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, Reserved2, UINT64);
3267ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, Reserved3, UINT32);
3277ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, OverrunOccured, BOOL32);
3287ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, MarkerUser, UINT64);
3297ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, MarkerDriver, UINT64);
3307ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, SliceFrequency, UINT64);
3317ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, UnsliceFrequency, UINT64);
3327ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, PerfCounter1, UINT64);
3337ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, PerfCounter2, UINT64);
3347ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, SplitOccured, BOOL32);
3357ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, CoreFrequencyChanged, BOOL32);
3367ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, CoreFrequency, UINT64);
3377ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, ReportId, UINT32);
3387ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, ReportsCount, UINT32);
3397ec681f3Smrg      for (int i = 0; i < ARRAY_SIZE(metric_data.UserCntr); i++) {
3407ec681f3Smrg         MDAPI_QUERY_ADD_ARRAY_COUNTER(perf->queries, query,
3417ec681f3Smrg                                       metric_data, UserCntr, i, UINT64);
3427ec681f3Smrg      }
3437ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, UserCntrCfgId, UINT32);
3447ec681f3Smrg      MDAPI_QUERY_ADD_COUNTER(query, metric_data, Reserved4, UINT32);
3457ec681f3Smrg      break;
3467ec681f3Smrg   }
3477ec681f3Smrg   default:
3487ec681f3Smrg      unreachable("Unsupported gen");
3497ec681f3Smrg      break;
3507ec681f3Smrg   }
3517ec681f3Smrg
3527ec681f3Smrg   query->kind = INTEL_PERF_QUERY_TYPE_RAW;
3537ec681f3Smrg   query->name = "Intel_Raw_Hardware_Counters_Set_0_Query";
3547ec681f3Smrg   query->guid = INTEL_PERF_QUERY_GUID_MDAPI;
3557ec681f3Smrg
3567ec681f3Smrg   {
3577ec681f3Smrg      /* Accumulation buffer offsets copied from an actual query... */
3587ec681f3Smrg      const struct intel_perf_query_info *copy_query =
3597ec681f3Smrg         &perf->queries[0];
3607ec681f3Smrg
3617ec681f3Smrg      query->gpu_time_offset = copy_query->gpu_time_offset;
3627ec681f3Smrg      query->gpu_clock_offset = copy_query->gpu_clock_offset;
3637ec681f3Smrg      query->a_offset = copy_query->a_offset;
3647ec681f3Smrg      query->b_offset = copy_query->b_offset;
3657ec681f3Smrg      query->c_offset = copy_query->c_offset;
3667ec681f3Smrg      query->perfcnt_offset = copy_query->perfcnt_offset;
3677ec681f3Smrg   }
3687ec681f3Smrg}
369