101e04c3fSmrg/* 201e04c3fSmrg * Copyright © 2016 Intel Corporation 301e04c3fSmrg * 401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a 501e04c3fSmrg * copy of this software and associated documentation files (the "Software"), 601e04c3fSmrg * to deal in the Software without restriction, including without limitation 701e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 801e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the 901e04c3fSmrg * Software is furnished to do so, subject to the following conditions: 1001e04c3fSmrg * 1101e04c3fSmrg * The above copyright notice and this permission notice (including the next 1201e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the 1301e04c3fSmrg * Software. 1401e04c3fSmrg * 1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1801e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1901e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2001e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 2101e04c3fSmrg * IN THE SOFTWARE. 2201e04c3fSmrg */ 2301e04c3fSmrg 2401e04c3fSmrg/* 2501e04c3fSmrg * NOTE: The header can be included multiple times, from the same file. 2601e04c3fSmrg */ 2701e04c3fSmrg 2801e04c3fSmrg/* 2901e04c3fSmrg * Gen-specific function declarations. This header must *not* be included 3001e04c3fSmrg * directly. Instead, it is included multiple times by anv_private.h. 317ec681f3Smrg * 3201e04c3fSmrg * In this header file, the usual genx() macro is available. 3301e04c3fSmrg */ 3401e04c3fSmrg 3501e04c3fSmrg#ifndef ANV_PRIVATE_H 3601e04c3fSmrg#error This file is included by means other than anv_private.h 3701e04c3fSmrg#endif 3801e04c3fSmrg 397ec681f3Smrgextern const uint32_t genX(vk_to_intel_cullmode)[]; 407ec681f3Smrg 417ec681f3Smrgextern const uint32_t genX(vk_to_intel_front_face)[]; 427ec681f3Smrg 437ec681f3Smrgextern const uint32_t genX(vk_to_intel_primitive_type)[]; 447ec681f3Smrg 457ec681f3Smrgextern const uint32_t genX(vk_to_intel_compare_op)[]; 467ec681f3Smrg 477ec681f3Smrgextern const uint32_t genX(vk_to_intel_stencil_op)[]; 487ec681f3Smrg 497ec681f3Smrgextern const uint32_t genX(vk_to_intel_logic_op)[]; 507ec681f3Smrg 517ec681f3Smrgvoid genX(init_physical_device_state)(struct anv_physical_device *device); 527ec681f3Smrg 5301e04c3fSmrgVkResult genX(init_device_state)(struct anv_device *device); 5401e04c3fSmrg 5501e04c3fSmrgvoid genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer); 5601e04c3fSmrg 5701e04c3fSmrgvoid genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer); 5801e04c3fSmrg 597ec681f3Smrgvoid genX(cmd_buffer_emit_gfx7_depth_flush)(struct anv_cmd_buffer *cmd_buffer); 607ec681f3Smrg 617ec681f3Smrgvoid genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer, 627ec681f3Smrg const struct isl_surf *surf); 637ec681f3Smrg 647ec681f3Smrgvoid genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(struct anv_cmd_buffer *cmd_buffer, 657ec681f3Smrg int vb_index, 667ec681f3Smrg struct anv_address vb_address, 677ec681f3Smrg uint32_t vb_size); 687ec681f3Smrgvoid genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(struct anv_cmd_buffer *cmd_buffer, 697ec681f3Smrg uint32_t access_type, 707ec681f3Smrg uint64_t vb_used); 717ec681f3Smrg 727ec681f3Smrgvoid genX(cmd_buffer_emit_hashing_mode)(struct anv_cmd_buffer *cmd_buffer, 737ec681f3Smrg unsigned width, unsigned height, 747ec681f3Smrg unsigned scale); 7501e04c3fSmrg 7601e04c3fSmrgvoid genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer); 7701e04c3fSmrgvoid genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer); 7801e04c3fSmrg 797ec681f3Smrgvoid genX(emit_l3_config)(struct anv_batch *batch, 807ec681f3Smrg const struct anv_device *device, 817ec681f3Smrg const struct intel_l3_config *cfg); 827ec681f3Smrg 8301e04c3fSmrgvoid genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, 847ec681f3Smrg const struct intel_l3_config *cfg); 8501e04c3fSmrg 8601e04c3fSmrgvoid genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer); 8701e04c3fSmrgvoid genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer); 8801e04c3fSmrg 8901e04c3fSmrgvoid genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer); 9001e04c3fSmrg 9101e04c3fSmrgvoid genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, 9201e04c3fSmrg bool enable); 9301e04c3fSmrg 9401e04c3fSmrgvoid genX(cmd_buffer_mark_image_written)(struct anv_cmd_buffer *cmd_buffer, 9501e04c3fSmrg const struct anv_image *image, 9601e04c3fSmrg VkImageAspectFlagBits aspect, 9701e04c3fSmrg enum isl_aux_usage aux_usage, 9801e04c3fSmrg uint32_t level, 9901e04c3fSmrg uint32_t base_layer, 10001e04c3fSmrg uint32_t layer_count); 10101e04c3fSmrg 1029f464c52Smayavoid genX(cmd_emit_conditional_render_predicate)(struct anv_cmd_buffer *cmd_buffer); 1039f464c52Smaya 10401e04c3fSmrgvoid 10501e04c3fSmrggenX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch, 1067ec681f3Smrg const struct intel_l3_config *l3_config, 10701e04c3fSmrg VkShaderStageFlags active_stages, 1087ec681f3Smrg const unsigned entry_size[4], 1097ec681f3Smrg enum intel_urb_deref_block_size *deref_block_size); 1107ec681f3Smrg 1117ec681f3Smrgvoid genX(emit_multisample)(struct anv_batch *batch, uint32_t samples, 1127ec681f3Smrg const VkSampleLocationEXT *locations); 1137ec681f3Smrg 1147ec681f3Smrgvoid genX(emit_sample_pattern)(struct anv_batch *batch, uint32_t samples, 1157ec681f3Smrg const VkSampleLocationEXT *locations); 1167ec681f3Smrg 1177ec681f3Smrgvoid genX(emit_shading_rate)(struct anv_batch *batch, 1187ec681f3Smrg const struct anv_graphics_pipeline *pipeline, 1197ec681f3Smrg struct anv_state cps_states, 1207ec681f3Smrg struct anv_dynamic_state *dynamic_state); 12101e04c3fSmrg 12201e04c3fSmrgvoid genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, 12301e04c3fSmrg struct anv_address dst, struct anv_address src, 12401e04c3fSmrg uint32_t size); 12501e04c3fSmrg 12601e04c3fSmrgvoid genX(blorp_exec)(struct blorp_batch *batch, 12701e04c3fSmrg const struct blorp_params *params); 1287ec681f3Smrg 1297ec681f3Smrgvoid genX(cmd_emit_timestamp)(struct anv_batch *batch, 1307ec681f3Smrg struct anv_bo *bo, 1317ec681f3Smrg uint32_t offset); 1327ec681f3Smrg 1337ec681f3Smrgvoid 1347ec681f3SmrggenX(rasterization_mode)(VkPolygonMode raster_mode, 1357ec681f3Smrg VkLineRasterizationModeEXT line_mode, 1367ec681f3Smrg float line_width, 1377ec681f3Smrg uint32_t *api_mode, 1387ec681f3Smrg bool *msaa_rasterization_enable); 1397ec681f3Smrg 1407ec681f3Smrguint32_t 1417ec681f3SmrggenX(ms_rasterization_mode)(struct anv_graphics_pipeline *pipeline, 1427ec681f3Smrg VkPolygonMode raster_mode); 1437ec681f3Smrg 1447ec681f3SmrgVkPolygonMode 1457ec681f3SmrggenX(raster_polygon_mode)(struct anv_graphics_pipeline *pipeline, 1467ec681f3Smrg VkPrimitiveTopology primitive_topology); 147