17ec681f3SmrgMOV.i32.ts r1, lane_id 27ec681f3SmrgMOV.i32.id r1, wls_ptr 37ec681f3SmrgMOV.i32 r1, lane_id 47ec681f3SmrgMOV.i32 r1, wls_ptr 57ec681f3SmrgFADD.f32 r0, r1 67ec681f3SmrgTEX.computed.2d.slot0 @r2, @r4:r5:r6:r7 77ec681f3SmrgBRANCH 87ec681f3SmrgBRANCH #0 97ec681f3SmrgBRANCH #0, offset: 107ec681f3SmrgBRANCH u0, offset:-123456789 117ec681f3SmrgBRANCH u0, offset:123456789 127ec681f3SmrgIADD_IMM.i32 r3, #12345 137ec681f3SmrgFADD.v2f16 r0, r1, r0.h0 147ec681f3SmrgMOV.i32.wait01.wait1 r0, r1 157ec681f3SmrgMOV.i32.wait01.return r0, r1 167ec681f3SmrgMOV.i32.reconverge.return r0, r1 177ec681f3SmrgFROUND.f32.rtn.clamp_m1_1 r2, `r2.neg 187ec681f3Smrg 197ec681f3Smrg# An instruction may access no more than a single 64-bit uniform slot. 207ec681f3SmrgFADD.f32 r0, u0, u4 217ec681f3SmrgFADD.f32 r0, u5, u3 227ec681f3SmrgFADD.f32 r0, u5, u6 237ec681f3Smrg 247ec681f3Smrg# An instruction may access no more than 64-bits of combined uniforms and constants. 257ec681f3SmrgFMA.f32 r0, u0, u1, 0x0 267ec681f3SmrgFMA.f32 r0, u0, 0x40490FDB, 0x0 277ec681f3SmrgFMA.f32 r0, 0x3F317218, 0x40490FDB, 0x0 287ec681f3Smrg 297ec681f3Smrg# An instruction may only access uniforms in the default immediate mode. 307ec681f3SmrgMOV.i32.id r0, u0 317ec681f3SmrgMOV.i32.ts r0, u1 327ec681f3Smrg 337ec681f3Smrg# An instruction may access no more than a single special immediate (e.g. lane_id). 347ec681f3SmrgIADD.u32 r0, lane_id, core_id 357ec681f3SmrgIADD.u32.id r0, lane_id, core_id 367ec681f3SmrgIADD.u32.ts r0, tls_ptr, wls_ptr 377ec681f3SmrgIADD.u32.ts r0, tls_ptr, tls_ptr_hi 387ec681f3SmrgIADD.u32.id r0, tls_ptr, tls_ptr_hi 397ec681f3SmrgIADD.u32.id r0, tls_ptr, 0x40490FDB 40