amdgpu_internal.h revision bbff01ce 
1/*
2 * Copyright © 2014 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _AMDGPU_INTERNAL_H_
26#define _AMDGPU_INTERNAL_H_
27
28#include <assert.h>
29#include <pthread.h>
30
31#include "libdrm_macros.h"
32#include "xf86atomic.h"
33#include "amdgpu.h"
34#include "util_double_list.h"
35#include "handle_table.h"
36
37#define AMDGPU_CS_MAX_RINGS 8
38/* do not use below macro if b is not power of 2 aligned value */
39#define __round_mask(x, y) ((__typeof__(x))((y)-1))
40#define ROUND_UP(x, y) ((((x)-1) | __round_mask(x, y))+1)
41#define ROUND_DOWN(x, y) ((x) & ~__round_mask(x, y))
42
43#define AMDGPU_INVALID_VA_ADDRESS	0xffffffffffffffff
44#define AMDGPU_NULL_SUBMIT_SEQ		0
45
46struct amdgpu_bo_va_hole {
47	struct list_head list;
48	uint64_t offset;
49	uint64_t size;
50};
51
52struct amdgpu_bo_va_mgr {
53	uint64_t va_max;
54	struct list_head va_holes;
55	pthread_mutex_t bo_va_mutex;
56	uint32_t va_alignment;
57};
58
59struct amdgpu_va {
60	uint64_t address;
61	uint64_t size;
62	enum amdgpu_gpu_va_range range;
63	struct amdgpu_bo_va_mgr *vamgr;
64};
65
66struct amdgpu_va_manager {
67	/** The VA manager for the lower virtual address space */
68	struct amdgpu_bo_va_mgr vamgr_low;
69	/** The VA manager for the 32bit address space */
70	struct amdgpu_bo_va_mgr vamgr_32;
71	/** The VA manager for the high virtual address space */
72	struct amdgpu_bo_va_mgr vamgr_high;
73	/** The VA manager for the 32bit high address space */
74	struct amdgpu_bo_va_mgr vamgr_high_32;
75};
76
77struct amdgpu_device {
78	atomic_t refcount;
79	struct amdgpu_device *next;
80	int fd;
81	int flink_fd;
82	unsigned major_version;
83	unsigned minor_version;
84
85	char *marketing_name;
86	/** List of buffer handles. Protected by bo_table_mutex. */
87	struct handle_table bo_handles;
88	/** List of buffer GEM flink names. Protected by bo_table_mutex. */
89	struct handle_table bo_flink_names;
90	/** This protects all hash tables. */
91	pthread_mutex_t bo_table_mutex;
92	struct drm_amdgpu_info_device dev_info;
93	struct amdgpu_gpu_info info;
94
95	struct amdgpu_va_manager va_mgr;
96};
97
98struct amdgpu_bo {
99	atomic_t refcount;
100	struct amdgpu_device *dev;
101
102	uint64_t alloc_size;
103
104	uint32_t handle;
105	uint32_t flink_name;
106
107	pthread_mutex_t cpu_access_mutex;
108	void *cpu_ptr;
109	int64_t cpu_map_count;
110};
111
112struct amdgpu_bo_list {
113	struct amdgpu_device *dev;
114
115	uint32_t handle;
116};
117
118struct amdgpu_context {
119	struct amdgpu_device *dev;
120	/** Mutex for accessing fences and to maintain command submissions
121	    in good sequence. */
122	pthread_mutex_t sequence_mutex;
123	/* context id*/
124	uint32_t id;
125	uint64_t last_seq[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
126	struct list_head sem_list[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
127};
128
129/**
130 * Structure describing sw semaphore based on scheduler
131 *
132 */
133struct amdgpu_semaphore {
134	atomic_t refcount;
135	struct list_head list;
136	struct amdgpu_cs_fence signal_fence;
137};
138
139/**
140 * Functions.
141 */
142
143drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start,
144		       uint64_t max, uint64_t alignment);
145
146drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr);
147
148drm_private void amdgpu_parse_asic_ids(struct amdgpu_device *dev);
149
150drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev);
151
152drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout);
153
154/**
155 * Inline functions.
156 */
157
158/**
159 * Increment src and decrement dst as if we were updating references
160 * for an assignment between 2 pointers of some objects.
161 *
162 * \return  true if dst is 0
163 */
164static inline bool update_references(atomic_t *dst, atomic_t *src)
165{
166	if (dst != src) {
167		/* bump src first */
168		if (src) {
169			assert(atomic_read(src) > 0);
170			atomic_inc(src);
171		}
172		if (dst) {
173			assert(atomic_read(dst) > 0);
174			return atomic_dec_and_test(dst);
175		}
176	}
177	return false;
178}
179
180#endif
181