etnaviv_drmif.h revision 037b3c26
1037b3c26Smrg/* 2037b3c26Smrg * Copyright (C) 2014-2015 Etnaviv Project 3037b3c26Smrg * 4037b3c26Smrg * Permission is hereby granted, free of charge, to any person obtaining a 5037b3c26Smrg * copy of this software and associated documentation files (the "Software"), 6037b3c26Smrg * to deal in the Software without restriction, including without limitation 7037b3c26Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8037b3c26Smrg * and/or sell copies of the Software, and to permit persons to whom the 9037b3c26Smrg * Software is furnished to do so, subject to the following conditions: 10037b3c26Smrg * 11037b3c26Smrg * The above copyright notice and this permission notice (including the next 12037b3c26Smrg * paragraph) shall be included in all copies or substantial portions of the 13037b3c26Smrg * Software. 14037b3c26Smrg * 15037b3c26Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16037b3c26Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17037b3c26Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18037b3c26Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19037b3c26Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20037b3c26Smrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21037b3c26Smrg * SOFTWARE. 22037b3c26Smrg * 23037b3c26Smrg * Authors: 24037b3c26Smrg * Christian Gmeiner <christian.gmeiner@gmail.com> 25037b3c26Smrg */ 26037b3c26Smrg 27037b3c26Smrg#ifndef ETNAVIV_DRMIF_H_ 28037b3c26Smrg#define ETNAVIV_DRMIF_H_ 29037b3c26Smrg 30037b3c26Smrg#include <xf86drm.h> 31037b3c26Smrg#include <stdint.h> 32037b3c26Smrg 33037b3c26Smrgstruct etna_bo; 34037b3c26Smrgstruct etna_pipe; 35037b3c26Smrgstruct etna_gpu; 36037b3c26Smrgstruct etna_device; 37037b3c26Smrgstruct etna_cmd_stream; 38037b3c26Smrg 39037b3c26Smrgenum etna_pipe_id { 40037b3c26Smrg ETNA_PIPE_3D = 0, 41037b3c26Smrg ETNA_PIPE_2D = 1, 42037b3c26Smrg ETNA_PIPE_VG = 2, 43037b3c26Smrg ETNA_PIPE_MAX 44037b3c26Smrg}; 45037b3c26Smrg 46037b3c26Smrgenum etna_param_id { 47037b3c26Smrg ETNA_GPU_MODEL = 0x1, 48037b3c26Smrg ETNA_GPU_REVISION = 0x2, 49037b3c26Smrg ETNA_GPU_FEATURES_0 = 0x3, 50037b3c26Smrg ETNA_GPU_FEATURES_1 = 0x4, 51037b3c26Smrg ETNA_GPU_FEATURES_2 = 0x5, 52037b3c26Smrg ETNA_GPU_FEATURES_3 = 0x6, 53037b3c26Smrg ETNA_GPU_FEATURES_4 = 0x7, 54037b3c26Smrg ETNA_GPU_FEATURES_5 = 0x8, 55037b3c26Smrg ETNA_GPU_FEATURES_6 = 0x9, 56037b3c26Smrg 57037b3c26Smrg ETNA_GPU_STREAM_COUNT = 0x10, 58037b3c26Smrg ETNA_GPU_REGISTER_MAX = 0x11, 59037b3c26Smrg ETNA_GPU_THREAD_COUNT = 0x12, 60037b3c26Smrg ETNA_GPU_VERTEX_CACHE_SIZE = 0x13, 61037b3c26Smrg ETNA_GPU_SHADER_CORE_COUNT = 0x14, 62037b3c26Smrg ETNA_GPU_PIXEL_PIPES = 0x15, 63037b3c26Smrg ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE = 0x16, 64037b3c26Smrg ETNA_GPU_BUFFER_SIZE = 0x17, 65037b3c26Smrg ETNA_GPU_INSTRUCTION_COUNT = 0x18, 66037b3c26Smrg ETNA_GPU_NUM_CONSTANTS = 0x19, 67037b3c26Smrg ETNA_GPU_NUM_VARYINGS = 0x1a 68037b3c26Smrg}; 69037b3c26Smrg 70037b3c26Smrg/* bo flags: */ 71037b3c26Smrg#define DRM_ETNA_GEM_CACHE_CACHED 0x00010000 72037b3c26Smrg#define DRM_ETNA_GEM_CACHE_WC 0x00020000 73037b3c26Smrg#define DRM_ETNA_GEM_CACHE_UNCACHED 0x00040000 74037b3c26Smrg#define DRM_ETNA_GEM_CACHE_MASK 0x000f0000 75037b3c26Smrg/* map flags */ 76037b3c26Smrg#define DRM_ETNA_GEM_FORCE_MMU 0x00100000 77037b3c26Smrg 78037b3c26Smrg/* bo access flags: (keep aligned to ETNA_PREP_x) */ 79037b3c26Smrg#define DRM_ETNA_PREP_READ 0x01 80037b3c26Smrg#define DRM_ETNA_PREP_WRITE 0x02 81037b3c26Smrg#define DRM_ETNA_PREP_NOSYNC 0x04 82037b3c26Smrg 83037b3c26Smrg/* device functions: 84037b3c26Smrg */ 85037b3c26Smrg 86037b3c26Smrgstruct etna_device *etna_device_new(int fd); 87037b3c26Smrgstruct etna_device *etna_device_new_dup(int fd); 88037b3c26Smrgstruct etna_device *etna_device_ref(struct etna_device *dev); 89037b3c26Smrgvoid etna_device_del(struct etna_device *dev); 90037b3c26Smrgint etna_device_fd(struct etna_device *dev); 91037b3c26Smrg 92037b3c26Smrg/* gpu functions: 93037b3c26Smrg */ 94037b3c26Smrg 95037b3c26Smrgstruct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core); 96037b3c26Smrgvoid etna_gpu_del(struct etna_gpu *gpu); 97037b3c26Smrgint etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param, 98037b3c26Smrg uint64_t *value); 99037b3c26Smrg 100037b3c26Smrg 101037b3c26Smrg/* pipe functions: 102037b3c26Smrg */ 103037b3c26Smrg 104037b3c26Smrgstruct etna_pipe *etna_pipe_new(struct etna_gpu *gpu, enum etna_pipe_id id); 105037b3c26Smrgvoid etna_pipe_del(struct etna_pipe *pipe); 106037b3c26Smrgint etna_pipe_wait(struct etna_pipe *pipe, uint32_t timestamp, uint32_t ms); 107037b3c26Smrgint etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns); 108037b3c26Smrg 109037b3c26Smrg 110037b3c26Smrg/* buffer-object functions: 111037b3c26Smrg */ 112037b3c26Smrg 113037b3c26Smrgstruct etna_bo *etna_bo_new(struct etna_device *dev, 114037b3c26Smrg uint32_t size, uint32_t flags); 115037b3c26Smrgstruct etna_bo *etna_bo_from_handle(struct etna_device *dev, 116037b3c26Smrg uint32_t handle, uint32_t size); 117037b3c26Smrgstruct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name); 118037b3c26Smrgstruct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd); 119037b3c26Smrgstruct etna_bo *etna_bo_ref(struct etna_bo *bo); 120037b3c26Smrgvoid etna_bo_del(struct etna_bo *bo); 121037b3c26Smrgint etna_bo_get_name(struct etna_bo *bo, uint32_t *name); 122037b3c26Smrguint32_t etna_bo_handle(struct etna_bo *bo); 123037b3c26Smrgint etna_bo_dmabuf(struct etna_bo *bo); 124037b3c26Smrguint32_t etna_bo_size(struct etna_bo *bo); 125037b3c26Smrgvoid * etna_bo_map(struct etna_bo *bo); 126037b3c26Smrgint etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op); 127037b3c26Smrgvoid etna_bo_cpu_fini(struct etna_bo *bo); 128037b3c26Smrg 129037b3c26Smrg 130037b3c26Smrg/* cmd stream functions: 131037b3c26Smrg */ 132037b3c26Smrg 133037b3c26Smrgstruct etna_cmd_stream { 134037b3c26Smrg uint32_t *buffer; 135037b3c26Smrg uint32_t offset; /* in 32-bit words */ 136037b3c26Smrg uint32_t size; /* in 32-bit words */ 137037b3c26Smrg}; 138037b3c26Smrg 139037b3c26Smrgstruct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe, uint32_t size, 140037b3c26Smrg void (*reset_notify)(struct etna_cmd_stream *stream, void *priv), 141037b3c26Smrg void *priv); 142037b3c26Smrgvoid etna_cmd_stream_del(struct etna_cmd_stream *stream); 143037b3c26Smrguint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream); 144037b3c26Smrgvoid etna_cmd_stream_flush(struct etna_cmd_stream *stream); 145037b3c26Smrgvoid etna_cmd_stream_finish(struct etna_cmd_stream *stream); 146037b3c26Smrg 147037b3c26Smrgstatic inline uint32_t etna_cmd_stream_avail(struct etna_cmd_stream *stream) 148037b3c26Smrg{ 149037b3c26Smrg static const uint32_t END_CLEARANCE = 2; /* LINK op code */ 150037b3c26Smrg 151037b3c26Smrg return stream->size - stream->offset - END_CLEARANCE; 152037b3c26Smrg} 153037b3c26Smrg 154037b3c26Smrgstatic inline void etna_cmd_stream_reserve(struct etna_cmd_stream *stream, size_t n) 155037b3c26Smrg{ 156037b3c26Smrg if (etna_cmd_stream_avail(stream) < n) 157037b3c26Smrg etna_cmd_stream_flush(stream); 158037b3c26Smrg} 159037b3c26Smrg 160037b3c26Smrgstatic inline void etna_cmd_stream_emit(struct etna_cmd_stream *stream, uint32_t data) 161037b3c26Smrg{ 162037b3c26Smrg stream->buffer[stream->offset++] = data; 163037b3c26Smrg} 164037b3c26Smrg 165037b3c26Smrgstatic inline uint32_t etna_cmd_stream_get(struct etna_cmd_stream *stream, uint32_t offset) 166037b3c26Smrg{ 167037b3c26Smrg return stream->buffer[offset]; 168037b3c26Smrg} 169037b3c26Smrg 170037b3c26Smrgstatic inline void etna_cmd_stream_set(struct etna_cmd_stream *stream, uint32_t offset, 171037b3c26Smrg uint32_t data) 172037b3c26Smrg{ 173037b3c26Smrg stream->buffer[offset] = data; 174037b3c26Smrg} 175037b3c26Smrg 176037b3c26Smrgstatic inline uint32_t etna_cmd_stream_offset(struct etna_cmd_stream *stream) 177037b3c26Smrg{ 178037b3c26Smrg return stream->offset; 179037b3c26Smrg} 180037b3c26Smrg 181037b3c26Smrgstruct etna_reloc { 182037b3c26Smrg struct etna_bo *bo; 183037b3c26Smrg#define ETNA_RELOC_READ 0x0001 184037b3c26Smrg#define ETNA_RELOC_WRITE 0x0002 185037b3c26Smrg uint32_t flags; 186037b3c26Smrg uint32_t offset; 187037b3c26Smrg}; 188037b3c26Smrg 189037b3c26Smrgvoid etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_reloc *r); 190037b3c26Smrg 191037b3c26Smrg#endif /* ETNAVIV_DRMIF_H_ */ 192