1e88f27b3Smrg#ifndef _MSM_KGSL_H 2e88f27b3Smrg#define _MSM_KGSL_H 3e88f27b3Smrg 4e88f27b3Smrg#define KGSL_VERSION_MAJOR 3 5e88f27b3Smrg#define KGSL_VERSION_MINOR 11 6e88f27b3Smrg 7e88f27b3Smrg/*context flags */ 8e88f27b3Smrg#define KGSL_CONTEXT_SAVE_GMEM 0x00000001 9e88f27b3Smrg#define KGSL_CONTEXT_NO_GMEM_ALLOC 0x00000002 10e88f27b3Smrg#define KGSL_CONTEXT_SUBMIT_IB_LIST 0x00000004 11e88f27b3Smrg#define KGSL_CONTEXT_CTX_SWITCH 0x00000008 12e88f27b3Smrg#define KGSL_CONTEXT_PREAMBLE 0x00000010 13e88f27b3Smrg#define KGSL_CONTEXT_TRASH_STATE 0x00000020 14e88f27b3Smrg#define KGSL_CONTEXT_PER_CONTEXT_TS 0x00000040 15e88f27b3Smrg 16e88f27b3Smrg#define KGSL_CONTEXT_INVALID 0xffffffff 17e88f27b3Smrg 18e88f27b3Smrg/* Memory allocayion flags */ 19e88f27b3Smrg#define KGSL_MEMFLAGS_GPUREADONLY 0x01000000 20e88f27b3Smrg 21e88f27b3Smrg/* generic flag values */ 22e88f27b3Smrg#define KGSL_FLAGS_NORMALMODE 0x00000000 23e88f27b3Smrg#define KGSL_FLAGS_SAFEMODE 0x00000001 24e88f27b3Smrg#define KGSL_FLAGS_INITIALIZED0 0x00000002 25e88f27b3Smrg#define KGSL_FLAGS_INITIALIZED 0x00000004 26e88f27b3Smrg#define KGSL_FLAGS_STARTED 0x00000008 27e88f27b3Smrg#define KGSL_FLAGS_ACTIVE 0x00000010 28e88f27b3Smrg#define KGSL_FLAGS_RESERVED0 0x00000020 29e88f27b3Smrg#define KGSL_FLAGS_RESERVED1 0x00000040 30e88f27b3Smrg#define KGSL_FLAGS_RESERVED2 0x00000080 31e88f27b3Smrg#define KGSL_FLAGS_SOFT_RESET 0x00000100 32e88f27b3Smrg#define KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS 0x00000200 33e88f27b3Smrg 343f012e29Smrg/* Clock flags to show which clocks should be controlled by a given platform */ 35e88f27b3Smrg#define KGSL_CLK_SRC 0x00000001 36e88f27b3Smrg#define KGSL_CLK_CORE 0x00000002 37e88f27b3Smrg#define KGSL_CLK_IFACE 0x00000004 38e88f27b3Smrg#define KGSL_CLK_MEM 0x00000008 39e88f27b3Smrg#define KGSL_CLK_MEM_IFACE 0x00000010 40e88f27b3Smrg#define KGSL_CLK_AXI 0x00000020 41e88f27b3Smrg 42e88f27b3Smrg/* 43e88f27b3Smrg * Reset status values for context 44e88f27b3Smrg */ 45e88f27b3Smrgenum kgsl_ctx_reset_stat { 46e88f27b3Smrg KGSL_CTX_STAT_NO_ERROR = 0x00000000, 47e88f27b3Smrg KGSL_CTX_STAT_GUILTY_CONTEXT_RESET_EXT = 0x00000001, 48e88f27b3Smrg KGSL_CTX_STAT_INNOCENT_CONTEXT_RESET_EXT = 0x00000002, 49e88f27b3Smrg KGSL_CTX_STAT_UNKNOWN_CONTEXT_RESET_EXT = 0x00000003 50e88f27b3Smrg}; 51e88f27b3Smrg 52e88f27b3Smrg#define KGSL_MAX_PWRLEVELS 5 53e88f27b3Smrg 54e88f27b3Smrg#define KGSL_CONVERT_TO_MBPS(val) \ 55e88f27b3Smrg (val*1000*1000U) 56e88f27b3Smrg 57e88f27b3Smrg/* device id */ 58e88f27b3Smrgenum kgsl_deviceid { 59e88f27b3Smrg KGSL_DEVICE_3D0 = 0x00000000, 60e88f27b3Smrg KGSL_DEVICE_2D0 = 0x00000001, 61e88f27b3Smrg KGSL_DEVICE_2D1 = 0x00000002, 62e88f27b3Smrg KGSL_DEVICE_MAX = 0x00000003 63e88f27b3Smrg}; 64e88f27b3Smrg 65e88f27b3Smrgenum kgsl_user_mem_type { 66e88f27b3Smrg KGSL_USER_MEM_TYPE_PMEM = 0x00000000, 67e88f27b3Smrg KGSL_USER_MEM_TYPE_ASHMEM = 0x00000001, 68e88f27b3Smrg KGSL_USER_MEM_TYPE_ADDR = 0x00000002, 69e88f27b3Smrg KGSL_USER_MEM_TYPE_ION = 0x00000003, 70e88f27b3Smrg KGSL_USER_MEM_TYPE_MAX = 0x00000004, 71e88f27b3Smrg}; 72e88f27b3Smrg 73e88f27b3Smrgstruct kgsl_devinfo { 74e88f27b3Smrg 75e88f27b3Smrg unsigned int device_id; 76e88f27b3Smrg /* chip revision id 77e88f27b3Smrg * coreid:8 majorrev:8 minorrev:8 patch:8 78e88f27b3Smrg */ 79e88f27b3Smrg unsigned int chip_id; 80e88f27b3Smrg unsigned int mmu_enabled; 81e88f27b3Smrg unsigned int gmem_gpubaseaddr; 82e88f27b3Smrg /* 83e88f27b3Smrg * This field contains the adreno revision 84e88f27b3Smrg * number 200, 205, 220, etc... 85e88f27b3Smrg */ 86e88f27b3Smrg unsigned int gpu_id; 87e88f27b3Smrg unsigned int gmem_sizebytes; 88e88f27b3Smrg}; 89e88f27b3Smrg 90e88f27b3Smrg/* this structure defines the region of memory that can be mmap()ed from this 91e88f27b3Smrg driver. The timestamp fields are volatile because they are written by the 92e88f27b3Smrg GPU 93e88f27b3Smrg*/ 94e88f27b3Smrgstruct kgsl_devmemstore { 95e88f27b3Smrg volatile unsigned int soptimestamp; 96e88f27b3Smrg unsigned int sbz; 97e88f27b3Smrg volatile unsigned int eoptimestamp; 98e88f27b3Smrg unsigned int sbz2; 99e88f27b3Smrg volatile unsigned int ts_cmp_enable; 100e88f27b3Smrg unsigned int sbz3; 101e88f27b3Smrg volatile unsigned int ref_wait_ts; 102e88f27b3Smrg unsigned int sbz4; 103e88f27b3Smrg unsigned int current_context; 104e88f27b3Smrg unsigned int sbz5; 105e88f27b3Smrg}; 106e88f27b3Smrg 107e88f27b3Smrg#define KGSL_MEMSTORE_OFFSET(ctxt_id, field) \ 108e88f27b3Smrg ((ctxt_id)*sizeof(struct kgsl_devmemstore) + \ 109e88f27b3Smrg offsetof(struct kgsl_devmemstore, field)) 110e88f27b3Smrg 111e88f27b3Smrg/* timestamp id*/ 112e88f27b3Smrgenum kgsl_timestamp_type { 113e88f27b3Smrg KGSL_TIMESTAMP_CONSUMED = 0x00000001, /* start-of-pipeline timestamp */ 114e88f27b3Smrg KGSL_TIMESTAMP_RETIRED = 0x00000002, /* end-of-pipeline timestamp*/ 115e88f27b3Smrg KGSL_TIMESTAMP_QUEUED = 0x00000003, 116e88f27b3Smrg}; 117e88f27b3Smrg 118e88f27b3Smrg/* property types - used with kgsl_device_getproperty */ 119e88f27b3Smrgenum kgsl_property_type { 120e88f27b3Smrg KGSL_PROP_DEVICE_INFO = 0x00000001, 121e88f27b3Smrg KGSL_PROP_DEVICE_SHADOW = 0x00000002, 122e88f27b3Smrg KGSL_PROP_DEVICE_POWER = 0x00000003, 123e88f27b3Smrg KGSL_PROP_SHMEM = 0x00000004, 124e88f27b3Smrg KGSL_PROP_SHMEM_APERTURES = 0x00000005, 125e88f27b3Smrg KGSL_PROP_MMU_ENABLE = 0x00000006, 126e88f27b3Smrg KGSL_PROP_INTERRUPT_WAITS = 0x00000007, 127e88f27b3Smrg KGSL_PROP_VERSION = 0x00000008, 128e88f27b3Smrg KGSL_PROP_GPU_RESET_STAT = 0x00000009, 129e88f27b3Smrg KGSL_PROP_PWRCTRL = 0x0000000E, 130e88f27b3Smrg}; 131e88f27b3Smrg 132e88f27b3Smrgstruct kgsl_shadowprop { 133e88f27b3Smrg unsigned int gpuaddr; 134e88f27b3Smrg unsigned int size; 135e88f27b3Smrg unsigned int flags; /* contains KGSL_FLAGS_ values */ 136e88f27b3Smrg}; 137e88f27b3Smrg 138e88f27b3Smrgstruct kgsl_pwrlevel { 139e88f27b3Smrg unsigned int gpu_freq; 140e88f27b3Smrg unsigned int bus_freq; 141e88f27b3Smrg unsigned int io_fraction; 142e88f27b3Smrg}; 143e88f27b3Smrg 144e88f27b3Smrgstruct kgsl_version { 145e88f27b3Smrg unsigned int drv_major; 146e88f27b3Smrg unsigned int drv_minor; 147e88f27b3Smrg unsigned int dev_major; 148e88f27b3Smrg unsigned int dev_minor; 149e88f27b3Smrg}; 150e88f27b3Smrg 151e88f27b3Smrg#ifdef __KERNEL__ 152e88f27b3Smrg 153e88f27b3Smrg#define KGSL_3D0_REG_MEMORY "kgsl_3d0_reg_memory" 154e88f27b3Smrg#define KGSL_3D0_IRQ "kgsl_3d0_irq" 155e88f27b3Smrg#define KGSL_2D0_REG_MEMORY "kgsl_2d0_reg_memory" 156e88f27b3Smrg#define KGSL_2D0_IRQ "kgsl_2d0_irq" 157e88f27b3Smrg#define KGSL_2D1_REG_MEMORY "kgsl_2d1_reg_memory" 158e88f27b3Smrg#define KGSL_2D1_IRQ "kgsl_2d1_irq" 159e88f27b3Smrg 160e88f27b3Smrgenum kgsl_iommu_context_id { 161e88f27b3Smrg KGSL_IOMMU_CONTEXT_USER = 0, 162e88f27b3Smrg KGSL_IOMMU_CONTEXT_PRIV = 1, 163e88f27b3Smrg}; 164e88f27b3Smrg 165e88f27b3Smrgstruct kgsl_iommu_ctx { 166e88f27b3Smrg const char *iommu_ctx_name; 167e88f27b3Smrg enum kgsl_iommu_context_id ctx_id; 168e88f27b3Smrg}; 169e88f27b3Smrg 170e88f27b3Smrgstruct kgsl_device_iommu_data { 171e88f27b3Smrg const struct kgsl_iommu_ctx *iommu_ctxs; 172e88f27b3Smrg int iommu_ctx_count; 173e88f27b3Smrg unsigned int physstart; 174e88f27b3Smrg unsigned int physend; 175e88f27b3Smrg}; 176e88f27b3Smrg 177e88f27b3Smrgstruct kgsl_device_platform_data { 178e88f27b3Smrg struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS]; 179e88f27b3Smrg int init_level; 180e88f27b3Smrg int num_levels; 181e88f27b3Smrg int (*set_grp_async)(void); 182e88f27b3Smrg unsigned int idle_timeout; 183e88f27b3Smrg bool strtstp_sleepwake; 184e88f27b3Smrg unsigned int nap_allowed; 185e88f27b3Smrg unsigned int clk_map; 186e88f27b3Smrg unsigned int idle_needed; 187e88f27b3Smrg struct msm_bus_scale_pdata *bus_scale_table; 188e88f27b3Smrg struct kgsl_device_iommu_data *iommu_data; 189e88f27b3Smrg int iommu_count; 190e88f27b3Smrg struct msm_dcvs_core_info *core_info; 191e88f27b3Smrg}; 192e88f27b3Smrg 193e88f27b3Smrg#endif 194e88f27b3Smrg 195e88f27b3Smrg/* structure holds list of ibs */ 196e88f27b3Smrgstruct kgsl_ibdesc { 197e88f27b3Smrg unsigned int gpuaddr; 198e88f27b3Smrg void *hostptr; 199e88f27b3Smrg unsigned int sizedwords; 200e88f27b3Smrg unsigned int ctrl; 201e88f27b3Smrg}; 202e88f27b3Smrg 203e88f27b3Smrg/* ioctls */ 204e88f27b3Smrg#define KGSL_IOC_TYPE 0x09 205e88f27b3Smrg 206e88f27b3Smrg/* get misc info about the GPU 207e88f27b3Smrg type should be a value from enum kgsl_property_type 208e88f27b3Smrg value points to a structure that varies based on type 209e88f27b3Smrg sizebytes is sizeof() that structure 210e88f27b3Smrg for KGSL_PROP_DEVICE_INFO, use struct kgsl_devinfo 211e88f27b3Smrg this structure contaings hardware versioning info. 212e88f27b3Smrg for KGSL_PROP_DEVICE_SHADOW, use struct kgsl_shadowprop 213e88f27b3Smrg this is used to find mmap() offset and sizes for mapping 214e88f27b3Smrg struct kgsl_memstore into userspace. 215e88f27b3Smrg*/ 216e88f27b3Smrgstruct kgsl_device_getproperty { 217e88f27b3Smrg unsigned int type; 218e88f27b3Smrg void *value; 219e88f27b3Smrg unsigned int sizebytes; 220e88f27b3Smrg}; 221e88f27b3Smrg 222e88f27b3Smrg#define IOCTL_KGSL_DEVICE_GETPROPERTY \ 223e88f27b3Smrg _IOWR(KGSL_IOC_TYPE, 0x2, struct kgsl_device_getproperty) 224e88f27b3Smrg 225e88f27b3Smrg/* IOCTL_KGSL_DEVICE_READ (0x3) - removed 03/2012 226e88f27b3Smrg */ 227e88f27b3Smrg 228e88f27b3Smrg/* block until the GPU has executed past a given timestamp 229e88f27b3Smrg * timeout is in milliseconds. 230e88f27b3Smrg */ 231e88f27b3Smrgstruct kgsl_device_waittimestamp { 232e88f27b3Smrg unsigned int timestamp; 233e88f27b3Smrg unsigned int timeout; 234e88f27b3Smrg}; 235e88f27b3Smrg 236e88f27b3Smrg#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP \ 237e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x6, struct kgsl_device_waittimestamp) 238e88f27b3Smrg 239e88f27b3Smrgstruct kgsl_device_waittimestamp_ctxtid { 240e88f27b3Smrg unsigned int context_id; 241e88f27b3Smrg unsigned int timestamp; 242e88f27b3Smrg unsigned int timeout; 243e88f27b3Smrg}; 244e88f27b3Smrg 245e88f27b3Smrg#define IOCTL_KGSL_DEVICE_WAITTIMESTAMP_CTXTID \ 246e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x7, struct kgsl_device_waittimestamp_ctxtid) 247e88f27b3Smrg 248e88f27b3Smrg/* issue indirect commands to the GPU. 249e88f27b3Smrg * drawctxt_id must have been created with IOCTL_KGSL_DRAWCTXT_CREATE 250e88f27b3Smrg * ibaddr and sizedwords must specify a subset of a buffer created 251e88f27b3Smrg * with IOCTL_KGSL_SHAREDMEM_FROM_PMEM 252e88f27b3Smrg * flags may be a mask of KGSL_CONTEXT_ values 253e88f27b3Smrg * timestamp is a returned counter value which can be passed to 254e88f27b3Smrg * other ioctls to determine when the commands have been executed by 255e88f27b3Smrg * the GPU. 256e88f27b3Smrg */ 257e88f27b3Smrgstruct kgsl_ringbuffer_issueibcmds { 258e88f27b3Smrg unsigned int drawctxt_id; 259e88f27b3Smrg unsigned int ibdesc_addr; 260e88f27b3Smrg unsigned int numibs; 261e88f27b3Smrg unsigned int timestamp; /*output param */ 262e88f27b3Smrg unsigned int flags; 263e88f27b3Smrg}; 264e88f27b3Smrg 265e88f27b3Smrg#define IOCTL_KGSL_RINGBUFFER_ISSUEIBCMDS \ 266e88f27b3Smrg _IOWR(KGSL_IOC_TYPE, 0x10, struct kgsl_ringbuffer_issueibcmds) 267e88f27b3Smrg 268e88f27b3Smrg/* read the most recently executed timestamp value 269e88f27b3Smrg * type should be a value from enum kgsl_timestamp_type 270e88f27b3Smrg */ 271e88f27b3Smrgstruct kgsl_cmdstream_readtimestamp { 272e88f27b3Smrg unsigned int type; 273e88f27b3Smrg unsigned int timestamp; /*output param */ 274e88f27b3Smrg}; 275e88f27b3Smrg 276e88f27b3Smrg#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_OLD \ 277e88f27b3Smrg _IOR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) 278e88f27b3Smrg 279e88f27b3Smrg#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP \ 280e88f27b3Smrg _IOWR(KGSL_IOC_TYPE, 0x11, struct kgsl_cmdstream_readtimestamp) 281e88f27b3Smrg 282e88f27b3Smrg/* free memory when the GPU reaches a given timestamp. 283e88f27b3Smrg * gpuaddr specify a memory region created by a 284e88f27b3Smrg * IOCTL_KGSL_SHAREDMEM_FROM_PMEM call 285e88f27b3Smrg * type should be a value from enum kgsl_timestamp_type 286e88f27b3Smrg */ 287e88f27b3Smrgstruct kgsl_cmdstream_freememontimestamp { 288e88f27b3Smrg unsigned int gpuaddr; 289e88f27b3Smrg unsigned int type; 290e88f27b3Smrg unsigned int timestamp; 291e88f27b3Smrg}; 292e88f27b3Smrg 293e88f27b3Smrg#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP \ 294e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) 295e88f27b3Smrg 296e88f27b3Smrg/* Previous versions of this header had incorrectly defined 297e88f27b3Smrg IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP as a read-only ioctl instead 2983f012e29Smrg of a write only ioctl. To ensure binary compatibility, the following 299e88f27b3Smrg #define will be used to intercept the incorrect ioctl 300e88f27b3Smrg*/ 301e88f27b3Smrg 302e88f27b3Smrg#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_OLD \ 303e88f27b3Smrg _IOR(KGSL_IOC_TYPE, 0x12, struct kgsl_cmdstream_freememontimestamp) 304e88f27b3Smrg 305e88f27b3Smrg/* create a draw context, which is used to preserve GPU state. 306e88f27b3Smrg * The flags field may contain a mask KGSL_CONTEXT_* values 307e88f27b3Smrg */ 308e88f27b3Smrgstruct kgsl_drawctxt_create { 309e88f27b3Smrg unsigned int flags; 310e88f27b3Smrg unsigned int drawctxt_id; /*output param */ 311e88f27b3Smrg}; 312e88f27b3Smrg 313e88f27b3Smrg#define IOCTL_KGSL_DRAWCTXT_CREATE \ 314e88f27b3Smrg _IOWR(KGSL_IOC_TYPE, 0x13, struct kgsl_drawctxt_create) 315e88f27b3Smrg 316e88f27b3Smrg/* destroy a draw context */ 317e88f27b3Smrgstruct kgsl_drawctxt_destroy { 318e88f27b3Smrg unsigned int drawctxt_id; 319e88f27b3Smrg}; 320e88f27b3Smrg 321e88f27b3Smrg#define IOCTL_KGSL_DRAWCTXT_DESTROY \ 322e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x14, struct kgsl_drawctxt_destroy) 323e88f27b3Smrg 324e88f27b3Smrg/* add a block of pmem, fb, ashmem or user allocated address 325e88f27b3Smrg * into the GPU address space */ 326e88f27b3Smrgstruct kgsl_map_user_mem { 327e88f27b3Smrg int fd; 328e88f27b3Smrg unsigned int gpuaddr; /*output param */ 329e88f27b3Smrg unsigned int len; 330e88f27b3Smrg unsigned int offset; 331e88f27b3Smrg unsigned int hostptr; /*input param */ 332e88f27b3Smrg enum kgsl_user_mem_type memtype; 333e88f27b3Smrg unsigned int reserved; /* May be required to add 334e88f27b3Smrg params for another mem type */ 335e88f27b3Smrg}; 336e88f27b3Smrg 337e88f27b3Smrg#define IOCTL_KGSL_MAP_USER_MEM \ 338e88f27b3Smrg _IOWR(KGSL_IOC_TYPE, 0x15, struct kgsl_map_user_mem) 339e88f27b3Smrg 340e88f27b3Smrgstruct kgsl_cmdstream_readtimestamp_ctxtid { 341e88f27b3Smrg unsigned int context_id; 342e88f27b3Smrg unsigned int type; 343e88f27b3Smrg unsigned int timestamp; /*output param */ 344e88f27b3Smrg}; 345e88f27b3Smrg 346e88f27b3Smrg#define IOCTL_KGSL_CMDSTREAM_READTIMESTAMP_CTXTID \ 347e88f27b3Smrg _IOWR(KGSL_IOC_TYPE, 0x16, struct kgsl_cmdstream_readtimestamp_ctxtid) 348e88f27b3Smrg 349e88f27b3Smrgstruct kgsl_cmdstream_freememontimestamp_ctxtid { 350e88f27b3Smrg unsigned int context_id; 351e88f27b3Smrg unsigned int gpuaddr; 352e88f27b3Smrg unsigned int type; 353e88f27b3Smrg unsigned int timestamp; 354e88f27b3Smrg}; 355e88f27b3Smrg 356e88f27b3Smrg#define IOCTL_KGSL_CMDSTREAM_FREEMEMONTIMESTAMP_CTXTID \ 357e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x17, \ 358e88f27b3Smrg struct kgsl_cmdstream_freememontimestamp_ctxtid) 359e88f27b3Smrg 360e88f27b3Smrg/* add a block of pmem or fb into the GPU address space */ 361e88f27b3Smrgstruct kgsl_sharedmem_from_pmem { 362e88f27b3Smrg int pmem_fd; 363e88f27b3Smrg unsigned int gpuaddr; /*output param */ 364e88f27b3Smrg unsigned int len; 365e88f27b3Smrg unsigned int offset; 366e88f27b3Smrg}; 367e88f27b3Smrg 368e88f27b3Smrg#define IOCTL_KGSL_SHAREDMEM_FROM_PMEM \ 369e88f27b3Smrg _IOWR(KGSL_IOC_TYPE, 0x20, struct kgsl_sharedmem_from_pmem) 370e88f27b3Smrg 371e88f27b3Smrg/* remove memory from the GPU's address space */ 372e88f27b3Smrgstruct kgsl_sharedmem_free { 373e88f27b3Smrg unsigned int gpuaddr; 374e88f27b3Smrg}; 375e88f27b3Smrg 376e88f27b3Smrg#define IOCTL_KGSL_SHAREDMEM_FREE \ 377e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x21, struct kgsl_sharedmem_free) 378e88f27b3Smrg 379e88f27b3Smrgstruct kgsl_cff_user_event { 380e88f27b3Smrg unsigned char cff_opcode; 381e88f27b3Smrg unsigned int op1; 382e88f27b3Smrg unsigned int op2; 383e88f27b3Smrg unsigned int op3; 384e88f27b3Smrg unsigned int op4; 385e88f27b3Smrg unsigned int op5; 386e88f27b3Smrg unsigned int __pad[2]; 387e88f27b3Smrg}; 388e88f27b3Smrg 389e88f27b3Smrg#define IOCTL_KGSL_CFF_USER_EVENT \ 390e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_cff_user_event) 391e88f27b3Smrg 392e88f27b3Smrgstruct kgsl_gmem_desc { 393e88f27b3Smrg unsigned int x; 394e88f27b3Smrg unsigned int y; 395e88f27b3Smrg unsigned int width; 396e88f27b3Smrg unsigned int height; 397e88f27b3Smrg unsigned int pitch; 398e88f27b3Smrg}; 399e88f27b3Smrg 400e88f27b3Smrgstruct kgsl_buffer_desc { 401e88f27b3Smrg void *hostptr; 402e88f27b3Smrg unsigned int gpuaddr; 403e88f27b3Smrg int size; 404e88f27b3Smrg unsigned int format; 405e88f27b3Smrg unsigned int pitch; 406e88f27b3Smrg unsigned int enabled; 407e88f27b3Smrg}; 408e88f27b3Smrg 409e88f27b3Smrgstruct kgsl_bind_gmem_shadow { 410e88f27b3Smrg unsigned int drawctxt_id; 411e88f27b3Smrg struct kgsl_gmem_desc gmem_desc; 412e88f27b3Smrg unsigned int shadow_x; 413e88f27b3Smrg unsigned int shadow_y; 414e88f27b3Smrg struct kgsl_buffer_desc shadow_buffer; 415e88f27b3Smrg unsigned int buffer_id; 416e88f27b3Smrg}; 417e88f27b3Smrg 418e88f27b3Smrg#define IOCTL_KGSL_DRAWCTXT_BIND_GMEM_SHADOW \ 419e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x22, struct kgsl_bind_gmem_shadow) 420e88f27b3Smrg 421e88f27b3Smrg/* add a block of memory into the GPU address space */ 422e88f27b3Smrgstruct kgsl_sharedmem_from_vmalloc { 423e88f27b3Smrg unsigned int gpuaddr; /*output param */ 424e88f27b3Smrg unsigned int hostptr; 425e88f27b3Smrg unsigned int flags; 426e88f27b3Smrg}; 427e88f27b3Smrg 428e88f27b3Smrg#define IOCTL_KGSL_SHAREDMEM_FROM_VMALLOC \ 429e88f27b3Smrg _IOWR(KGSL_IOC_TYPE, 0x23, struct kgsl_sharedmem_from_vmalloc) 430e88f27b3Smrg 431e88f27b3Smrg#define IOCTL_KGSL_SHAREDMEM_FLUSH_CACHE \ 432e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x24, struct kgsl_sharedmem_free) 433e88f27b3Smrg 434e88f27b3Smrgstruct kgsl_drawctxt_set_bin_base_offset { 435e88f27b3Smrg unsigned int drawctxt_id; 436e88f27b3Smrg unsigned int offset; 437e88f27b3Smrg}; 438e88f27b3Smrg 439e88f27b3Smrg#define IOCTL_KGSL_DRAWCTXT_SET_BIN_BASE_OFFSET \ 440e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x25, struct kgsl_drawctxt_set_bin_base_offset) 441e88f27b3Smrg 442e88f27b3Smrgenum kgsl_cmdwindow_type { 443e88f27b3Smrg KGSL_CMDWINDOW_MIN = 0x00000000, 444e88f27b3Smrg KGSL_CMDWINDOW_2D = 0x00000000, 445e88f27b3Smrg KGSL_CMDWINDOW_3D = 0x00000001, /* legacy */ 446e88f27b3Smrg KGSL_CMDWINDOW_MMU = 0x00000002, 447e88f27b3Smrg KGSL_CMDWINDOW_ARBITER = 0x000000FF, 448e88f27b3Smrg KGSL_CMDWINDOW_MAX = 0x000000FF, 449e88f27b3Smrg}; 450e88f27b3Smrg 451e88f27b3Smrg/* write to the command window */ 452e88f27b3Smrgstruct kgsl_cmdwindow_write { 453e88f27b3Smrg enum kgsl_cmdwindow_type target; 454e88f27b3Smrg unsigned int addr; 455e88f27b3Smrg unsigned int data; 456e88f27b3Smrg}; 457e88f27b3Smrg 458e88f27b3Smrg#define IOCTL_KGSL_CMDWINDOW_WRITE \ 459e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x2e, struct kgsl_cmdwindow_write) 460e88f27b3Smrg 461e88f27b3Smrgstruct kgsl_gpumem_alloc { 462e88f27b3Smrg unsigned long gpuaddr; 463e88f27b3Smrg size_t size; 464e88f27b3Smrg unsigned int flags; 465e88f27b3Smrg}; 466e88f27b3Smrg 467e88f27b3Smrg#define IOCTL_KGSL_GPUMEM_ALLOC \ 468e88f27b3Smrg _IOWR(KGSL_IOC_TYPE, 0x2f, struct kgsl_gpumem_alloc) 469e88f27b3Smrg 470e88f27b3Smrgstruct kgsl_cff_syncmem { 471e88f27b3Smrg unsigned int gpuaddr; 472e88f27b3Smrg unsigned int len; 473e88f27b3Smrg unsigned int __pad[2]; /* For future binary compatibility */ 474e88f27b3Smrg}; 475e88f27b3Smrg 476e88f27b3Smrg#define IOCTL_KGSL_CFF_SYNCMEM \ 477e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x30, struct kgsl_cff_syncmem) 478e88f27b3Smrg 479e88f27b3Smrg/* 480e88f27b3Smrg * A timestamp event allows the user space to register an action following an 481e88f27b3Smrg * expired timestamp. 482e88f27b3Smrg */ 483e88f27b3Smrg 484e88f27b3Smrgstruct kgsl_timestamp_event { 485e88f27b3Smrg int type; /* Type of event (see list below) */ 486e88f27b3Smrg unsigned int timestamp; /* Timestamp to trigger event on */ 487e88f27b3Smrg unsigned int context_id; /* Context for the timestamp */ 488e88f27b3Smrg void *priv; /* Pointer to the event specific blob */ 489e88f27b3Smrg size_t len; /* Size of the event specific blob */ 490e88f27b3Smrg}; 491e88f27b3Smrg 492e88f27b3Smrg#define IOCTL_KGSL_TIMESTAMP_EVENT \ 493e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x31, struct kgsl_timestamp_event) 494e88f27b3Smrg 495e88f27b3Smrg/* A genlock timestamp event releases an existing lock on timestamp expire */ 496e88f27b3Smrg 497e88f27b3Smrg#define KGSL_TIMESTAMP_EVENT_GENLOCK 1 498e88f27b3Smrg 499e88f27b3Smrgstruct kgsl_timestamp_event_genlock { 500e88f27b3Smrg int handle; /* Handle of the genlock lock to release */ 501e88f27b3Smrg}; 502e88f27b3Smrg 503e88f27b3Smrg/* 504e88f27b3Smrg * Set a property within the kernel. Uses the same structure as 505e88f27b3Smrg * IOCTL_KGSL_GETPROPERTY 506e88f27b3Smrg */ 507e88f27b3Smrg 508e88f27b3Smrg#define IOCTL_KGSL_SETPROPERTY \ 509e88f27b3Smrg _IOW(KGSL_IOC_TYPE, 0x32, struct kgsl_device_getproperty) 510e88f27b3Smrg 511e88f27b3Smrg#ifdef __KERNEL__ 512e88f27b3Smrg#ifdef CONFIG_MSM_KGSL_DRM 513e88f27b3Smrgint kgsl_gem_obj_addr(int drm_fd, int handle, unsigned long *start, 514e88f27b3Smrg unsigned long *len); 515e88f27b3Smrg#else 516e88f27b3Smrg#define kgsl_gem_obj_addr(...) 0 517e88f27b3Smrg#endif 518e88f27b3Smrg#endif 519e88f27b3Smrg#endif /* _MSM_KGSL_H */ 520