amdgpu_drm.h revision 037b3c26
1/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32#ifndef __AMDGPU_DRM_H__ 33#define __AMDGPU_DRM_H__ 34 35#include "drm.h" 36 37#if defined(__cplusplus) 38extern "C" { 39#endif 40 41#define DRM_AMDGPU_GEM_CREATE 0x00 42#define DRM_AMDGPU_GEM_MMAP 0x01 43#define DRM_AMDGPU_CTX 0x02 44#define DRM_AMDGPU_BO_LIST 0x03 45#define DRM_AMDGPU_CS 0x04 46#define DRM_AMDGPU_INFO 0x05 47#define DRM_AMDGPU_GEM_METADATA 0x06 48#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49#define DRM_AMDGPU_GEM_VA 0x08 50#define DRM_AMDGPU_WAIT_CS 0x09 51#define DRM_AMDGPU_GEM_OP 0x10 52#define DRM_AMDGPU_GEM_USERPTR 0x11 53 54#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 55#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 56#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 57#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 58#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 59#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 60#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 61#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 62#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 63#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 64#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 65#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 66 67#define AMDGPU_GEM_DOMAIN_CPU 0x1 68#define AMDGPU_GEM_DOMAIN_GTT 0x2 69#define AMDGPU_GEM_DOMAIN_VRAM 0x4 70#define AMDGPU_GEM_DOMAIN_GDS 0x8 71#define AMDGPU_GEM_DOMAIN_GWS 0x10 72#define AMDGPU_GEM_DOMAIN_OA 0x20 73 74/* Flag that CPU access will be required for the case of VRAM domain */ 75#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 76/* Flag that CPU access will not work, this VRAM domain is invisible */ 77#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 78/* Flag that USWC attributes should be used for GTT */ 79#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 80/* Flag that the memory should be in VRAM and cleared */ 81#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 82 83struct drm_amdgpu_gem_create_in { 84 /** the requested memory size */ 85 uint64_t bo_size; 86 /** physical start_addr alignment in bytes for some HW requirements */ 87 uint64_t alignment; 88 /** the requested memory domains */ 89 uint64_t domains; 90 /** allocation flags */ 91 uint64_t domain_flags; 92}; 93 94struct drm_amdgpu_gem_create_out { 95 /** returned GEM object handle */ 96 uint32_t handle; 97 uint32_t _pad; 98}; 99 100union drm_amdgpu_gem_create { 101 struct drm_amdgpu_gem_create_in in; 102 struct drm_amdgpu_gem_create_out out; 103}; 104 105/** Opcode to create new residency list. */ 106#define AMDGPU_BO_LIST_OP_CREATE 0 107/** Opcode to destroy previously created residency list */ 108#define AMDGPU_BO_LIST_OP_DESTROY 1 109/** Opcode to update resource information in the list */ 110#define AMDGPU_BO_LIST_OP_UPDATE 2 111 112struct drm_amdgpu_bo_list_in { 113 /** Type of operation */ 114 uint32_t operation; 115 /** Handle of list or 0 if we want to create one */ 116 uint32_t list_handle; 117 /** Number of BOs in list */ 118 uint32_t bo_number; 119 /** Size of each element describing BO */ 120 uint32_t bo_info_size; 121 /** Pointer to array describing BOs */ 122 uint64_t bo_info_ptr; 123}; 124 125struct drm_amdgpu_bo_list_entry { 126 /** Handle of BO */ 127 uint32_t bo_handle; 128 /** New (if specified) BO priority to be used during migration */ 129 uint32_t bo_priority; 130}; 131 132struct drm_amdgpu_bo_list_out { 133 /** Handle of resource list */ 134 uint32_t list_handle; 135 uint32_t _pad; 136}; 137 138union drm_amdgpu_bo_list { 139 struct drm_amdgpu_bo_list_in in; 140 struct drm_amdgpu_bo_list_out out; 141}; 142 143/* context related */ 144#define AMDGPU_CTX_OP_ALLOC_CTX 1 145#define AMDGPU_CTX_OP_FREE_CTX 2 146#define AMDGPU_CTX_OP_QUERY_STATE 3 147 148/* GPU reset status */ 149#define AMDGPU_CTX_NO_RESET 0 150/* this the context caused it */ 151#define AMDGPU_CTX_GUILTY_RESET 1 152/* some other context caused it */ 153#define AMDGPU_CTX_INNOCENT_RESET 2 154/* unknown cause */ 155#define AMDGPU_CTX_UNKNOWN_RESET 3 156 157struct drm_amdgpu_ctx_in { 158 /** AMDGPU_CTX_OP_* */ 159 uint32_t op; 160 /** For future use, no flags defined so far */ 161 uint32_t flags; 162 uint32_t ctx_id; 163 uint32_t _pad; 164}; 165 166union drm_amdgpu_ctx_out { 167 struct { 168 uint32_t ctx_id; 169 uint32_t _pad; 170 } alloc; 171 172 struct { 173 /** For future use, no flags defined so far */ 174 uint64_t flags; 175 /** Number of resets caused by this context so far. */ 176 uint32_t hangs; 177 /** Reset status since the last call of the ioctl. */ 178 uint32_t reset_status; 179 } state; 180}; 181 182union drm_amdgpu_ctx { 183 struct drm_amdgpu_ctx_in in; 184 union drm_amdgpu_ctx_out out; 185}; 186 187/* 188 * This is not a reliable API and you should expect it to fail for any 189 * number of reasons and have fallback path that do not use userptr to 190 * perform any operation. 191 */ 192#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 193#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 194#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 195#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 196 197struct drm_amdgpu_gem_userptr { 198 uint64_t addr; 199 uint64_t size; 200 /* AMDGPU_GEM_USERPTR_* */ 201 uint32_t flags; 202 /* Resulting GEM handle */ 203 uint32_t handle; 204}; 205 206/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 207#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 208#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 209#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 210#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 211#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 212#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 213#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 214#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 215#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 216#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 217#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 218#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 219#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 220#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 221#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 222#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 223 224#define AMDGPU_TILING_SET(field, value) \ 225 (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 226#define AMDGPU_TILING_GET(value, field) \ 227 (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 228 229#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 230#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 231 232/** The same structure is shared for input/output */ 233struct drm_amdgpu_gem_metadata { 234 /** GEM Object handle */ 235 uint32_t handle; 236 /** Do we want get or set metadata */ 237 uint32_t op; 238 struct { 239 /** For future use, no flags defined so far */ 240 uint64_t flags; 241 /** family specific tiling info */ 242 uint64_t tiling_info; 243 uint32_t data_size_bytes; 244 uint32_t data[64]; 245 } data; 246}; 247 248struct drm_amdgpu_gem_mmap_in { 249 /** the GEM object handle */ 250 uint32_t handle; 251 uint32_t _pad; 252}; 253 254struct drm_amdgpu_gem_mmap_out { 255 /** mmap offset from the vma offset manager */ 256 uint64_t addr_ptr; 257}; 258 259union drm_amdgpu_gem_mmap { 260 struct drm_amdgpu_gem_mmap_in in; 261 struct drm_amdgpu_gem_mmap_out out; 262}; 263 264struct drm_amdgpu_gem_wait_idle_in { 265 /** GEM object handle */ 266 uint32_t handle; 267 /** For future use, no flags defined so far */ 268 uint32_t flags; 269 /** Absolute timeout to wait */ 270 uint64_t timeout; 271}; 272 273struct drm_amdgpu_gem_wait_idle_out { 274 /** BO status: 0 - BO is idle, 1 - BO is busy */ 275 uint32_t status; 276 /** Returned current memory domain */ 277 uint32_t domain; 278}; 279 280union drm_amdgpu_gem_wait_idle { 281 struct drm_amdgpu_gem_wait_idle_in in; 282 struct drm_amdgpu_gem_wait_idle_out out; 283}; 284 285struct drm_amdgpu_wait_cs_in { 286 /** Command submission handle */ 287 uint64_t handle; 288 /** Absolute timeout to wait */ 289 uint64_t timeout; 290 uint32_t ip_type; 291 uint32_t ip_instance; 292 uint32_t ring; 293 uint32_t ctx_id; 294}; 295 296struct drm_amdgpu_wait_cs_out { 297 /** CS status: 0 - CS completed, 1 - CS still busy */ 298 uint64_t status; 299}; 300 301union drm_amdgpu_wait_cs { 302 struct drm_amdgpu_wait_cs_in in; 303 struct drm_amdgpu_wait_cs_out out; 304}; 305 306#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 307#define AMDGPU_GEM_OP_SET_PLACEMENT 1 308 309/* Sets or returns a value associated with a buffer. */ 310struct drm_amdgpu_gem_op { 311 /** GEM object handle */ 312 uint32_t handle; 313 /** AMDGPU_GEM_OP_* */ 314 uint32_t op; 315 /** Input or return value */ 316 uint64_t value; 317}; 318 319#define AMDGPU_VA_OP_MAP 1 320#define AMDGPU_VA_OP_UNMAP 2 321 322/* Delay the page table update till the next CS */ 323#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 324 325/* Mapping flags */ 326/* readable mapping */ 327#define AMDGPU_VM_PAGE_READABLE (1 << 1) 328/* writable mapping */ 329#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 330/* executable mapping, new for VI */ 331#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 332 333struct drm_amdgpu_gem_va { 334 /** GEM object handle */ 335 uint32_t handle; 336 uint32_t _pad; 337 /** AMDGPU_VA_OP_* */ 338 uint32_t operation; 339 /** AMDGPU_VM_PAGE_* */ 340 uint32_t flags; 341 /** va address to assign . Must be correctly aligned.*/ 342 uint64_t va_address; 343 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 344 uint64_t offset_in_bo; 345 /** Specify mapping size. Must be correctly aligned. */ 346 uint64_t map_size; 347}; 348 349#define AMDGPU_HW_IP_GFX 0 350#define AMDGPU_HW_IP_COMPUTE 1 351#define AMDGPU_HW_IP_DMA 2 352#define AMDGPU_HW_IP_UVD 3 353#define AMDGPU_HW_IP_VCE 4 354#define AMDGPU_HW_IP_NUM 5 355 356#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 357 358#define AMDGPU_CHUNK_ID_IB 0x01 359#define AMDGPU_CHUNK_ID_FENCE 0x02 360#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 361 362struct drm_amdgpu_cs_chunk { 363 uint32_t chunk_id; 364 uint32_t length_dw; 365 uint64_t chunk_data; 366}; 367 368struct drm_amdgpu_cs_in { 369 /** Rendering context id */ 370 uint32_t ctx_id; 371 /** Handle of resource list associated with CS */ 372 uint32_t bo_list_handle; 373 uint32_t num_chunks; 374 uint32_t _pad; 375 /** this points to uint64_t * which point to cs chunks */ 376 uint64_t chunks; 377}; 378 379struct drm_amdgpu_cs_out { 380 uint64_t handle; 381}; 382 383union drm_amdgpu_cs { 384 struct drm_amdgpu_cs_in in; 385 struct drm_amdgpu_cs_out out; 386}; 387 388/* Specify flags to be used for IB */ 389 390/* This IB should be submitted to CE */ 391#define AMDGPU_IB_FLAG_CE (1<<0) 392 393/* CE Preamble */ 394#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 395 396struct drm_amdgpu_cs_chunk_ib { 397 uint32_t _pad; 398 /** AMDGPU_IB_FLAG_* */ 399 uint32_t flags; 400 /** Virtual address to begin IB execution */ 401 uint64_t va_start; 402 /** Size of submission */ 403 uint32_t ib_bytes; 404 /** HW IP to submit to */ 405 uint32_t ip_type; 406 /** HW IP index of the same type to submit to */ 407 uint32_t ip_instance; 408 /** Ring index to submit to */ 409 uint32_t ring; 410}; 411 412struct drm_amdgpu_cs_chunk_dep { 413 uint32_t ip_type; 414 uint32_t ip_instance; 415 uint32_t ring; 416 uint32_t ctx_id; 417 uint64_t handle; 418}; 419 420struct drm_amdgpu_cs_chunk_fence { 421 uint32_t handle; 422 uint32_t offset; 423}; 424 425struct drm_amdgpu_cs_chunk_data { 426 union { 427 struct drm_amdgpu_cs_chunk_ib ib_data; 428 struct drm_amdgpu_cs_chunk_fence fence_data; 429 }; 430}; 431 432/** 433 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 434 * 435 */ 436#define AMDGPU_IDS_FLAGS_FUSION 0x1 437 438/* indicate if acceleration can be working */ 439#define AMDGPU_INFO_ACCEL_WORKING 0x00 440/* get the crtc_id from the mode object id? */ 441#define AMDGPU_INFO_CRTC_FROM_ID 0x01 442/* query hw IP info */ 443#define AMDGPU_INFO_HW_IP_INFO 0x02 444/* query hw IP instance count for the specified type */ 445#define AMDGPU_INFO_HW_IP_COUNT 0x03 446/* timestamp for GL_ARB_timer_query */ 447#define AMDGPU_INFO_TIMESTAMP 0x05 448/* Query the firmware version */ 449#define AMDGPU_INFO_FW_VERSION 0x0e 450 /* Subquery id: Query VCE firmware version */ 451 #define AMDGPU_INFO_FW_VCE 0x1 452 /* Subquery id: Query UVD firmware version */ 453 #define AMDGPU_INFO_FW_UVD 0x2 454 /* Subquery id: Query GMC firmware version */ 455 #define AMDGPU_INFO_FW_GMC 0x03 456 /* Subquery id: Query GFX ME firmware version */ 457 #define AMDGPU_INFO_FW_GFX_ME 0x04 458 /* Subquery id: Query GFX PFP firmware version */ 459 #define AMDGPU_INFO_FW_GFX_PFP 0x05 460 /* Subquery id: Query GFX CE firmware version */ 461 #define AMDGPU_INFO_FW_GFX_CE 0x06 462 /* Subquery id: Query GFX RLC firmware version */ 463 #define AMDGPU_INFO_FW_GFX_RLC 0x07 464 /* Subquery id: Query GFX MEC firmware version */ 465 #define AMDGPU_INFO_FW_GFX_MEC 0x08 466 /* Subquery id: Query SMC firmware version */ 467 #define AMDGPU_INFO_FW_SMC 0x0a 468 /* Subquery id: Query SDMA firmware version */ 469 #define AMDGPU_INFO_FW_SDMA 0x0b 470/* number of bytes moved for TTM migration */ 471#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 472/* the used VRAM size */ 473#define AMDGPU_INFO_VRAM_USAGE 0x10 474/* the used GTT size */ 475#define AMDGPU_INFO_GTT_USAGE 0x11 476/* Information about GDS, etc. resource configuration */ 477#define AMDGPU_INFO_GDS_CONFIG 0x13 478/* Query information about VRAM and GTT domains */ 479#define AMDGPU_INFO_VRAM_GTT 0x14 480/* Query information about register in MMR address space*/ 481#define AMDGPU_INFO_READ_MMR_REG 0x15 482/* Query information about device: rev id, family, etc. */ 483#define AMDGPU_INFO_DEV_INFO 0x16 484/* visible vram usage */ 485#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 486 487#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 488#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 489#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 490#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 491 492struct drm_amdgpu_query_fw { 493 /** AMDGPU_INFO_FW_* */ 494 uint32_t fw_type; 495 /** 496 * Index of the IP if there are more IPs of 497 * the same type. 498 */ 499 uint32_t ip_instance; 500 /** 501 * Index of the engine. Whether this is used depends 502 * on the firmware type. (e.g. MEC, SDMA) 503 */ 504 uint32_t index; 505 uint32_t _pad; 506}; 507 508/* Input structure for the INFO ioctl */ 509struct drm_amdgpu_info { 510 /* Where the return value will be stored */ 511 uint64_t return_pointer; 512 /* The size of the return value. Just like "size" in "snprintf", 513 * it limits how many bytes the kernel can write. */ 514 uint32_t return_size; 515 /* The query request id. */ 516 uint32_t query; 517 518 union { 519 struct { 520 uint32_t id; 521 uint32_t _pad; 522 } mode_crtc; 523 524 struct { 525 /** AMDGPU_HW_IP_* */ 526 uint32_t type; 527 /** 528 * Index of the IP if there are more IPs of the same 529 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 530 */ 531 uint32_t ip_instance; 532 } query_hw_ip; 533 534 struct { 535 uint32_t dword_offset; 536 /** number of registers to read */ 537 uint32_t count; 538 uint32_t instance; 539 /** For future use, no flags defined so far */ 540 uint32_t flags; 541 } read_mmr_reg; 542 543 struct drm_amdgpu_query_fw query_fw; 544 }; 545}; 546 547struct drm_amdgpu_info_gds { 548 /** GDS GFX partition size */ 549 uint32_t gds_gfx_partition_size; 550 /** GDS compute partition size */ 551 uint32_t compute_partition_size; 552 /** total GDS memory size */ 553 uint32_t gds_total_size; 554 /** GWS size per GFX partition */ 555 uint32_t gws_per_gfx_partition; 556 /** GSW size per compute partition */ 557 uint32_t gws_per_compute_partition; 558 /** OA size per GFX partition */ 559 uint32_t oa_per_gfx_partition; 560 /** OA size per compute partition */ 561 uint32_t oa_per_compute_partition; 562 uint32_t _pad; 563}; 564 565struct drm_amdgpu_info_vram_gtt { 566 uint64_t vram_size; 567 uint64_t vram_cpu_accessible_size; 568 uint64_t gtt_size; 569}; 570 571struct drm_amdgpu_info_firmware { 572 uint32_t ver; 573 uint32_t feature; 574}; 575 576#define AMDGPU_VRAM_TYPE_UNKNOWN 0 577#define AMDGPU_VRAM_TYPE_GDDR1 1 578#define AMDGPU_VRAM_TYPE_DDR2 2 579#define AMDGPU_VRAM_TYPE_GDDR3 3 580#define AMDGPU_VRAM_TYPE_GDDR4 4 581#define AMDGPU_VRAM_TYPE_GDDR5 5 582#define AMDGPU_VRAM_TYPE_HBM 6 583#define AMDGPU_VRAM_TYPE_DDR3 7 584 585struct drm_amdgpu_info_device { 586 /** PCI Device ID */ 587 uint32_t device_id; 588 /** Internal chip revision: A0, A1, etc.) */ 589 uint32_t chip_rev; 590 uint32_t external_rev; 591 /** Revision id in PCI Config space */ 592 uint32_t pci_rev; 593 uint32_t family; 594 uint32_t num_shader_engines; 595 uint32_t num_shader_arrays_per_engine; 596 /* in KHz */ 597 uint32_t gpu_counter_freq; 598 uint64_t max_engine_clock; 599 uint64_t max_memory_clock; 600 /* cu information */ 601 uint32_t cu_active_number; 602 uint32_t cu_ao_mask; 603 uint32_t cu_bitmap[4][4]; 604 /** Render backend pipe mask. One render backend is CB+DB. */ 605 uint32_t enabled_rb_pipes_mask; 606 uint32_t num_rb_pipes; 607 uint32_t num_hw_gfx_contexts; 608 uint32_t _pad; 609 uint64_t ids_flags; 610 /** Starting virtual address for UMDs. */ 611 uint64_t virtual_address_offset; 612 /** The maximum virtual address */ 613 uint64_t virtual_address_max; 614 /** Required alignment of virtual addresses. */ 615 uint32_t virtual_address_alignment; 616 /** Page table entry - fragment size */ 617 uint32_t pte_fragment_size; 618 uint32_t gart_page_size; 619 /** constant engine ram size*/ 620 uint32_t ce_ram_size; 621 /** video memory type info*/ 622 uint32_t vram_type; 623 /** video memory bit width*/ 624 uint32_t vram_bit_width; 625 /* vce harvesting instance */ 626 uint32_t vce_harvest_config; 627}; 628 629struct drm_amdgpu_info_hw_ip { 630 /** Version of h/w IP */ 631 uint32_t hw_ip_version_major; 632 uint32_t hw_ip_version_minor; 633 /** Capabilities */ 634 uint64_t capabilities_flags; 635 /** command buffer address start alignment*/ 636 uint32_t ib_start_alignment; 637 /** command buffer size alignment*/ 638 uint32_t ib_size_alignment; 639 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 640 uint32_t available_rings; 641 uint32_t _pad; 642}; 643 644/* 645 * Supported GPU families 646 */ 647#define AMDGPU_FAMILY_UNKNOWN 0 648#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 649#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 650#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 651#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 652 653#if defined(__cplusplus) 654} 655#endif 656 657#endif 658