amdgpu_drm.h revision bbff01ce
1/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32#ifndef __AMDGPU_DRM_H__ 33#define __AMDGPU_DRM_H__ 34 35#include "drm.h" 36 37#if defined(__cplusplus) 38extern "C" { 39#endif 40 41#define DRM_AMDGPU_GEM_CREATE 0x00 42#define DRM_AMDGPU_GEM_MMAP 0x01 43#define DRM_AMDGPU_CTX 0x02 44#define DRM_AMDGPU_BO_LIST 0x03 45#define DRM_AMDGPU_CS 0x04 46#define DRM_AMDGPU_INFO 0x05 47#define DRM_AMDGPU_GEM_METADATA 0x06 48#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49#define DRM_AMDGPU_GEM_VA 0x08 50#define DRM_AMDGPU_WAIT_CS 0x09 51#define DRM_AMDGPU_GEM_OP 0x10 52#define DRM_AMDGPU_GEM_USERPTR 0x11 53#define DRM_AMDGPU_WAIT_FENCES 0x12 54#define DRM_AMDGPU_VM 0x13 55#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56#define DRM_AMDGPU_SCHED 0x15 57 58#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75/** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linearized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 * 98 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 99 * signalling user mode queues. 100 */ 101#define AMDGPU_GEM_DOMAIN_CPU 0x1 102#define AMDGPU_GEM_DOMAIN_GTT 0x2 103#define AMDGPU_GEM_DOMAIN_VRAM 0x4 104#define AMDGPU_GEM_DOMAIN_GDS 0x8 105#define AMDGPU_GEM_DOMAIN_GWS 0x10 106#define AMDGPU_GEM_DOMAIN_OA 0x20 107#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 108#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 109 AMDGPU_GEM_DOMAIN_GTT | \ 110 AMDGPU_GEM_DOMAIN_VRAM | \ 111 AMDGPU_GEM_DOMAIN_GDS | \ 112 AMDGPU_GEM_DOMAIN_GWS | \ 113 AMDGPU_GEM_DOMAIN_OA | \ 114 AMDGPU_GEM_DOMAIN_DOORBELL) 115 116/* Flag that CPU access will be required for the case of VRAM domain */ 117#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 118/* Flag that CPU access will not work, this VRAM domain is invisible */ 119#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 120/* Flag that USWC attributes should be used for GTT */ 121#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 122/* Flag that the memory should be in VRAM and cleared */ 123#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 124/* Flag that allocating the BO should use linear VRAM */ 125#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 126/* Flag that BO is always valid in this VM */ 127#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 128/* Flag that BO sharing will be explicitly synchronized */ 129#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 130/* Flag that indicates allocating MQD gart on GFX9, where the mtype 131 * for the second page onward should be set to NC. It should never 132 * be used by user space applications. 133 */ 134#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 135/* Flag that BO may contain sensitive data that must be wiped before 136 * releasing the memory 137 */ 138#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 139/* Flag that BO will be encrypted and that the TMZ bit should be 140 * set in the PTEs when mapping this buffer via GPUVM or 141 * accessing it with various hw blocks 142 */ 143#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 144/* Flag that BO will be used only in preemptible context, which does 145 * not require GTT memory accounting 146 */ 147#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 148/* Flag that BO can be discarded under memory pressure without keeping the 149 * content. 150 */ 151#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 152/* Flag that BO is shared coherently between multiple devices or CPU threads. 153 * May depend on GPU instructions to flush caches to system scope explicitly. 154 * 155 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 156 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 157 */ 158#define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 159/* Flag that BO should not be cached by GPU. Coherent without having to flush 160 * GPU caches explicitly 161 * 162 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 163 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 164 */ 165#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 166/* Flag that BO should be coherent across devices when using device-level 167 * atomics. May depend on GPU instructions to flush caches to device scope 168 * explicitly, promoting them to system scope automatically. 169 * 170 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 171 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 172 */ 173#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 174 175struct drm_amdgpu_gem_create_in { 176 /** the requested memory size */ 177 __u64 bo_size; 178 /** physical start_addr alignment in bytes for some HW requirements */ 179 __u64 alignment; 180 /** the requested memory domains */ 181 __u64 domains; 182 /** allocation flags */ 183 __u64 domain_flags; 184}; 185 186struct drm_amdgpu_gem_create_out { 187 /** returned GEM object handle */ 188 __u32 handle; 189 __u32 _pad; 190}; 191 192union drm_amdgpu_gem_create { 193 struct drm_amdgpu_gem_create_in in; 194 struct drm_amdgpu_gem_create_out out; 195}; 196 197/** Opcode to create new residency list. */ 198#define AMDGPU_BO_LIST_OP_CREATE 0 199/** Opcode to destroy previously created residency list */ 200#define AMDGPU_BO_LIST_OP_DESTROY 1 201/** Opcode to update resource information in the list */ 202#define AMDGPU_BO_LIST_OP_UPDATE 2 203 204struct drm_amdgpu_bo_list_in { 205 /** Type of operation */ 206 __u32 operation; 207 /** Handle of list or 0 if we want to create one */ 208 __u32 list_handle; 209 /** Number of BOs in list */ 210 __u32 bo_number; 211 /** Size of each element describing BO */ 212 __u32 bo_info_size; 213 /** Pointer to array describing BOs */ 214 __u64 bo_info_ptr; 215}; 216 217struct drm_amdgpu_bo_list_entry { 218 /** Handle of BO */ 219 __u32 bo_handle; 220 /** New (if specified) BO priority to be used during migration */ 221 __u32 bo_priority; 222}; 223 224struct drm_amdgpu_bo_list_out { 225 /** Handle of resource list */ 226 __u32 list_handle; 227 __u32 _pad; 228}; 229 230union drm_amdgpu_bo_list { 231 struct drm_amdgpu_bo_list_in in; 232 struct drm_amdgpu_bo_list_out out; 233}; 234 235/* context related */ 236#define AMDGPU_CTX_OP_ALLOC_CTX 1 237#define AMDGPU_CTX_OP_FREE_CTX 2 238#define AMDGPU_CTX_OP_QUERY_STATE 3 239#define AMDGPU_CTX_OP_QUERY_STATE2 4 240#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 241#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 242 243/* GPU reset status */ 244#define AMDGPU_CTX_NO_RESET 0 245/* this the context caused it */ 246#define AMDGPU_CTX_GUILTY_RESET 1 247/* some other context caused it */ 248#define AMDGPU_CTX_INNOCENT_RESET 2 249/* unknown cause */ 250#define AMDGPU_CTX_UNKNOWN_RESET 3 251 252/* indicate gpu reset occurred after ctx created */ 253#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 254/* indicate vram lost occurred after ctx created */ 255#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 256/* indicate some job from this context once cause gpu hang */ 257#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 258/* indicate some errors are detected by RAS */ 259#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 260#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 261/* indicate that the reset hasn't completed yet */ 262#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 263 264/* Context priority level */ 265#define AMDGPU_CTX_PRIORITY_UNSET -2048 266#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 267#define AMDGPU_CTX_PRIORITY_LOW -512 268#define AMDGPU_CTX_PRIORITY_NORMAL 0 269/* 270 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 271 * CAP_SYS_NICE or DRM_MASTER 272*/ 273#define AMDGPU_CTX_PRIORITY_HIGH 512 274#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 275 276/* select a stable profiling pstate for perfmon tools */ 277#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 278#define AMDGPU_CTX_STABLE_PSTATE_NONE 0 279#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 280#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 281#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 282#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 283 284struct drm_amdgpu_ctx_in { 285 /** AMDGPU_CTX_OP_* */ 286 __u32 op; 287 /** Flags */ 288 __u32 flags; 289 __u32 ctx_id; 290 /** AMDGPU_CTX_PRIORITY_* */ 291 __s32 priority; 292}; 293 294union drm_amdgpu_ctx_out { 295 struct { 296 __u32 ctx_id; 297 __u32 _pad; 298 } alloc; 299 300 struct { 301 /** For future use, no flags defined so far */ 302 __u64 flags; 303 /** Number of resets caused by this context so far. */ 304 __u32 hangs; 305 /** Reset status since the last call of the ioctl. */ 306 __u32 reset_status; 307 } state; 308 309 struct { 310 __u32 flags; 311 __u32 _pad; 312 } pstate; 313}; 314 315union drm_amdgpu_ctx { 316 struct drm_amdgpu_ctx_in in; 317 union drm_amdgpu_ctx_out out; 318}; 319 320/* vm ioctl */ 321#define AMDGPU_VM_OP_RESERVE_VMID 1 322#define AMDGPU_VM_OP_UNRESERVE_VMID 2 323 324struct drm_amdgpu_vm_in { 325 /** AMDGPU_VM_OP_* */ 326 __u32 op; 327 __u32 flags; 328}; 329 330struct drm_amdgpu_vm_out { 331 /** For future use, no flags defined so far */ 332 __u64 flags; 333}; 334 335union drm_amdgpu_vm { 336 struct drm_amdgpu_vm_in in; 337 struct drm_amdgpu_vm_out out; 338}; 339 340/* sched ioctl */ 341#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 342#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 343 344struct drm_amdgpu_sched_in { 345 /* AMDGPU_SCHED_OP_* */ 346 __u32 op; 347 __u32 fd; 348 /** AMDGPU_CTX_PRIORITY_* */ 349 __s32 priority; 350 __u32 ctx_id; 351}; 352 353union drm_amdgpu_sched { 354 struct drm_amdgpu_sched_in in; 355}; 356 357/* 358 * This is not a reliable API and you should expect it to fail for any 359 * number of reasons and have fallback path that do not use userptr to 360 * perform any operation. 361 */ 362#define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 363#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 364#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 365#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 366 367struct drm_amdgpu_gem_userptr { 368 __u64 addr; 369 __u64 size; 370 /* AMDGPU_GEM_USERPTR_* */ 371 __u32 flags; 372 /* Resulting GEM handle */ 373 __u32 handle; 374}; 375 376/* SI-CI-VI: */ 377/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 378#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 379#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 380#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 381#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 382#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 383#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 384#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 385#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 386#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 387#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 388#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 389#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 390#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 391#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 392#define AMDGPU_TILING_NUM_BANKS_SHIFT 21 393#define AMDGPU_TILING_NUM_BANKS_MASK 0x3 394 395/* GFX9 - GFX11: */ 396#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 397#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 398#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 399#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 400#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 401#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 402#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 403#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 404#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 405#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 406#define AMDGPU_TILING_SCANOUT_SHIFT 63 407#define AMDGPU_TILING_SCANOUT_MASK 0x1 408 409/* GFX12 and later: */ 410#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 411#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 412/* These are DCC recompression setting for memory management: */ 413#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 414#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ 415#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 416#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ 417#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 418#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 419 420/* Set/Get helpers for tiling flags. */ 421#define AMDGPU_TILING_SET(field, value) \ 422 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 423#define AMDGPU_TILING_GET(value, field) \ 424 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 425 426#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 427#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 428 429/** The same structure is shared for input/output */ 430struct drm_amdgpu_gem_metadata { 431 /** GEM Object handle */ 432 __u32 handle; 433 /** Do we want get or set metadata */ 434 __u32 op; 435 struct { 436 /** For future use, no flags defined so far */ 437 __u64 flags; 438 /** family specific tiling info */ 439 __u64 tiling_info; 440 __u32 data_size_bytes; 441 __u32 data[64]; 442 } data; 443}; 444 445struct drm_amdgpu_gem_mmap_in { 446 /** the GEM object handle */ 447 __u32 handle; 448 __u32 _pad; 449}; 450 451struct drm_amdgpu_gem_mmap_out { 452 /** mmap offset from the vma offset manager */ 453 __u64 addr_ptr; 454}; 455 456union drm_amdgpu_gem_mmap { 457 struct drm_amdgpu_gem_mmap_in in; 458 struct drm_amdgpu_gem_mmap_out out; 459}; 460 461struct drm_amdgpu_gem_wait_idle_in { 462 /** GEM object handle */ 463 __u32 handle; 464 /** For future use, no flags defined so far */ 465 __u32 flags; 466 /** Absolute timeout to wait */ 467 __u64 timeout; 468}; 469 470struct drm_amdgpu_gem_wait_idle_out { 471 /** BO status: 0 - BO is idle, 1 - BO is busy */ 472 __u32 status; 473 /** Returned current memory domain */ 474 __u32 domain; 475}; 476 477union drm_amdgpu_gem_wait_idle { 478 struct drm_amdgpu_gem_wait_idle_in in; 479 struct drm_amdgpu_gem_wait_idle_out out; 480}; 481 482struct drm_amdgpu_wait_cs_in { 483 /* Command submission handle 484 * handle equals 0 means none to wait for 485 * handle equals ~0ull means wait for the latest sequence number 486 */ 487 __u64 handle; 488 /** Absolute timeout to wait */ 489 __u64 timeout; 490 __u32 ip_type; 491 __u32 ip_instance; 492 __u32 ring; 493 __u32 ctx_id; 494}; 495 496struct drm_amdgpu_wait_cs_out { 497 /** CS status: 0 - CS completed, 1 - CS still busy */ 498 __u64 status; 499}; 500 501union drm_amdgpu_wait_cs { 502 struct drm_amdgpu_wait_cs_in in; 503 struct drm_amdgpu_wait_cs_out out; 504}; 505 506struct drm_amdgpu_fence { 507 __u32 ctx_id; 508 __u32 ip_type; 509 __u32 ip_instance; 510 __u32 ring; 511 __u64 seq_no; 512}; 513 514struct drm_amdgpu_wait_fences_in { 515 /** This points to uint64_t * which points to fences */ 516 __u64 fences; 517 __u32 fence_count; 518 __u32 wait_all; 519 __u64 timeout_ns; 520}; 521 522struct drm_amdgpu_wait_fences_out { 523 __u32 status; 524 __u32 first_signaled; 525}; 526 527union drm_amdgpu_wait_fences { 528 struct drm_amdgpu_wait_fences_in in; 529 struct drm_amdgpu_wait_fences_out out; 530}; 531 532#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 533#define AMDGPU_GEM_OP_SET_PLACEMENT 1 534 535/* Sets or returns a value associated with a buffer. */ 536struct drm_amdgpu_gem_op { 537 /** GEM object handle */ 538 __u32 handle; 539 /** AMDGPU_GEM_OP_* */ 540 __u32 op; 541 /** Input or return value */ 542 __u64 value; 543}; 544 545#define AMDGPU_VA_OP_MAP 1 546#define AMDGPU_VA_OP_UNMAP 2 547#define AMDGPU_VA_OP_CLEAR 3 548#define AMDGPU_VA_OP_REPLACE 4 549 550/* Delay the page table update till the next CS */ 551#define AMDGPU_VM_DELAY_UPDATE (1 << 0) 552 553/* Mapping flags */ 554/* readable mapping */ 555#define AMDGPU_VM_PAGE_READABLE (1 << 1) 556/* writable mapping */ 557#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 558/* executable mapping, new for VI */ 559#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 560/* partially resident texture */ 561#define AMDGPU_VM_PAGE_PRT (1 << 4) 562/* MTYPE flags use bit 5 to 8 */ 563#define AMDGPU_VM_MTYPE_MASK (0xf << 5) 564/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 565#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 566/* Use Non Coherent MTYPE instead of default MTYPE */ 567#define AMDGPU_VM_MTYPE_NC (1 << 5) 568/* Use Write Combine MTYPE instead of default MTYPE */ 569#define AMDGPU_VM_MTYPE_WC (2 << 5) 570/* Use Cache Coherent MTYPE instead of default MTYPE */ 571#define AMDGPU_VM_MTYPE_CC (3 << 5) 572/* Use UnCached MTYPE instead of default MTYPE */ 573#define AMDGPU_VM_MTYPE_UC (4 << 5) 574/* Use Read Write MTYPE instead of default MTYPE */ 575#define AMDGPU_VM_MTYPE_RW (5 << 5) 576/* don't allocate MALL */ 577#define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 578 579struct drm_amdgpu_gem_va { 580 /** GEM object handle */ 581 __u32 handle; 582 __u32 _pad; 583 /** AMDGPU_VA_OP_* */ 584 __u32 operation; 585 /** AMDGPU_VM_PAGE_* */ 586 __u32 flags; 587 /** va address to assign . Must be correctly aligned.*/ 588 __u64 va_address; 589 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 590 __u64 offset_in_bo; 591 /** Specify mapping size. Must be correctly aligned. */ 592 __u64 map_size; 593}; 594 595#define AMDGPU_HW_IP_GFX 0 596#define AMDGPU_HW_IP_COMPUTE 1 597#define AMDGPU_HW_IP_DMA 2 598#define AMDGPU_HW_IP_UVD 3 599#define AMDGPU_HW_IP_VCE 4 600#define AMDGPU_HW_IP_UVD_ENC 5 601#define AMDGPU_HW_IP_VCN_DEC 6 602/* 603 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 604 * both encoding and decoding jobs. 605 */ 606#define AMDGPU_HW_IP_VCN_ENC 7 607#define AMDGPU_HW_IP_VCN_JPEG 8 608#define AMDGPU_HW_IP_VPE 9 609#define AMDGPU_HW_IP_NUM 10 610 611#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 612 613#define AMDGPU_CHUNK_ID_IB 0x01 614#define AMDGPU_CHUNK_ID_FENCE 0x02 615#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 616#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 617#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 618#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 619#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 620#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 621#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 622#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 623 624struct drm_amdgpu_cs_chunk { 625 __u32 chunk_id; 626 __u32 length_dw; 627 __u64 chunk_data; 628}; 629 630struct drm_amdgpu_cs_in { 631 /** Rendering context id */ 632 __u32 ctx_id; 633 /** Handle of resource list associated with CS */ 634 __u32 bo_list_handle; 635 __u32 num_chunks; 636 __u32 flags; 637 /** this points to __u64 * which point to cs chunks */ 638 __u64 chunks; 639}; 640 641struct drm_amdgpu_cs_out { 642 __u64 handle; 643}; 644 645union drm_amdgpu_cs { 646 struct drm_amdgpu_cs_in in; 647 struct drm_amdgpu_cs_out out; 648}; 649 650/* Specify flags to be used for IB */ 651 652/* This IB should be submitted to CE */ 653#define AMDGPU_IB_FLAG_CE (1<<0) 654 655/* Preamble flag, which means the IB could be dropped if no context switch */ 656#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 657 658/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 659#define AMDGPU_IB_FLAG_PREEMPT (1<<2) 660 661/* The IB fence should do the L2 writeback but not invalidate any shader 662 * caches (L2/vL1/sL1/I$). */ 663#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 664 665/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 666 * This will reset wave ID counters for the IB. 667 */ 668#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 669 670/* Flag the IB as secure (TMZ) 671 */ 672#define AMDGPU_IB_FLAGS_SECURE (1 << 5) 673 674/* Tell KMD to flush and invalidate caches 675 */ 676#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 677 678struct drm_amdgpu_cs_chunk_ib { 679 __u32 _pad; 680 /** AMDGPU_IB_FLAG_* */ 681 __u32 flags; 682 /** Virtual address to begin IB execution */ 683 __u64 va_start; 684 /** Size of submission */ 685 __u32 ib_bytes; 686 /** HW IP to submit to */ 687 __u32 ip_type; 688 /** HW IP index of the same type to submit to */ 689 __u32 ip_instance; 690 /** Ring index to submit to */ 691 __u32 ring; 692}; 693 694struct drm_amdgpu_cs_chunk_dep { 695 __u32 ip_type; 696 __u32 ip_instance; 697 __u32 ring; 698 __u32 ctx_id; 699 __u64 handle; 700}; 701 702struct drm_amdgpu_cs_chunk_fence { 703 __u32 handle; 704 __u32 offset; 705}; 706 707struct drm_amdgpu_cs_chunk_sem { 708 __u32 handle; 709}; 710 711struct drm_amdgpu_cs_chunk_syncobj { 712 __u32 handle; 713 __u32 flags; 714 __u64 point; 715}; 716 717#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 718#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 719#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 720 721union drm_amdgpu_fence_to_handle { 722 struct { 723 struct drm_amdgpu_fence fence; 724 __u32 what; 725 __u32 pad; 726 } in; 727 struct { 728 __u32 handle; 729 } out; 730}; 731 732struct drm_amdgpu_cs_chunk_data { 733 union { 734 struct drm_amdgpu_cs_chunk_ib ib_data; 735 struct drm_amdgpu_cs_chunk_fence fence_data; 736 }; 737}; 738 739#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 740 741struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 742 __u64 shadow_va; 743 __u64 csa_va; 744 __u64 gds_va; 745 __u64 flags; 746}; 747 748/* 749 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 750 * 751 */ 752#define AMDGPU_IDS_FLAGS_FUSION 0x1 753#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 754#define AMDGPU_IDS_FLAGS_TMZ 0x4 755#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 756 757/* 758 * Query h/w info: Flag identifying VF/PF/PT mode 759 * 760 */ 761#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300 762#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8 763#define AMDGPU_IDS_FLAGS_MODE_PF 0x0 764#define AMDGPU_IDS_FLAGS_MODE_VF 0x1 765#define AMDGPU_IDS_FLAGS_MODE_PT 0x2 766 767/* indicate if acceleration can be working */ 768#define AMDGPU_INFO_ACCEL_WORKING 0x00 769/* get the crtc_id from the mode object id? */ 770#define AMDGPU_INFO_CRTC_FROM_ID 0x01 771/* query hw IP info */ 772#define AMDGPU_INFO_HW_IP_INFO 0x02 773/* query hw IP instance count for the specified type */ 774#define AMDGPU_INFO_HW_IP_COUNT 0x03 775/* timestamp for GL_ARB_timer_query */ 776#define AMDGPU_INFO_TIMESTAMP 0x05 777/* Query the firmware version */ 778#define AMDGPU_INFO_FW_VERSION 0x0e 779 /* Subquery id: Query VCE firmware version */ 780 #define AMDGPU_INFO_FW_VCE 0x1 781 /* Subquery id: Query UVD firmware version */ 782 #define AMDGPU_INFO_FW_UVD 0x2 783 /* Subquery id: Query GMC firmware version */ 784 #define AMDGPU_INFO_FW_GMC 0x03 785 /* Subquery id: Query GFX ME firmware version */ 786 #define AMDGPU_INFO_FW_GFX_ME 0x04 787 /* Subquery id: Query GFX PFP firmware version */ 788 #define AMDGPU_INFO_FW_GFX_PFP 0x05 789 /* Subquery id: Query GFX CE firmware version */ 790 #define AMDGPU_INFO_FW_GFX_CE 0x06 791 /* Subquery id: Query GFX RLC firmware version */ 792 #define AMDGPU_INFO_FW_GFX_RLC 0x07 793 /* Subquery id: Query GFX MEC firmware version */ 794 #define AMDGPU_INFO_FW_GFX_MEC 0x08 795 /* Subquery id: Query SMC firmware version */ 796 #define AMDGPU_INFO_FW_SMC 0x0a 797 /* Subquery id: Query SDMA firmware version */ 798 #define AMDGPU_INFO_FW_SDMA 0x0b 799 /* Subquery id: Query PSP SOS firmware version */ 800 #define AMDGPU_INFO_FW_SOS 0x0c 801 /* Subquery id: Query PSP ASD firmware version */ 802 #define AMDGPU_INFO_FW_ASD 0x0d 803 /* Subquery id: Query VCN firmware version */ 804 #define AMDGPU_INFO_FW_VCN 0x0e 805 /* Subquery id: Query GFX RLC SRLC firmware version */ 806 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 807 /* Subquery id: Query GFX RLC SRLG firmware version */ 808 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 809 /* Subquery id: Query GFX RLC SRLS firmware version */ 810 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 811 /* Subquery id: Query DMCU firmware version */ 812 #define AMDGPU_INFO_FW_DMCU 0x12 813 #define AMDGPU_INFO_FW_TA 0x13 814 /* Subquery id: Query DMCUB firmware version */ 815 #define AMDGPU_INFO_FW_DMCUB 0x14 816 /* Subquery id: Query TOC firmware version */ 817 #define AMDGPU_INFO_FW_TOC 0x15 818 /* Subquery id: Query CAP firmware version */ 819 #define AMDGPU_INFO_FW_CAP 0x16 820 /* Subquery id: Query GFX RLCP firmware version */ 821 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 822 /* Subquery id: Query GFX RLCV firmware version */ 823 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 824 /* Subquery id: Query MES_KIQ firmware version */ 825 #define AMDGPU_INFO_FW_MES_KIQ 0x19 826 /* Subquery id: Query MES firmware version */ 827 #define AMDGPU_INFO_FW_MES 0x1a 828 /* Subquery id: Query IMU firmware version */ 829 #define AMDGPU_INFO_FW_IMU 0x1b 830 /* Subquery id: Query VPE firmware version */ 831 #define AMDGPU_INFO_FW_VPE 0x1c 832 833/* number of bytes moved for TTM migration */ 834#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 835/* the used VRAM size */ 836#define AMDGPU_INFO_VRAM_USAGE 0x10 837/* the used GTT size */ 838#define AMDGPU_INFO_GTT_USAGE 0x11 839/* Information about GDS, etc. resource configuration */ 840#define AMDGPU_INFO_GDS_CONFIG 0x13 841/* Query information about VRAM and GTT domains */ 842#define AMDGPU_INFO_VRAM_GTT 0x14 843/* Query information about register in MMR address space*/ 844#define AMDGPU_INFO_READ_MMR_REG 0x15 845/* Query information about device: rev id, family, etc. */ 846#define AMDGPU_INFO_DEV_INFO 0x16 847/* visible vram usage */ 848#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 849/* number of TTM buffer evictions */ 850#define AMDGPU_INFO_NUM_EVICTIONS 0x18 851/* Query memory about VRAM and GTT domains */ 852#define AMDGPU_INFO_MEMORY 0x19 853/* Query vce clock table */ 854#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 855/* Query vbios related information */ 856#define AMDGPU_INFO_VBIOS 0x1B 857 /* Subquery id: Query vbios size */ 858 #define AMDGPU_INFO_VBIOS_SIZE 0x1 859 /* Subquery id: Query vbios image */ 860 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 861 /* Subquery id: Query vbios info */ 862 #define AMDGPU_INFO_VBIOS_INFO 0x3 863/* Query UVD handles */ 864#define AMDGPU_INFO_NUM_HANDLES 0x1C 865/* Query sensor related information */ 866#define AMDGPU_INFO_SENSOR 0x1D 867 /* Subquery id: Query GPU shader clock */ 868 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 869 /* Subquery id: Query GPU memory clock */ 870 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 871 /* Subquery id: Query GPU temperature */ 872 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 873 /* Subquery id: Query GPU load */ 874 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 875 /* Subquery id: Query average GPU power */ 876 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 877 /* Subquery id: Query northbridge voltage */ 878 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 879 /* Subquery id: Query graphics voltage */ 880 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 881 /* Subquery id: Query GPU stable pstate shader clock */ 882 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 883 /* Subquery id: Query GPU stable pstate memory clock */ 884 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 885 /* Subquery id: Query GPU peak pstate shader clock */ 886 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 887 /* Subquery id: Query GPU peak pstate memory clock */ 888 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 889 /* Subquery id: Query input GPU power */ 890 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 891/* Number of VRAM page faults on CPU access. */ 892#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 893#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 894/* query ras mask of enabled features*/ 895#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 896/* RAS MASK: UMC (VRAM) */ 897#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 898/* RAS MASK: SDMA */ 899#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 900/* RAS MASK: GFX */ 901#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 902/* RAS MASK: MMHUB */ 903#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 904/* RAS MASK: ATHUB */ 905#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 906/* RAS MASK: PCIE */ 907#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 908/* RAS MASK: HDP */ 909#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 910/* RAS MASK: XGMI */ 911#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 912/* RAS MASK: DF */ 913#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 914/* RAS MASK: SMN */ 915#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 916/* RAS MASK: SEM */ 917#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 918/* RAS MASK: MP0 */ 919#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 920/* RAS MASK: MP1 */ 921#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 922/* RAS MASK: FUSE */ 923#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 924/* query video encode/decode caps */ 925#define AMDGPU_INFO_VIDEO_CAPS 0x21 926 /* Subquery id: Decode */ 927 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 928 /* Subquery id: Encode */ 929 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 930/* Query the max number of IBs per gang per submission */ 931#define AMDGPU_INFO_MAX_IBS 0x22 932/* query last page fault info */ 933#define AMDGPU_INFO_GPUVM_FAULT 0x23 934 935#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 936#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 937#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 938#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 939 940struct drm_amdgpu_query_fw { 941 /** AMDGPU_INFO_FW_* */ 942 __u32 fw_type; 943 /** 944 * Index of the IP if there are more IPs of 945 * the same type. 946 */ 947 __u32 ip_instance; 948 /** 949 * Index of the engine. Whether this is used depends 950 * on the firmware type. (e.g. MEC, SDMA) 951 */ 952 __u32 index; 953 __u32 _pad; 954}; 955 956/* Input structure for the INFO ioctl */ 957struct drm_amdgpu_info { 958 /* Where the return value will be stored */ 959 __u64 return_pointer; 960 /* The size of the return value. Just like "size" in "snprintf", 961 * it limits how many bytes the kernel can write. */ 962 __u32 return_size; 963 /* The query request id. */ 964 __u32 query; 965 966 union { 967 struct { 968 __u32 id; 969 __u32 _pad; 970 } mode_crtc; 971 972 struct { 973 /** AMDGPU_HW_IP_* */ 974 __u32 type; 975 /** 976 * Index of the IP if there are more IPs of the same 977 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 978 */ 979 __u32 ip_instance; 980 } query_hw_ip; 981 982 struct { 983 __u32 dword_offset; 984 /** number of registers to read */ 985 __u32 count; 986 __u32 instance; 987 /** For future use, no flags defined so far */ 988 __u32 flags; 989 } read_mmr_reg; 990 991 struct drm_amdgpu_query_fw query_fw; 992 993 struct { 994 __u32 type; 995 __u32 offset; 996 } vbios_info; 997 998 struct { 999 __u32 type; 1000 } sensor_info; 1001 1002 struct { 1003 __u32 type; 1004 } video_cap; 1005 }; 1006}; 1007 1008struct drm_amdgpu_info_gds { 1009 /** GDS GFX partition size */ 1010 __u32 gds_gfx_partition_size; 1011 /** GDS compute partition size */ 1012 __u32 compute_partition_size; 1013 /** total GDS memory size */ 1014 __u32 gds_total_size; 1015 /** GWS size per GFX partition */ 1016 __u32 gws_per_gfx_partition; 1017 /** GSW size per compute partition */ 1018 __u32 gws_per_compute_partition; 1019 /** OA size per GFX partition */ 1020 __u32 oa_per_gfx_partition; 1021 /** OA size per compute partition */ 1022 __u32 oa_per_compute_partition; 1023 __u32 _pad; 1024}; 1025 1026struct drm_amdgpu_info_vram_gtt { 1027 __u64 vram_size; 1028 __u64 vram_cpu_accessible_size; 1029 __u64 gtt_size; 1030}; 1031 1032struct drm_amdgpu_heap_info { 1033 /** max. physical memory */ 1034 __u64 total_heap_size; 1035 1036 /** Theoretical max. available memory in the given heap */ 1037 __u64 usable_heap_size; 1038 1039 /** 1040 * Number of bytes allocated in the heap. This includes all processes 1041 * and private allocations in the kernel. It changes when new buffers 1042 * are allocated, freed, and moved. It cannot be larger than 1043 * heap_size. 1044 */ 1045 __u64 heap_usage; 1046 1047 /** 1048 * Theoretical possible max. size of buffer which 1049 * could be allocated in the given heap 1050 */ 1051 __u64 max_allocation; 1052}; 1053 1054struct drm_amdgpu_memory_info { 1055 struct drm_amdgpu_heap_info vram; 1056 struct drm_amdgpu_heap_info cpu_accessible_vram; 1057 struct drm_amdgpu_heap_info gtt; 1058}; 1059 1060struct drm_amdgpu_info_firmware { 1061 __u32 ver; 1062 __u32 feature; 1063}; 1064 1065struct drm_amdgpu_info_vbios { 1066 __u8 name[64]; 1067 __u8 vbios_pn[64]; 1068 __u32 version; 1069 __u32 pad; 1070 __u8 vbios_ver_str[32]; 1071 __u8 date[32]; 1072}; 1073 1074#define AMDGPU_VRAM_TYPE_UNKNOWN 0 1075#define AMDGPU_VRAM_TYPE_GDDR1 1 1076#define AMDGPU_VRAM_TYPE_DDR2 2 1077#define AMDGPU_VRAM_TYPE_GDDR3 3 1078#define AMDGPU_VRAM_TYPE_GDDR4 4 1079#define AMDGPU_VRAM_TYPE_GDDR5 5 1080#define AMDGPU_VRAM_TYPE_HBM 6 1081#define AMDGPU_VRAM_TYPE_DDR3 7 1082#define AMDGPU_VRAM_TYPE_DDR4 8 1083#define AMDGPU_VRAM_TYPE_GDDR6 9 1084#define AMDGPU_VRAM_TYPE_DDR5 10 1085#define AMDGPU_VRAM_TYPE_LPDDR4 11 1086#define AMDGPU_VRAM_TYPE_LPDDR5 12 1087 1088struct drm_amdgpu_info_device { 1089 /** PCI Device ID */ 1090 __u32 device_id; 1091 /** Internal chip revision: A0, A1, etc.) */ 1092 __u32 chip_rev; 1093 __u32 external_rev; 1094 /** Revision id in PCI Config space */ 1095 __u32 pci_rev; 1096 __u32 family; 1097 __u32 num_shader_engines; 1098 __u32 num_shader_arrays_per_engine; 1099 /* in KHz */ 1100 __u32 gpu_counter_freq; 1101 __u64 max_engine_clock; 1102 __u64 max_memory_clock; 1103 /* cu information */ 1104 __u32 cu_active_number; 1105 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1106 __u32 cu_ao_mask; 1107 __u32 cu_bitmap[4][4]; 1108 /** Render backend pipe mask. One render backend is CB+DB. */ 1109 __u32 enabled_rb_pipes_mask; 1110 __u32 num_rb_pipes; 1111 __u32 num_hw_gfx_contexts; 1112 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1113 __u32 pcie_gen; 1114 __u64 ids_flags; 1115 /** Starting virtual address for UMDs. */ 1116 __u64 virtual_address_offset; 1117 /** The maximum virtual address */ 1118 __u64 virtual_address_max; 1119 /** Required alignment of virtual addresses. */ 1120 __u32 virtual_address_alignment; 1121 /** Page table entry - fragment size */ 1122 __u32 pte_fragment_size; 1123 __u32 gart_page_size; 1124 /** constant engine ram size*/ 1125 __u32 ce_ram_size; 1126 /** video memory type info*/ 1127 __u32 vram_type; 1128 /** video memory bit width*/ 1129 __u32 vram_bit_width; 1130 /* vce harvesting instance */ 1131 __u32 vce_harvest_config; 1132 /* gfx double offchip LDS buffers */ 1133 __u32 gc_double_offchip_lds_buf; 1134 /* NGG Primitive Buffer */ 1135 __u64 prim_buf_gpu_addr; 1136 /* NGG Position Buffer */ 1137 __u64 pos_buf_gpu_addr; 1138 /* NGG Control Sideband */ 1139 __u64 cntl_sb_buf_gpu_addr; 1140 /* NGG Parameter Cache */ 1141 __u64 param_buf_gpu_addr; 1142 __u32 prim_buf_size; 1143 __u32 pos_buf_size; 1144 __u32 cntl_sb_buf_size; 1145 __u32 param_buf_size; 1146 /* wavefront size*/ 1147 __u32 wave_front_size; 1148 /* shader visible vgprs*/ 1149 __u32 num_shader_visible_vgprs; 1150 /* CU per shader array*/ 1151 __u32 num_cu_per_sh; 1152 /* number of tcc blocks*/ 1153 __u32 num_tcc_blocks; 1154 /* gs vgt table depth*/ 1155 __u32 gs_vgt_table_depth; 1156 /* gs primitive buffer depth*/ 1157 __u32 gs_prim_buffer_depth; 1158 /* max gs wavefront per vgt*/ 1159 __u32 max_gs_waves_per_vgt; 1160 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1161 __u32 pcie_num_lanes; 1162 /* always on cu bitmap */ 1163 __u32 cu_ao_bitmap[4][4]; 1164 /** Starting high virtual address for UMDs. */ 1165 __u64 high_va_offset; 1166 /** The maximum high virtual address */ 1167 __u64 high_va_max; 1168 /* gfx10 pa_sc_tile_steering_override */ 1169 __u32 pa_sc_tile_steering_override; 1170 /* disabled TCCs */ 1171 __u64 tcc_disabled_mask; 1172 __u64 min_engine_clock; 1173 __u64 min_memory_clock; 1174 /* The following fields are only set on gfx11+, older chips set 0. */ 1175 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1176 __u32 num_sqc_per_wgp; 1177 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1178 __u32 sqc_inst_cache_size; 1179 __u32 gl1c_cache_size; 1180 __u32 gl2c_cache_size; 1181 __u64 mall_size; /* AKA infinity cache */ 1182 /* high 32 bits of the rb pipes mask */ 1183 __u32 enabled_rb_pipes_mask_hi; 1184 /* shadow area size for gfx11 */ 1185 __u32 shadow_size; 1186 /* shadow area base virtual alignment for gfx11 */ 1187 __u32 shadow_alignment; 1188 /* context save area size for gfx11 */ 1189 __u32 csa_size; 1190 /* context save area base virtual alignment for gfx11 */ 1191 __u32 csa_alignment; 1192}; 1193 1194struct drm_amdgpu_info_hw_ip { 1195 /** Version of h/w IP */ 1196 __u32 hw_ip_version_major; 1197 __u32 hw_ip_version_minor; 1198 /** Capabilities */ 1199 __u64 capabilities_flags; 1200 /** command buffer address start alignment*/ 1201 __u32 ib_start_alignment; 1202 /** command buffer size alignment*/ 1203 __u32 ib_size_alignment; 1204 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1205 __u32 available_rings; 1206 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1207 __u32 ip_discovery_version; 1208}; 1209 1210struct drm_amdgpu_info_num_handles { 1211 /** Max handles as supported by firmware for UVD */ 1212 __u32 uvd_max_handles; 1213 /** Handles currently in use for UVD */ 1214 __u32 uvd_used_handles; 1215}; 1216 1217#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1218 1219struct drm_amdgpu_info_vce_clock_table_entry { 1220 /** System clock */ 1221 __u32 sclk; 1222 /** Memory clock */ 1223 __u32 mclk; 1224 /** VCE clock */ 1225 __u32 eclk; 1226 __u32 pad; 1227}; 1228 1229struct drm_amdgpu_info_vce_clock_table { 1230 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1231 __u32 num_valid_entries; 1232 __u32 pad; 1233}; 1234 1235/* query video encode/decode caps */ 1236#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1237#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1238#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1239#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1240#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1241#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1242#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1243#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1244#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1245 1246struct drm_amdgpu_info_video_codec_info { 1247 __u32 valid; 1248 __u32 max_width; 1249 __u32 max_height; 1250 __u32 max_pixels_per_frame; 1251 __u32 max_level; 1252 __u32 pad; 1253}; 1254 1255struct drm_amdgpu_info_video_caps { 1256 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1257}; 1258 1259#define AMDGPU_VMHUB_TYPE_MASK 0xff 1260#define AMDGPU_VMHUB_TYPE_SHIFT 0 1261#define AMDGPU_VMHUB_TYPE_GFX 0 1262#define AMDGPU_VMHUB_TYPE_MM0 1 1263#define AMDGPU_VMHUB_TYPE_MM1 2 1264#define AMDGPU_VMHUB_IDX_MASK 0xff00 1265#define AMDGPU_VMHUB_IDX_SHIFT 8 1266 1267struct drm_amdgpu_info_gpuvm_fault { 1268 __u64 addr; 1269 __u32 status; 1270 __u32 vmhub; 1271}; 1272 1273/* 1274 * Supported GPU families 1275 */ 1276#define AMDGPU_FAMILY_UNKNOWN 0 1277#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1278#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1279#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1280#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1281#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1282#define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1283#define AMDGPU_FAMILY_RV 142 /* Raven */ 1284#define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1285#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1286#define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1287#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1288#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1289#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1290#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1291#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ 1292#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ 1293 1294#if defined(__cplusplus) 1295} 1296#endif 1297 1298#endif 1299