drm.h revision 87bf8e7c
1/** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11/* 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 36#ifndef _DRM_H_ 37#define _DRM_H_ 38 39#if defined(__linux__) 40 41#include <linux/types.h> 42#include <asm/ioctl.h> 43typedef unsigned int drm_handle_t; 44 45#else /* One of the BSDs */ 46 47#include <stdint.h> 48#include <sys/ioccom.h> 49#include <sys/types.h> 50#ifndef __linux_sized_types__ 51#define __linux_sized_types__ 52typedef int8_t __s8; 53typedef uint8_t __u8; 54typedef int16_t __s16; 55typedef uint16_t __u16; 56typedef int32_t __s32; 57typedef uint32_t __u32; 58typedef int64_t __s64; 59typedef uint64_t __u64; 60#endif /* __linux_sized_types__ */ 61typedef size_t __kernel_size_t; 62typedef unsigned long drm_handle_t; 63 64#endif 65 66#if defined(__cplusplus) 67extern "C" { 68#endif 69 70#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 71#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 72#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 73#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 74 75#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 76#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 77#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 78#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 79#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 80 81typedef unsigned int drm_context_t; 82typedef unsigned int drm_drawable_t; 83typedef unsigned int drm_magic_t; 84 85/** 86 * Cliprect. 87 * 88 * \warning: If you change this structure, make sure you change 89 * XF86DRIClipRectRec in the server as well 90 * 91 * \note KW: Actually it's illegal to change either for 92 * backwards-compatibility reasons. 93 */ 94struct drm_clip_rect { 95 unsigned short x1; 96 unsigned short y1; 97 unsigned short x2; 98 unsigned short y2; 99}; 100 101/** 102 * Drawable information. 103 */ 104struct drm_drawable_info { 105 unsigned int num_rects; 106 struct drm_clip_rect *rects; 107}; 108 109/** 110 * Texture region, 111 */ 112struct drm_tex_region { 113 unsigned char next; 114 unsigned char prev; 115 unsigned char in_use; 116 unsigned char padding; 117 unsigned int age; 118}; 119 120/** 121 * Hardware lock. 122 * 123 * The lock structure is a simple cache-line aligned integer. To avoid 124 * processor bus contention on a multiprocessor system, there should not be any 125 * other data stored in the same cache line. 126 */ 127struct drm_hw_lock { 128 __volatile__ unsigned int lock; /**< lock variable */ 129 char padding[60]; /**< Pad to cache line */ 130}; 131 132/** 133 * DRM_IOCTL_VERSION ioctl argument type. 134 * 135 * \sa drmGetVersion(). 136 */ 137struct drm_version { 138 int version_major; /**< Major version */ 139 int version_minor; /**< Minor version */ 140 int version_patchlevel; /**< Patch level */ 141 __kernel_size_t name_len; /**< Length of name buffer */ 142 char *name; /**< Name of driver */ 143 __kernel_size_t date_len; /**< Length of date buffer */ 144 char *date; /**< User-space buffer to hold date */ 145 __kernel_size_t desc_len; /**< Length of desc buffer */ 146 char *desc; /**< User-space buffer to hold desc */ 147}; 148 149/** 150 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 151 * 152 * \sa drmGetBusid() and drmSetBusId(). 153 */ 154struct drm_unique { 155 __kernel_size_t unique_len; /**< Length of unique */ 156 char *unique; /**< Unique name for driver instantiation */ 157}; 158 159struct drm_list { 160 int count; /**< Length of user-space structures */ 161 struct drm_version *version; 162}; 163 164struct drm_block { 165 int unused; 166}; 167 168/** 169 * DRM_IOCTL_CONTROL ioctl argument type. 170 * 171 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 172 */ 173struct drm_control { 174 enum { 175 DRM_ADD_COMMAND, 176 DRM_RM_COMMAND, 177 DRM_INST_HANDLER, 178 DRM_UNINST_HANDLER 179 } func; 180 int irq; 181}; 182 183/** 184 * Type of memory to map. 185 */ 186enum drm_map_type { 187 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 188 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 189 _DRM_SHM = 2, /**< shared, cached */ 190 _DRM_AGP = 3, /**< AGP/GART */ 191 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 192 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ 193}; 194 195/** 196 * Memory mapping flags. 197 */ 198enum drm_map_flags { 199 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 200 _DRM_READ_ONLY = 0x02, 201 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 202 _DRM_KERNEL = 0x08, /**< kernel requires access */ 203 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 204 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 205 _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 206 _DRM_DRIVER = 0x80 /**< Managed by driver */ 207}; 208 209struct drm_ctx_priv_map { 210 unsigned int ctx_id; /**< Context requesting private mapping */ 211 void *handle; /**< Handle of map */ 212}; 213 214/** 215 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 216 * argument type. 217 * 218 * \sa drmAddMap(). 219 */ 220struct drm_map { 221 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 222 unsigned long size; /**< Requested physical size (bytes) */ 223 enum drm_map_type type; /**< Type of memory to map */ 224 enum drm_map_flags flags; /**< Flags */ 225 void *handle; /**< User-space: "Handle" to pass to mmap() */ 226 /**< Kernel-space: kernel-virtual address */ 227 int mtrr; /**< MTRR slot used */ 228 /* Private data */ 229}; 230 231/** 232 * DRM_IOCTL_GET_CLIENT ioctl argument type. 233 */ 234struct drm_client { 235 int idx; /**< Which client desired? */ 236 int auth; /**< Is client authenticated? */ 237 unsigned long pid; /**< Process ID */ 238 unsigned long uid; /**< User ID */ 239 unsigned long magic; /**< Magic */ 240 unsigned long iocs; /**< Ioctl count */ 241}; 242 243enum drm_stat_type { 244 _DRM_STAT_LOCK, 245 _DRM_STAT_OPENS, 246 _DRM_STAT_CLOSES, 247 _DRM_STAT_IOCTLS, 248 _DRM_STAT_LOCKS, 249 _DRM_STAT_UNLOCKS, 250 _DRM_STAT_VALUE, /**< Generic value */ 251 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 252 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 253 254 _DRM_STAT_IRQ, /**< IRQ */ 255 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 256 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 257 _DRM_STAT_DMA, /**< DMA */ 258 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 259 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 260 /* Add to the *END* of the list */ 261}; 262 263/** 264 * DRM_IOCTL_GET_STATS ioctl argument type. 265 */ 266struct drm_stats { 267 unsigned long count; 268 struct { 269 unsigned long value; 270 enum drm_stat_type type; 271 } data[15]; 272}; 273 274/** 275 * Hardware locking flags. 276 */ 277enum drm_lock_flags { 278 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 279 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 280 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 281 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 282 /* These *HALT* flags aren't supported yet 283 -- they will be used to support the 284 full-screen DGA-like mode. */ 285 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 286 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 287}; 288 289/** 290 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 291 * 292 * \sa drmGetLock() and drmUnlock(). 293 */ 294struct drm_lock { 295 int context; 296 enum drm_lock_flags flags; 297}; 298 299/** 300 * DMA flags 301 * 302 * \warning 303 * These values \e must match xf86drm.h. 304 * 305 * \sa drm_dma. 306 */ 307enum drm_dma_flags { 308 /* Flags for DMA buffer dispatch */ 309 _DRM_DMA_BLOCK = 0x01, /**< 310 * Block until buffer dispatched. 311 * 312 * \note The buffer may not yet have 313 * been processed by the hardware -- 314 * getting a hardware lock with the 315 * hardware quiescent will ensure 316 * that the buffer has been 317 * processed. 318 */ 319 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 320 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 321 322 /* Flags for DMA buffer request */ 323 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 324 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 325 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 326}; 327 328/** 329 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 330 * 331 * \sa drmAddBufs(). 332 */ 333struct drm_buf_desc { 334 int count; /**< Number of buffers of this size */ 335 int size; /**< Size in bytes */ 336 int low_mark; /**< Low water mark */ 337 int high_mark; /**< High water mark */ 338 enum { 339 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 340 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 341 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 342 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 343 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 344 } flags; 345 unsigned long agp_start; /**< 346 * Start address of where the AGP buffers are 347 * in the AGP aperture 348 */ 349}; 350 351/** 352 * DRM_IOCTL_INFO_BUFS ioctl argument type. 353 */ 354struct drm_buf_info { 355 int count; /**< Entries in list */ 356 struct drm_buf_desc *list; 357}; 358 359/** 360 * DRM_IOCTL_FREE_BUFS ioctl argument type. 361 */ 362struct drm_buf_free { 363 int count; 364 int *list; 365}; 366 367/** 368 * Buffer information 369 * 370 * \sa drm_buf_map. 371 */ 372struct drm_buf_pub { 373 int idx; /**< Index into the master buffer list */ 374 int total; /**< Buffer size */ 375 int used; /**< Amount of buffer in use (for DMA) */ 376 void *address; /**< Address of buffer */ 377}; 378 379/** 380 * DRM_IOCTL_MAP_BUFS ioctl argument type. 381 */ 382struct drm_buf_map { 383 int count; /**< Length of the buffer list */ 384#ifdef __cplusplus 385 void *virt; 386#else 387 void *virtual; /**< Mmap'd area in user-virtual */ 388#endif 389 struct drm_buf_pub *list; /**< Buffer information */ 390}; 391 392/** 393 * DRM_IOCTL_DMA ioctl argument type. 394 * 395 * Indices here refer to the offset into the buffer list in drm_buf_get. 396 * 397 * \sa drmDMA(). 398 */ 399struct drm_dma { 400 int context; /**< Context handle */ 401 int send_count; /**< Number of buffers to send */ 402 int *send_indices; /**< List of handles to buffers */ 403 int *send_sizes; /**< Lengths of data to send */ 404 enum drm_dma_flags flags; /**< Flags */ 405 int request_count; /**< Number of buffers requested */ 406 int request_size; /**< Desired size for buffers */ 407 int *request_indices; /**< Buffer information */ 408 int *request_sizes; 409 int granted_count; /**< Number of buffers granted */ 410}; 411 412enum drm_ctx_flags { 413 _DRM_CONTEXT_PRESERVED = 0x01, 414 _DRM_CONTEXT_2DONLY = 0x02 415}; 416 417/** 418 * DRM_IOCTL_ADD_CTX ioctl argument type. 419 * 420 * \sa drmCreateContext() and drmDestroyContext(). 421 */ 422struct drm_ctx { 423 drm_context_t handle; 424 enum drm_ctx_flags flags; 425}; 426 427/** 428 * DRM_IOCTL_RES_CTX ioctl argument type. 429 */ 430struct drm_ctx_res { 431 int count; 432 struct drm_ctx *contexts; 433}; 434 435/** 436 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 437 */ 438struct drm_draw { 439 drm_drawable_t handle; 440}; 441 442/** 443 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 444 */ 445typedef enum { 446 DRM_DRAWABLE_CLIPRECTS 447} drm_drawable_info_type_t; 448 449struct drm_update_draw { 450 drm_drawable_t handle; 451 unsigned int type; 452 unsigned int num; 453 unsigned long long data; 454}; 455 456/** 457 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 458 */ 459struct drm_auth { 460 drm_magic_t magic; 461}; 462 463/** 464 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 465 * 466 * \sa drmGetInterruptFromBusID(). 467 */ 468struct drm_irq_busid { 469 int irq; /**< IRQ number */ 470 int busnum; /**< bus number */ 471 int devnum; /**< device number */ 472 int funcnum; /**< function number */ 473}; 474 475enum drm_vblank_seq_type { 476 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 477 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 478 /* bits 1-6 are reserved for high crtcs */ 479 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 480 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 481 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 482 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 483 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 484 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 485}; 486#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 487 488#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 489#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 490 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) 491 492struct drm_wait_vblank_request { 493 enum drm_vblank_seq_type type; 494 unsigned int sequence; 495 unsigned long signal; 496}; 497 498struct drm_wait_vblank_reply { 499 enum drm_vblank_seq_type type; 500 unsigned int sequence; 501 long tval_sec; 502 long tval_usec; 503}; 504 505/** 506 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 507 * 508 * \sa drmWaitVBlank(). 509 */ 510union drm_wait_vblank { 511 struct drm_wait_vblank_request request; 512 struct drm_wait_vblank_reply reply; 513}; 514 515#define _DRM_PRE_MODESET 1 516#define _DRM_POST_MODESET 2 517 518/** 519 * DRM_IOCTL_MODESET_CTL ioctl argument type 520 * 521 * \sa drmModesetCtl(). 522 */ 523struct drm_modeset_ctl { 524 __u32 crtc; 525 __u32 cmd; 526}; 527 528/** 529 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 530 * 531 * \sa drmAgpEnable(). 532 */ 533struct drm_agp_mode { 534 unsigned long mode; /**< AGP mode */ 535}; 536 537/** 538 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 539 * 540 * \sa drmAgpAlloc() and drmAgpFree(). 541 */ 542struct drm_agp_buffer { 543 unsigned long size; /**< In bytes -- will round to page boundary */ 544 unsigned long handle; /**< Used for binding / unbinding */ 545 unsigned long type; /**< Type of memory to allocate */ 546 unsigned long physical; /**< Physical used by i810 */ 547}; 548 549/** 550 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 551 * 552 * \sa drmAgpBind() and drmAgpUnbind(). 553 */ 554struct drm_agp_binding { 555 unsigned long handle; /**< From drm_agp_buffer */ 556 unsigned long offset; /**< In bytes -- will round to page boundary */ 557}; 558 559/** 560 * DRM_IOCTL_AGP_INFO ioctl argument type. 561 * 562 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 563 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 564 * drmAgpVendorId() and drmAgpDeviceId(). 565 */ 566struct drm_agp_info { 567 int agp_version_major; 568 int agp_version_minor; 569 unsigned long mode; 570 unsigned long aperture_base; /* physical address */ 571 unsigned long aperture_size; /* bytes */ 572 unsigned long memory_allowed; /* bytes */ 573 unsigned long memory_used; 574 575 /* PCI information */ 576 unsigned short id_vendor; 577 unsigned short id_device; 578}; 579 580/** 581 * DRM_IOCTL_SG_ALLOC ioctl argument type. 582 */ 583struct drm_scatter_gather { 584 unsigned long size; /**< In bytes -- will round to page boundary */ 585 unsigned long handle; /**< Used for mapping / unmapping */ 586}; 587 588/** 589 * DRM_IOCTL_SET_VERSION ioctl argument type. 590 */ 591struct drm_set_version { 592 int drm_di_major; 593 int drm_di_minor; 594 int drm_dd_major; 595 int drm_dd_minor; 596}; 597 598/** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 599struct drm_gem_close { 600 /** Handle of the object to be closed. */ 601 __u32 handle; 602 __u32 pad; 603}; 604 605/** DRM_IOCTL_GEM_FLINK ioctl argument type */ 606struct drm_gem_flink { 607 /** Handle for the object being named */ 608 __u32 handle; 609 610 /** Returned global name */ 611 __u32 name; 612}; 613 614/** DRM_IOCTL_GEM_OPEN ioctl argument type */ 615struct drm_gem_open { 616 /** Name of object being opened */ 617 __u32 name; 618 619 /** Returned handle for the object */ 620 __u32 handle; 621 622 /** Returned size of the object */ 623 __u64 size; 624}; 625 626#define DRM_CAP_DUMB_BUFFER 0x1 627#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 628#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 629#define DRM_CAP_DUMB_PREFER_SHADOW 0x4 630#define DRM_CAP_PRIME 0x5 631#define DRM_PRIME_CAP_IMPORT 0x1 632#define DRM_PRIME_CAP_EXPORT 0x2 633#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 634#define DRM_CAP_ASYNC_PAGE_FLIP 0x7 635/* 636 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight 637 * combination for the hardware cursor. The intention is that a hardware 638 * agnostic userspace can query a cursor plane size to use. 639 * 640 * Note that the cross-driver contract is to merely return a valid size; 641 * drivers are free to attach another meaning on top, eg. i915 returns the 642 * maximum plane size. 643 */ 644#define DRM_CAP_CURSOR_WIDTH 0x8 645#define DRM_CAP_CURSOR_HEIGHT 0x9 646#define DRM_CAP_ADDFB2_MODIFIERS 0x10 647#define DRM_CAP_PAGE_FLIP_TARGET 0x11 648#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 649#define DRM_CAP_SYNCOBJ 0x13 650#define DRM_CAP_SYNCOBJ_TIMELINE 0x14 651 652/** DRM_IOCTL_GET_CAP ioctl argument type */ 653struct drm_get_cap { 654 __u64 capability; 655 __u64 value; 656}; 657 658/** 659 * DRM_CLIENT_CAP_STEREO_3D 660 * 661 * if set to 1, the DRM core will expose the stereo 3D capabilities of the 662 * monitor by advertising the supported 3D layouts in the flags of struct 663 * drm_mode_modeinfo. 664 */ 665#define DRM_CLIENT_CAP_STEREO_3D 1 666 667/** 668 * DRM_CLIENT_CAP_UNIVERSAL_PLANES 669 * 670 * If set to 1, the DRM core will expose all planes (overlay, primary, and 671 * cursor) to userspace. 672 */ 673#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 674 675/** 676 * DRM_CLIENT_CAP_ATOMIC 677 * 678 * If set to 1, the DRM core will expose atomic properties to userspace 679 */ 680#define DRM_CLIENT_CAP_ATOMIC 3 681 682/** 683 * DRM_CLIENT_CAP_ASPECT_RATIO 684 * 685 * If set to 1, the DRM core will provide aspect ratio information in modes. 686 */ 687#define DRM_CLIENT_CAP_ASPECT_RATIO 4 688 689/** 690 * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 691 * 692 * If set to 1, the DRM core will expose special connectors to be used for 693 * writing back to memory the scene setup in the commit. Depends on client 694 * also supporting DRM_CLIENT_CAP_ATOMIC 695 */ 696#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 697 698/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ 699struct drm_set_client_cap { 700 __u64 capability; 701 __u64 value; 702}; 703 704#define DRM_RDWR O_RDWR 705#define DRM_CLOEXEC O_CLOEXEC 706struct drm_prime_handle { 707 __u32 handle; 708 709 /** Flags.. only applicable for handle->fd */ 710 __u32 flags; 711 712 /** Returned dmabuf file descriptor */ 713 __s32 fd; 714}; 715 716struct drm_syncobj_create { 717 __u32 handle; 718#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) 719 __u32 flags; 720}; 721 722struct drm_syncobj_destroy { 723 __u32 handle; 724 __u32 pad; 725}; 726 727#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) 728#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) 729struct drm_syncobj_handle { 730 __u32 handle; 731 __u32 flags; 732 733 __s32 fd; 734 __u32 pad; 735}; 736 737struct drm_syncobj_transfer { 738 __u32 src_handle; 739 __u32 dst_handle; 740 __u64 src_point; 741 __u64 dst_point; 742 __u32 flags; 743 __u32 pad; 744}; 745 746#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) 747#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) 748#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */ 749struct drm_syncobj_wait { 750 __u64 handles; 751 /* absolute timeout */ 752 __s64 timeout_nsec; 753 __u32 count_handles; 754 __u32 flags; 755 __u32 first_signaled; /* only valid when not waiting all */ 756 __u32 pad; 757}; 758 759struct drm_syncobj_timeline_wait { 760 __u64 handles; 761 /* wait on specific timeline point for every handles*/ 762 __u64 points; 763 /* absolute timeout */ 764 __s64 timeout_nsec; 765 __u32 count_handles; 766 __u32 flags; 767 __u32 first_signaled; /* only valid when not waiting all */ 768 __u32 pad; 769}; 770 771 772struct drm_syncobj_array { 773 __u64 handles; 774 __u32 count_handles; 775 __u32 pad; 776}; 777 778#define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */ 779struct drm_syncobj_timeline_array { 780 __u64 handles; 781 __u64 points; 782 __u32 count_handles; 783 __u32 flags; 784}; 785 786 787/* Query current scanout sequence number */ 788struct drm_crtc_get_sequence { 789 __u32 crtc_id; /* requested crtc_id */ 790 __u32 active; /* return: crtc output is active */ 791 __u64 sequence; /* return: most recent vblank sequence */ 792 __s64 sequence_ns; /* return: most recent time of first pixel out */ 793}; 794 795/* Queue event to be delivered at specified sequence. Time stamp marks 796 * when the first pixel of the refresh cycle leaves the display engine 797 * for the display 798 */ 799#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ 800#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ 801 802struct drm_crtc_queue_sequence { 803 __u32 crtc_id; 804 __u32 flags; 805 __u64 sequence; /* on input, target sequence. on output, actual sequence */ 806 __u64 user_data; /* user data passed to event */ 807}; 808 809#if defined(__cplusplus) 810} 811#endif 812 813#include "drm_mode.h" 814 815#if defined(__cplusplus) 816extern "C" { 817#endif 818 819#define DRM_IOCTL_BASE 'd' 820#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 821#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 822#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 823#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 824 825#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 826#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 827#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 828#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 829#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 830#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 831#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 832#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 833#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 834#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 835#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 836#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 837#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) 838#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) 839 840#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 841#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 842#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 843#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 844#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 845#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 846#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 847#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 848#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 849#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 850#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 851 852#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 853 854#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 855#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 856 857#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 858#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 859 860#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 861#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 862#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 863#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 864#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 865#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 866#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 867#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 868#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 869#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 870#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 871#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 872#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 873 874#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) 875#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) 876 877#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 878#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 879#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 880#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 881#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 882#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 883#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 884#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 885 886#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 887#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 888 889#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 890 891#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) 892#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) 893 894#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 895 896#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 897#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 898#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 899#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 900#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 901#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 902#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 903#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 904#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 905#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 906 907#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 908#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 909#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 910#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 911#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 912#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 913#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) 914#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) 915 916#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) 917#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 918#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) 919#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) 920#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) 921#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) 922#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) 923#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) 924#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 925#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) 926#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) 927#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) 928#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) 929 930#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) 931#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) 932#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) 933#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) 934#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) 935#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) 936#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) 937 938#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) 939#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) 940#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) 941#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) 942 943#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait) 944#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array) 945#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer) 946#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array) 947 948#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2) 949 950/** 951 * Device specific ioctls should only be in their respective headers 952 * The device specific ioctl range is from 0x40 to 0x9f. 953 * Generic IOCTLS restart at 0xA0. 954 * 955 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 956 * drmCommandReadWrite(). 957 */ 958#define DRM_COMMAND_BASE 0x40 959#define DRM_COMMAND_END 0xA0 960 961/** 962 * Header for events written back to userspace on the drm fd. The 963 * type defines the type of event, the length specifies the total 964 * length of the event (including the header), and user_data is 965 * typically a 64 bit value passed with the ioctl that triggered the 966 * event. A read on the drm fd will always only return complete 967 * events, that is, if for example the read buffer is 100 bytes, and 968 * there are two 64 byte events pending, only one will be returned. 969 * 970 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and 971 * up are chipset specific. 972 */ 973struct drm_event { 974 __u32 type; 975 __u32 length; 976}; 977 978#define DRM_EVENT_VBLANK 0x01 979#define DRM_EVENT_FLIP_COMPLETE 0x02 980#define DRM_EVENT_CRTC_SEQUENCE 0x03 981 982struct drm_event_vblank { 983 struct drm_event base; 984 __u64 user_data; 985 __u32 tv_sec; 986 __u32 tv_usec; 987 __u32 sequence; 988 __u32 crtc_id; /* 0 on older kernels that do not support this */ 989}; 990 991/* Event delivered at sequence. Time stamp marks when the first pixel 992 * of the refresh cycle leaves the display engine for the display 993 */ 994struct drm_event_crtc_sequence { 995 struct drm_event base; 996 __u64 user_data; 997 __s64 time_ns; 998 __u64 sequence; 999}; 1000 1001/* typedef area */ 1002typedef struct drm_clip_rect drm_clip_rect_t; 1003typedef struct drm_drawable_info drm_drawable_info_t; 1004typedef struct drm_tex_region drm_tex_region_t; 1005typedef struct drm_hw_lock drm_hw_lock_t; 1006typedef struct drm_version drm_version_t; 1007typedef struct drm_unique drm_unique_t; 1008typedef struct drm_list drm_list_t; 1009typedef struct drm_block drm_block_t; 1010typedef struct drm_control drm_control_t; 1011typedef enum drm_map_type drm_map_type_t; 1012typedef enum drm_map_flags drm_map_flags_t; 1013typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 1014typedef struct drm_map drm_map_t; 1015typedef struct drm_client drm_client_t; 1016typedef enum drm_stat_type drm_stat_type_t; 1017typedef struct drm_stats drm_stats_t; 1018typedef enum drm_lock_flags drm_lock_flags_t; 1019typedef struct drm_lock drm_lock_t; 1020typedef enum drm_dma_flags drm_dma_flags_t; 1021typedef struct drm_buf_desc drm_buf_desc_t; 1022typedef struct drm_buf_info drm_buf_info_t; 1023typedef struct drm_buf_free drm_buf_free_t; 1024typedef struct drm_buf_pub drm_buf_pub_t; 1025typedef struct drm_buf_map drm_buf_map_t; 1026typedef struct drm_dma drm_dma_t; 1027typedef union drm_wait_vblank drm_wait_vblank_t; 1028typedef struct drm_agp_mode drm_agp_mode_t; 1029typedef enum drm_ctx_flags drm_ctx_flags_t; 1030typedef struct drm_ctx drm_ctx_t; 1031typedef struct drm_ctx_res drm_ctx_res_t; 1032typedef struct drm_draw drm_draw_t; 1033typedef struct drm_update_draw drm_update_draw_t; 1034typedef struct drm_auth drm_auth_t; 1035typedef struct drm_irq_busid drm_irq_busid_t; 1036typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 1037 1038typedef struct drm_agp_buffer drm_agp_buffer_t; 1039typedef struct drm_agp_binding drm_agp_binding_t; 1040typedef struct drm_agp_info drm_agp_info_t; 1041typedef struct drm_scatter_gather drm_scatter_gather_t; 1042typedef struct drm_set_version drm_set_version_t; 1043 1044#if defined(__cplusplus) 1045} 1046#endif 1047 1048#endif 1049