drm_fourcc.h revision 41687f09
1/* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef DRM_FOURCC_H 25#define DRM_FOURCC_H 26 27#include "drm.h" 28 29#if defined(__cplusplus) 30extern "C" { 31#endif 32 33/** 34 * DOC: overview 35 * 36 * In the DRM subsystem, framebuffer pixel formats are described using the 37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 38 * fourcc code, a Format Modifier may optionally be provided, in order to 39 * further describe the buffer's format - for example tiling or compression. 40 * 41 * Format Modifiers 42 * ---------------- 43 * 44 * Format modifiers are used in conjunction with a fourcc code, forming a 45 * unique fourcc:modifier pair. This format:modifier pair must fully define the 46 * format and data layout of the buffer, and should be the only way to describe 47 * that particular buffer. 48 * 49 * Having multiple fourcc:modifier pairs which describe the same layout should 50 * be avoided, as such aliases run the risk of different drivers exposing 51 * different names for the same data format, forcing userspace to understand 52 * that they are aliases. 53 * 54 * Format modifiers may change any property of the buffer, including the number 55 * of planes and/or the required allocation size. Format modifiers are 56 * vendor-namespaced, and as such the relationship between a fourcc code and a 57 * modifier is specific to the modifer being used. For example, some modifiers 58 * may preserve meaning - such as number of planes - from the fourcc code, 59 * whereas others may not. 60 * 61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 62 * match only a single modifier. A modifier must not be a subset of layouts of 63 * another modifier. For instance, it's incorrect to encode pitch alignment in 64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 65 * aligned modifier. That said, modifiers can have implicit minimal 66 * requirements. 67 * 68 * For modifiers where the combination of fourcc code and modifier can alias, 69 * a canonical pair needs to be defined and used by all drivers. Preferred 70 * combinations are also encouraged where all combinations might lead to 71 * confusion and unnecessarily reduced interoperability. An example for the 72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 73 * 74 * There are two kinds of modifier users: 75 * 76 * - Kernel and user-space drivers: for drivers it's important that modifiers 77 * don't alias, otherwise two drivers might support the same format but use 78 * different aliases, preventing them from sharing buffers in an efficient 79 * format. 80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 81 * see modifiers as opaque tokens they can check for equality and intersect. 82 * These users musn't need to know to reason about the modifier value 83 * (i.e. they are not expected to extract information out of the modifier). 84 * 85 * Vendors should document their modifier usage in as much detail as 86 * possible, to ensure maximum compatibility across devices, drivers and 87 * applications. 88 * 89 * The authoritative list of format modifier codes is found in 90 * `include/uapi/drm/drm_fourcc.h` 91 */ 92 93#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ 94 ((__u32)(c) << 16) | ((__u32)(d) << 24)) 95 96#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 97 98/* Reserve 0 for the invalid format specifier */ 99#define DRM_FORMAT_INVALID 0 100 101/* color index */ 102#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 103 104/* 8 bpp Red */ 105#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 106 107/* 16 bpp Red */ 108#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 109 110/* 16 bpp RG */ 111#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 112#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 113 114/* 32 bpp RG */ 115#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 116#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 117 118/* 8 bpp RGB */ 119#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 120#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 121 122/* 16 bpp RGB */ 123#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 124#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 125#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 126#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 127 128#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 129#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 130#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 131#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 132 133#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 134#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 135#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 136#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 137 138#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 139#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 140#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 141#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 142 143#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 144#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 145 146/* 24 bpp RGB */ 147#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 148#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 149 150/* 32 bpp RGB */ 151#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 152#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 153#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 154#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 155 156#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 157#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 158#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 159#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 160 161#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 162#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 163#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 164#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 165 166#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 167#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 168#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 169#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 170 171/* 172 * Floating point 64bpp RGB 173 * IEEE 754-2008 binary16 half-precision float 174 * [15:0] sign:exponent:mantissa 1:5:10 175 */ 176#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 177#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 178 179#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 180#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 181 182/* 183 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 184 * of unused padding per component: 185 */ 186#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 187 188/* packed YCbCr */ 189#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 190#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 191#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 192#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 193 194#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 195#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 196#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 197#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 198 199/* 200 * packed Y2xx indicate for each component, xx valid data occupy msb 201 * 16-xx padding occupy lsb 202 */ 203#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 204#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 205#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 206 207/* 208 * packed Y4xx indicate for each component, xx valid data occupy msb 209 * 16-xx padding occupy lsb except Y410 210 */ 211#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 212#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 213#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 214 215#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 216#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 217#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 218 219/* 220 * packed YCbCr420 2x2 tiled formats 221 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 222 */ 223/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 224#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 225/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 226#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 227 228/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 229#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 230/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 231#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 232 233/* 234 * 1-plane YUV 4:2:0 235 * In these formats, the component ordering is specified (Y, followed by U 236 * then V), but the exact Linear layout is undefined. 237 * These formats can only be used with a non-Linear modifier. 238 */ 239#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 240#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 241 242/* 243 * 2 plane RGB + A 244 * index 0 = RGB plane, same format as the corresponding non _A8 format has 245 * index 1 = A plane, [7:0] A 246 */ 247#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 248#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 249#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 250#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 251#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 252#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 253#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 254#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 255 256/* 257 * 2 plane YCbCr 258 * index 0 = Y plane, [7:0] Y 259 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 260 * or 261 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 262 */ 263#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 264#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 265#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 266#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 267#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 268#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 269/* 270 * 2 plane YCbCr 271 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 272 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 273 */ 274#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 275 276/* 277 * 2 plane YCbCr MSB aligned 278 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 279 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 280 */ 281#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 282 283/* 284 * 2 plane YCbCr MSB aligned 285 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 286 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 287 */ 288#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 289 290/* 291 * 2 plane YCbCr MSB aligned 292 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 293 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 294 */ 295#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 296 297/* 298 * 2 plane YCbCr MSB aligned 299 * index 0 = Y plane, [15:0] Y little endian 300 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 301 */ 302#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 303 304/* 3 plane non-subsampled (444) YCbCr 305 * 16 bits per component, but only 10 bits are used and 6 bits are padded 306 * index 0: Y plane, [15:0] Y:x [10:6] little endian 307 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 308 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 309 */ 310#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 311 312/* 3 plane non-subsampled (444) YCrCb 313 * 16 bits per component, but only 10 bits are used and 6 bits are padded 314 * index 0: Y plane, [15:0] Y:x [10:6] little endian 315 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 316 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 317 */ 318#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 319 320/* 321 * 3 plane YCbCr 322 * index 0: Y plane, [7:0] Y 323 * index 1: Cb plane, [7:0] Cb 324 * index 2: Cr plane, [7:0] Cr 325 * or 326 * index 1: Cr plane, [7:0] Cr 327 * index 2: Cb plane, [7:0] Cb 328 */ 329#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 330#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 331#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 332#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 333#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 334#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 335#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 336#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 337#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 338#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 339 340 341/* 342 * Format Modifiers: 343 * 344 * Format modifiers describe, typically, a re-ordering or modification 345 * of the data in a plane of an FB. This can be used to express tiled/ 346 * swizzled formats, or compression, or a combination of the two. 347 * 348 * The upper 8 bits of the format modifier are a vendor-id as assigned 349 * below. The lower 56 bits are assigned as vendor sees fit. 350 */ 351 352/* Vendor Ids: */ 353#define DRM_FORMAT_MOD_VENDOR_NONE 0 354#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 355#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 356#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 357#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 358#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 359#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 360#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 361#define DRM_FORMAT_MOD_VENDOR_ARM 0x08 362#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 363#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 364 365/* add more to the end as needed */ 366 367#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 368 369#define fourcc_mod_code(vendor, val) \ 370 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 371 372/* 373 * Format Modifier tokens: 374 * 375 * When adding a new token please document the layout with a code comment, 376 * similar to the fourcc codes above. drm_fourcc.h is considered the 377 * authoritative source for all of these. 378 * 379 * Generic modifier names: 380 * 381 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 382 * for layouts which are common across multiple vendors. To preserve 383 * compatibility, in cases where a vendor-specific definition already exists and 384 * a generic name for it is desired, the common name is a purely symbolic alias 385 * and must use the same numerical value as the original definition. 386 * 387 * Note that generic names should only be used for modifiers which describe 388 * generic layouts (such as pixel re-ordering), which may have 389 * independently-developed support across multiple vendors. 390 * 391 * In future cases where a generic layout is identified before merging with a 392 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 393 * 'NONE' could be considered. This should only be for obvious, exceptional 394 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 395 * apply to a single vendor. 396 * 397 * Generic names should not be used for cases where multiple hardware vendors 398 * have implementations of the same standardised compression scheme (such as 399 * AFBC). In those cases, all implementations should use the same format 400 * modifier(s), reflecting the vendor of the standard. 401 */ 402 403#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 404 405/* 406 * Invalid Modifier 407 * 408 * This modifier can be used as a sentinel to terminate the format modifiers 409 * list, or to initialize a variable with an invalid modifier. It might also be 410 * used to report an error back to userspace for certain APIs. 411 */ 412#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 413 414/* 415 * Linear Layout 416 * 417 * Just plain linear layout. Note that this is different from no specifying any 418 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 419 * which tells the driver to also take driver-internal information into account 420 * and so might actually result in a tiled framebuffer. 421 */ 422#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 423 424/* 425 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 426 * 427 * The "none" format modifier doesn't actually mean that the modifier is 428 * implicit, instead it means that the layout is linear. Whether modifiers are 429 * used is out-of-band information carried in an API-specific way (e.g. in a 430 * flag for drm_mode_fb_cmd2). 431 */ 432#define DRM_FORMAT_MOD_NONE 0 433 434/* Intel framebuffer modifiers */ 435 436/* 437 * Intel X-tiling layout 438 * 439 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 440 * in row-major layout. Within the tile bytes are laid out row-major, with 441 * a platform-dependent stride. On top of that the memory can apply 442 * platform-depending swizzling of some higher address bits into bit6. 443 * 444 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 445 * On earlier platforms the is highly platforms specific and not useful for 446 * cross-driver sharing. It exists since on a given platform it does uniquely 447 * identify the layout in a simple way for i915-specific userspace, which 448 * facilitated conversion of userspace to modifiers. Additionally the exact 449 * format on some really old platforms is not known. 450 */ 451#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 452 453/* 454 * Intel Y-tiling layout 455 * 456 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 457 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 458 * chunks column-major, with a platform-dependent height. On top of that the 459 * memory can apply platform-depending swizzling of some higher address bits 460 * into bit6. 461 * 462 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 463 * On earlier platforms the is highly platforms specific and not useful for 464 * cross-driver sharing. It exists since on a given platform it does uniquely 465 * identify the layout in a simple way for i915-specific userspace, which 466 * facilitated conversion of userspace to modifiers. Additionally the exact 467 * format on some really old platforms is not known. 468 */ 469#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 470 471/* 472 * Intel Yf-tiling layout 473 * 474 * This is a tiled layout using 4Kb tiles in row-major layout. 475 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 476 * are arranged in four groups (two wide, two high) with column-major layout. 477 * Each group therefore consists out of four 256 byte units, which are also laid 478 * out as 2x2 column-major. 479 * 256 byte units are made out of four 64 byte blocks of pixels, producing 480 * either a square block or a 2:1 unit. 481 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 482 * in pixel depends on the pixel depth. 483 */ 484#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 485 486/* 487 * Intel color control surface (CCS) for render compression 488 * 489 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 490 * The main surface will be plane index 0 and must be Y/Yf-tiled, 491 * the CCS will be plane index 1. 492 * 493 * Each CCS tile matches a 1024x512 pixel area of the main surface. 494 * To match certain aspects of the 3D hardware the CCS is 495 * considered to be made up of normal 128Bx32 Y tiles, Thus 496 * the CCS pitch must be specified in multiples of 128 bytes. 497 * 498 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 499 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 500 * But that fact is not relevant unless the memory is accessed 501 * directly. 502 */ 503#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 504#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 505 506/* 507 * Intel color control surfaces (CCS) for Gen-12 render compression. 508 * 509 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 510 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 511 * main surface. In other words, 4 bits in CCS map to a main surface cache 512 * line pair. The main surface pitch is required to be a multiple of four 513 * Y-tile widths. 514 */ 515#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 516 517/* 518 * Intel color control surfaces (CCS) for Gen-12 media compression 519 * 520 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 521 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 522 * main surface. In other words, 4 bits in CCS map to a main surface cache 523 * line pair. The main surface pitch is required to be a multiple of four 524 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 525 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 526 * planes 2 and 3 for the respective CCS. 527 */ 528#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 529 530/* 531 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 532 * 533 * Macroblocks are laid in a Z-shape, and each pixel data is following the 534 * standard NV12 style. 535 * As for NV12, an image is the result of two frame buffers: one for Y, 536 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 537 * Alignment requirements are (for each buffer): 538 * - multiple of 128 pixels for the width 539 * - multiple of 32 pixels for the height 540 * 541 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 542 */ 543#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 544 545/* 546 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 547 * 548 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 549 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 550 * they correspond to their 16x16 luma block. 551 */ 552#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 553 554/* 555 * Qualcomm Compressed Format 556 * 557 * Refers to a compressed variant of the base format that is compressed. 558 * Implementation may be platform and base-format specific. 559 * 560 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 561 * Pixel data pitch/stride is aligned with macrotile width. 562 * Pixel data height is aligned with macrotile height. 563 * Entire pixel data buffer is aligned with 4k(bytes). 564 */ 565#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 566 567/* Vivante framebuffer modifiers */ 568 569/* 570 * Vivante 4x4 tiling layout 571 * 572 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 573 * layout. 574 */ 575#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 576 577/* 578 * Vivante 64x64 super-tiling layout 579 * 580 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 581 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 582 * major layout. 583 * 584 * For more information: see 585 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 586 */ 587#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 588 589/* 590 * Vivante 4x4 tiling layout for dual-pipe 591 * 592 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 593 * different base address. Offsets from the base addresses are therefore halved 594 * compared to the non-split tiled layout. 595 */ 596#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 597 598/* 599 * Vivante 64x64 super-tiling layout for dual-pipe 600 * 601 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 602 * starts at a different base address. Offsets from the base addresses are 603 * therefore halved compared to the non-split super-tiled layout. 604 */ 605#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 606 607/* NVIDIA frame buffer modifiers */ 608 609/* 610 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 611 * 612 * Pixels are arranged in simple tiles of 16 x 16 bytes. 613 */ 614#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 615 616/* 617 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 618 * and Tegra GPUs starting with Tegra K1. 619 * 620 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 621 * based on the architecture generation. GOBs themselves are then arranged in 622 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 623 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 624 * a block depth or height of "4"). 625 * 626 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 627 * in full detail. 628 * 629 * Macro 630 * Bits Param Description 631 * ---- ----- ----------------------------------------------------------------- 632 * 633 * 3:0 h log2(height) of each block, in GOBs. Placed here for 634 * compatibility with the existing 635 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 636 * 637 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 638 * compatibility with the existing 639 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 640 * 641 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 642 * size). Must be zero. 643 * 644 * Note there is no log2(width) parameter. Some portions of the 645 * hardware support a block width of two gobs, but it is impractical 646 * to use due to lack of support elsewhere, and has no known 647 * benefits. 648 * 649 * 11:9 - Reserved (To support 2D-array textures with variable array stride 650 * in blocks, specified via log2(tile width in blocks)). Must be 651 * zero. 652 * 653 * 19:12 k Page Kind. This value directly maps to a field in the page 654 * tables of all GPUs >= NV50. It affects the exact layout of bits 655 * in memory and can be derived from the tuple 656 * 657 * (format, GPU model, compression type, samples per pixel) 658 * 659 * Where compression type is defined below. If GPU model were 660 * implied by the format modifier, format, or memory buffer, page 661 * kind would not need to be included in the modifier itself, but 662 * since the modifier should define the layout of the associated 663 * memory buffer independent from any device or other context, it 664 * must be included here. 665 * 666 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 667 * starting with Fermi GPUs. Additionally, the mapping between page 668 * kind and bit layout has changed at various points. 669 * 670 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 671 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 672 * 2 = Gob Height 8, Turing+ Page Kind mapping 673 * 3 = Reserved for future use. 674 * 675 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 676 * bit remapping step that occurs at an even lower level than the 677 * page kind and block linear swizzles. This causes the layout of 678 * surfaces mapped in those SOC's GPUs to be incompatible with the 679 * equivalent mapping on other GPUs in the same system. 680 * 681 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 682 * 1 = Desktop GPU and Tegra Xavier+ Layout 683 * 684 * 25:23 c Lossless Framebuffer Compression type. 685 * 686 * 0 = none 687 * 1 = ROP/3D, layout 1, exact compression format implied by Page 688 * Kind field 689 * 2 = ROP/3D, layout 2, exact compression format implied by Page 690 * Kind field 691 * 3 = CDE horizontal 692 * 4 = CDE vertical 693 * 5 = Reserved for future use 694 * 6 = Reserved for future use 695 * 7 = Reserved for future use 696 * 697 * 55:25 - Reserved for future use. Must be zero. 698 */ 699#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 700 fourcc_mod_code(NVIDIA, (0x10 | \ 701 ((h) & 0xf) | \ 702 (((k) & 0xff) << 12) | \ 703 (((g) & 0x3) << 20) | \ 704 (((s) & 0x1) << 22) | \ 705 (((c) & 0x7) << 23))) 706 707/* To grandfather in prior block linear format modifiers to the above layout, 708 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 709 * with block-linear layouts, is remapped within drivers to the value 0xfe, 710 * which corresponds to the "generic" kind used for simple single-sample 711 * uncompressed color formats on Fermi - Volta GPUs. 712 */ 713static __inline__ __u64 714drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 715{ 716 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 717 return modifier; 718 else 719 return modifier | (0xfe << 12); 720} 721 722/* 723 * 16Bx2 Block Linear layout, used by Tegra K1 and later 724 * 725 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 726 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 727 * 728 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 729 * 730 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 731 * Valid values are: 732 * 733 * 0 == ONE_GOB 734 * 1 == TWO_GOBS 735 * 2 == FOUR_GOBS 736 * 3 == EIGHT_GOBS 737 * 4 == SIXTEEN_GOBS 738 * 5 == THIRTYTWO_GOBS 739 * 740 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 741 * in full detail. 742 */ 743#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 744 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 745 746#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 747 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 748#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 749 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 750#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 751 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 752#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 753 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 754#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 755 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 756#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 757 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 758 759/* 760 * Some Broadcom modifiers take parameters, for example the number of 761 * vertical lines in the image. Reserve the lower 32 bits for modifier 762 * type, and the next 24 bits for parameters. Top 8 bits are the 763 * vendor code. 764 */ 765#define __fourcc_mod_broadcom_param_shift 8 766#define __fourcc_mod_broadcom_param_bits 48 767#define fourcc_mod_broadcom_code(val, params) \ 768 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val)) 769#define fourcc_mod_broadcom_param(m) \ 770 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 771 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 772#define fourcc_mod_broadcom_mod(m) \ 773 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 774 __fourcc_mod_broadcom_param_shift)) 775 776/* 777 * Broadcom VC4 "T" format 778 * 779 * This is the primary layout that the V3D GPU can texture from (it 780 * can't do linear). The T format has: 781 * 782 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 783 * pixels at 32 bit depth. 784 * 785 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 786 * 16x16 pixels). 787 * 788 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 789 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 790 * they're (TR, BR, BL, TL), where bottom left is start of memory. 791 * 792 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 793 * tiles) or right-to-left (odd rows of 4k tiles). 794 */ 795#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 796 797/* 798 * Broadcom SAND format 799 * 800 * This is the native format that the H.264 codec block uses. For VC4 801 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 802 * 803 * The image can be considered to be split into columns, and the 804 * columns are placed consecutively into memory. The width of those 805 * columns can be either 32, 64, 128, or 256 pixels, but in practice 806 * only 128 pixel columns are used. 807 * 808 * The pitch between the start of each column is set to optimally 809 * switch between SDRAM banks. This is passed as the number of lines 810 * of column width in the modifier (we can't use the stride value due 811 * to various core checks that look at it , so you should set the 812 * stride to width*cpp). 813 * 814 * Note that the column height for this format modifier is the same 815 * for all of the planes, assuming that each column contains both Y 816 * and UV. Some SAND-using hardware stores UV in a separate tiled 817 * image from Y to reduce the column height, which is not supported 818 * with these modifiers. 819 */ 820 821#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 822 fourcc_mod_broadcom_code(2, v) 823#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 824 fourcc_mod_broadcom_code(3, v) 825#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 826 fourcc_mod_broadcom_code(4, v) 827#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 828 fourcc_mod_broadcom_code(5, v) 829 830#define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 831 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 832#define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 833 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 834#define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 835 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 836#define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 837 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 838 839/* Broadcom UIF format 840 * 841 * This is the common format for the current Broadcom multimedia 842 * blocks, including V3D 3.x and newer, newer video codecs, and 843 * displays. 844 * 845 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 846 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 847 * stored in columns, with padding between the columns to ensure that 848 * moving from one column to the next doesn't hit the same SDRAM page 849 * bank. 850 * 851 * To calculate the padding, it is assumed that each hardware block 852 * and the software driving it knows the platform's SDRAM page size, 853 * number of banks, and XOR address, and that it's identical between 854 * all blocks using the format. This tiling modifier will use XOR as 855 * necessary to reduce the padding. If a hardware block can't do XOR, 856 * the assumption is that a no-XOR tiling modifier will be created. 857 */ 858#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 859 860/* 861 * Arm Framebuffer Compression (AFBC) modifiers 862 * 863 * AFBC is a proprietary lossless image compression protocol and format. 864 * It provides fine-grained random access and minimizes the amount of data 865 * transferred between IP blocks. 866 * 867 * AFBC has several features which may be supported and/or used, which are 868 * represented using bits in the modifier. Not all combinations are valid, 869 * and different devices or use-cases may support different combinations. 870 * 871 * Further information on the use of AFBC modifiers can be found in 872 * Documentation/gpu/afbc.rst 873 */ 874 875/* 876 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific 877 * modifiers) denote the category for modifiers. Currently we have only two 878 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen 879 * different categories. 880 */ 881#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 882 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 883 884#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 885#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 886 887#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 888 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 889 890/* 891 * AFBC superblock size 892 * 893 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 894 * size (in pixels) must be aligned to a multiple of the superblock size. 895 * Four lowest significant bits(LSBs) are reserved for block size. 896 * 897 * Where one superblock size is specified, it applies to all planes of the 898 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 899 * the first applies to the Luma plane and the second applies to the Chroma 900 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 901 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 902 */ 903#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 904#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 905#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 906#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 907#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 908 909/* 910 * AFBC lossless colorspace transform 911 * 912 * Indicates that the buffer makes use of the AFBC lossless colorspace 913 * transform. 914 */ 915#define AFBC_FORMAT_MOD_YTR (1ULL << 4) 916 917/* 918 * AFBC block-split 919 * 920 * Indicates that the payload of each superblock is split. The second 921 * half of the payload is positioned at a predefined offset from the start 922 * of the superblock payload. 923 */ 924#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 925 926/* 927 * AFBC sparse layout 928 * 929 * This flag indicates that the payload of each superblock must be stored at a 930 * predefined position relative to the other superblocks in the same AFBC 931 * buffer. This order is the same order used by the header buffer. In this mode 932 * each superblock is given the same amount of space as an uncompressed 933 * superblock of the particular format would require, rounding up to the next 934 * multiple of 128 bytes in size. 935 */ 936#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 937 938/* 939 * AFBC copy-block restrict 940 * 941 * Buffers with this flag must obey the copy-block restriction. The restriction 942 * is such that there are no copy-blocks referring across the border of 8x8 943 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 944 */ 945#define AFBC_FORMAT_MOD_CBR (1ULL << 7) 946 947/* 948 * AFBC tiled layout 949 * 950 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 951 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 952 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 953 * larger bpp formats. The order between the tiles is scan line. 954 * When the tiled layout is used, the buffer size (in pixels) must be aligned 955 * to the tile size. 956 */ 957#define AFBC_FORMAT_MOD_TILED (1ULL << 8) 958 959/* 960 * AFBC solid color blocks 961 * 962 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 963 * can be reduced if a whole superblock is a single color. 964 */ 965#define AFBC_FORMAT_MOD_SC (1ULL << 9) 966 967/* 968 * AFBC double-buffer 969 * 970 * Indicates that the buffer is allocated in a layout safe for front-buffer 971 * rendering. 972 */ 973#define AFBC_FORMAT_MOD_DB (1ULL << 10) 974 975/* 976 * AFBC buffer content hints 977 * 978 * Indicates that the buffer includes per-superblock content hints. 979 */ 980#define AFBC_FORMAT_MOD_BCH (1ULL << 11) 981 982/* AFBC uncompressed storage mode 983 * 984 * Indicates that the buffer is using AFBC uncompressed storage mode. 985 * In this mode all superblock payloads in the buffer use the uncompressed 986 * storage mode, which is usually only used for data which cannot be compressed. 987 * The buffer layout is the same as for AFBC buffers without USM set, this only 988 * affects the storage mode of the individual superblocks. Note that even a 989 * buffer without USM set may use uncompressed storage mode for some or all 990 * superblocks, USM just guarantees it for all. 991 */ 992#define AFBC_FORMAT_MOD_USM (1ULL << 12) 993 994/* 995 * Arm 16x16 Block U-Interleaved modifier 996 * 997 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 998 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 999 * in the block are reordered. 1000 */ 1001#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1002 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1003 1004/* 1005 * Allwinner tiled modifier 1006 * 1007 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1008 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1009 * planes. 1010 * 1011 * With this tiling, the luminance samples are disposed in tiles representing 1012 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1013 * The pixel order in each tile is linear and the tiles are disposed linearly, 1014 * both in row-major order. 1015 */ 1016#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1017 1018/* 1019 * Amlogic Video Framebuffer Compression modifiers 1020 * 1021 * Amlogic uses a proprietary lossless image compression protocol and format 1022 * for their hardware video codec accelerators, either video decoders or 1023 * video input encoders. 1024 * 1025 * It considerably reduces memory bandwidth while writing and reading 1026 * frames in memory. 1027 * 1028 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1029 * per component YCbCr 420, single plane : 1030 * - DRM_FORMAT_YUV420_8BIT 1031 * - DRM_FORMAT_YUV420_10BIT 1032 * 1033 * The first 8 bits of the mode defines the layout, then the following 8 bits 1034 * defines the options changing the layout. 1035 * 1036 * Not all combinations are valid, and different SoCs may support different 1037 * combinations of layout and options. 1038 */ 1039#define __fourcc_mod_amlogic_layout_mask 0xf 1040#define __fourcc_mod_amlogic_options_shift 8 1041#define __fourcc_mod_amlogic_options_mask 0xf 1042 1043#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1044 fourcc_mod_code(AMLOGIC, \ 1045 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1046 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1047 << __fourcc_mod_amlogic_options_shift)) 1048 1049/* Amlogic FBC Layouts */ 1050 1051/* 1052 * Amlogic FBC Basic Layout 1053 * 1054 * The basic layout is composed of: 1055 * - a body content organized in 64x32 superblocks with 4096 bytes per 1056 * superblock in default mode. 1057 * - a 32 bytes per 128x64 header block 1058 * 1059 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1060 */ 1061#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1062 1063/* 1064 * Amlogic FBC Scatter Memory layout 1065 * 1066 * Indicates the header contains IOMMU references to the compressed 1067 * frames content to optimize memory access and layout. 1068 * 1069 * In this mode, only the header memory address is needed, thus the 1070 * content memory organization is tied to the current producer 1071 * execution and cannot be saved/dumped neither transferrable between 1072 * Amlogic SoCs supporting this modifier. 1073 * 1074 * Due to the nature of the layout, these buffers are not expected to 1075 * be accessible by the user-space clients, but only accessible by the 1076 * hardware producers and consumers. 1077 * 1078 * The user-space clients should expect a failure while trying to mmap 1079 * the DMA-BUF handle returned by the producer. 1080 */ 1081#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1082 1083/* Amlogic FBC Layout Options Bit Mask */ 1084 1085/* 1086 * Amlogic FBC Memory Saving mode 1087 * 1088 * Indicates the storage is packed when pixel size is multiple of word 1089 * boudaries, i.e. 8bit should be stored in this mode to save allocation 1090 * memory. 1091 * 1092 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1093 * the basic layout and 3200 bytes per 64x32 superblock combined with 1094 * the scatter layout. 1095 */ 1096#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1097 1098/* 1099 * AMD modifiers 1100 * 1101 * Memory layout: 1102 * 1103 * without DCC: 1104 * - main surface 1105 * 1106 * with DCC & without DCC_RETILE: 1107 * - main surface in plane 0 1108 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1109 * 1110 * with DCC & DCC_RETILE: 1111 * - main surface in plane 0 1112 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1113 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1114 * 1115 * For multi-plane formats the above surfaces get merged into one plane for 1116 * each format plane, based on the required alignment only. 1117 * 1118 * Bits Parameter Notes 1119 * ----- ------------------------ --------------------------------------------- 1120 * 1121 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1122 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1123 * 13 DCC 1124 * 14 DCC_RETILE 1125 * 15 DCC_PIPE_ALIGN 1126 * 16 DCC_INDEPENDENT_64B 1127 * 17 DCC_INDEPENDENT_128B 1128 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1129 * 20 DCC_CONSTANT_ENCODE 1130 * 23:21 PIPE_XOR_BITS Only for some chips 1131 * 26:24 BANK_XOR_BITS Only for some chips 1132 * 29:27 PACKERS Only for some chips 1133 * 32:30 RB Only for some chips 1134 * 35:33 PIPE Only for some chips 1135 * 55:36 - Reserved for future use, must be zero 1136 */ 1137#define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1138 1139#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1140 1141/* Reserve 0 for GFX8 and older */ 1142#define AMD_FMT_MOD_TILE_VER_GFX9 1 1143#define AMD_FMT_MOD_TILE_VER_GFX10 2 1144#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1145 1146/* 1147 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1148 * version. 1149 */ 1150#define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1151 1152/* 1153 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1154 * GFX9 as canonical version. 1155 */ 1156#define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1157#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1158#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1159#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1160 1161#define AMD_FMT_MOD_DCC_BLOCK_64B 0 1162#define AMD_FMT_MOD_DCC_BLOCK_128B 1 1163#define AMD_FMT_MOD_DCC_BLOCK_256B 2 1164 1165#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1166#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1167#define AMD_FMT_MOD_TILE_SHIFT 8 1168#define AMD_FMT_MOD_TILE_MASK 0x1F 1169 1170/* Whether DCC compression is enabled. */ 1171#define AMD_FMT_MOD_DCC_SHIFT 13 1172#define AMD_FMT_MOD_DCC_MASK 0x1 1173 1174/* 1175 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1176 * one which is not-aligned. 1177 */ 1178#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1179#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1180 1181/* Only set if DCC_RETILE = false */ 1182#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1183#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1184 1185#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1186#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1187#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1188#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1189#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1190#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1191 1192/* 1193 * DCC supports embedding some clear colors directly in the DCC surface. 1194 * However, on older GPUs the rendering HW ignores the embedded clear color 1195 * and prefers the driver provided color. This necessitates doing a fastclear 1196 * eliminate operation before a process transfers control. 1197 * 1198 * If this bit is set that means the fastclear eliminate is not needed for these 1199 * embeddable colors. 1200 */ 1201#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1202#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1203 1204/* 1205 * The below fields are for accounting for per GPU differences. These are only 1206 * relevant for GFX9 and later and if the tile field is *_X/_T. 1207 * 1208 * PIPE_XOR_BITS = always needed 1209 * BANK_XOR_BITS = only for TILE_VER_GFX9 1210 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1211 * RB = only for TILE_VER_GFX9 & DCC 1212 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1213 */ 1214#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1215#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1216#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1217#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1218#define AMD_FMT_MOD_PACKERS_SHIFT 27 1219#define AMD_FMT_MOD_PACKERS_MASK 0x7 1220#define AMD_FMT_MOD_RB_SHIFT 30 1221#define AMD_FMT_MOD_RB_MASK 0x7 1222#define AMD_FMT_MOD_PIPE_SHIFT 33 1223#define AMD_FMT_MOD_PIPE_MASK 0x7 1224 1225#define AMD_FMT_MOD_SET(field, value) \ 1226 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) 1227#define AMD_FMT_MOD_GET(field, value) \ 1228 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1229#define AMD_FMT_MOD_CLEAR(field) \ 1230 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1231 1232#if defined(__cplusplus) 1233} 1234#endif 1235 1236#endif /* DRM_FOURCC_H */ 1237