122944501Smrg/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
222944501Smrg * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
322944501Smrg */
422944501Smrg/*
522944501Smrg * Copyright 2000 Gareth Hughes
622944501Smrg * Copyright 2002 Frank C. Earl
722944501Smrg * Copyright 2002-2003 Leif Delgass
822944501Smrg * All Rights Reserved.
922944501Smrg *
1022944501Smrg * Permission is hereby granted, free of charge, to any person obtaining a
1122944501Smrg * copy of this software and associated documentation files (the "Software"),
1222944501Smrg * to deal in the Software without restriction, including without limitation
1322944501Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1422944501Smrg * and/or sell copies of the Software, and to permit persons to whom the
1522944501Smrg * Software is furnished to do so, subject to the following conditions:
1622944501Smrg *
1722944501Smrg * The above copyright notice and this permission notice (including the next
1822944501Smrg * paragraph) shall be included in all copies or substantial portions of the
1922944501Smrg * Software.
2022944501Smrg *
2122944501Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2222944501Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2322944501Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
2422944501Smrg * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
2522944501Smrg * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
2622944501Smrg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
2722944501Smrg *
2822944501Smrg * Authors:
2922944501Smrg *    Gareth Hughes <gareth@valinux.com>
3022944501Smrg *    Frank C. Earl <fearl@airmail.net>
3122944501Smrg *    Leif Delgass <ldelgass@retinalburn.net>
3222944501Smrg */
3322944501Smrg
3422944501Smrg#ifndef __MACH64_DRM_H__
3522944501Smrg#define __MACH64_DRM_H__
3622944501Smrg
3722944501Smrg/* WARNING: If you change any of these defines, make sure to change the
3822944501Smrg * defines in the Xserver file (mach64_sarea.h)
3922944501Smrg */
4022944501Smrg#ifndef __MACH64_SAREA_DEFINES__
4122944501Smrg#define __MACH64_SAREA_DEFINES__
4222944501Smrg
4322944501Smrg/* What needs to be changed for the current vertex buffer?
4422944501Smrg * GH: We're going to be pedantic about this.  We want the card to do as
4522944501Smrg * little as possible, so let's avoid having it fetch a whole bunch of
4622944501Smrg * register values that don't change all that often, if at all.
4722944501Smrg */
4822944501Smrg#define MACH64_UPLOAD_DST_OFF_PITCH	0x0001
4922944501Smrg#define MACH64_UPLOAD_Z_OFF_PITCH	0x0002
5022944501Smrg#define MACH64_UPLOAD_Z_ALPHA_CNTL	0x0004
5122944501Smrg#define MACH64_UPLOAD_SCALE_3D_CNTL	0x0008
5222944501Smrg#define MACH64_UPLOAD_DP_FOG_CLR	0x0010
5322944501Smrg#define MACH64_UPLOAD_DP_WRITE_MASK	0x0020
5422944501Smrg#define MACH64_UPLOAD_DP_PIX_WIDTH	0x0040
5522944501Smrg#define MACH64_UPLOAD_SETUP_CNTL	0x0080
5622944501Smrg#define MACH64_UPLOAD_MISC		0x0100
5722944501Smrg#define MACH64_UPLOAD_TEXTURE		0x0200
5822944501Smrg#define MACH64_UPLOAD_TEX0IMAGE		0x0400
5922944501Smrg#define MACH64_UPLOAD_TEX1IMAGE		0x0800
6022944501Smrg#define MACH64_UPLOAD_CLIPRECTS		0x1000	/* handled client-side */
6122944501Smrg#define MACH64_UPLOAD_CONTEXT		0x00ff
6222944501Smrg#define MACH64_UPLOAD_ALL		0x1fff
6322944501Smrg
6422944501Smrg/* DMA buffer size
6522944501Smrg */
6622944501Smrg#define MACH64_BUFFER_SIZE		16384
6722944501Smrg
6822944501Smrg/* Max number of swaps allowed on the ring
6922944501Smrg * before the client must wait
7022944501Smrg */
7122944501Smrg#define MACH64_MAX_QUEUED_FRAMES        3U
7222944501Smrg
7322944501Smrg/* Byte offsets for host blit buffer data
7422944501Smrg */
7522944501Smrg#define MACH64_HOSTDATA_BLIT_OFFSET	104
7622944501Smrg
7722944501Smrg/* Keep these small for testing.
7822944501Smrg */
7922944501Smrg#define MACH64_NR_SAREA_CLIPRECTS	8
8022944501Smrg
8122944501Smrg#define MACH64_CARD_HEAP		0
8222944501Smrg#define MACH64_AGP_HEAP			1
8322944501Smrg#define MACH64_NR_TEX_HEAPS		2
8422944501Smrg#define MACH64_NR_TEX_REGIONS		64
8522944501Smrg#define MACH64_LOG_TEX_GRANULARITY	16
8622944501Smrg
8722944501Smrg#define MACH64_TEX_MAXLEVELS		1
8822944501Smrg
8922944501Smrg#define MACH64_NR_CONTEXT_REGS		15
9022944501Smrg#define MACH64_NR_TEXTURE_REGS		4
9122944501Smrg
9222944501Smrg#endif				/* __MACH64_SAREA_DEFINES__ */
9322944501Smrg
9422944501Smrgtypedef struct {
9522944501Smrg	unsigned int dst_off_pitch;
9622944501Smrg
9722944501Smrg	unsigned int z_off_pitch;
9822944501Smrg	unsigned int z_cntl;
9922944501Smrg	unsigned int alpha_tst_cntl;
10022944501Smrg
10122944501Smrg	unsigned int scale_3d_cntl;
10222944501Smrg
10322944501Smrg	unsigned int sc_left_right;
10422944501Smrg	unsigned int sc_top_bottom;
10522944501Smrg
10622944501Smrg	unsigned int dp_fog_clr;
10722944501Smrg	unsigned int dp_write_mask;
10822944501Smrg	unsigned int dp_pix_width;
10922944501Smrg	unsigned int dp_mix;
11022944501Smrg	unsigned int dp_src;
11122944501Smrg
11222944501Smrg	unsigned int clr_cmp_cntl;
11322944501Smrg	unsigned int gui_traj_cntl;
11422944501Smrg
11522944501Smrg	unsigned int setup_cntl;
11622944501Smrg
11722944501Smrg	unsigned int tex_size_pitch;
11822944501Smrg	unsigned int tex_cntl;
11922944501Smrg	unsigned int secondary_tex_off;
12022944501Smrg	unsigned int tex_offset;
12122944501Smrg} drm_mach64_context_regs_t;
12222944501Smrg
12322944501Smrgtypedef struct drm_mach64_sarea {
12422944501Smrg	/* The channel for communication of state information to the kernel
12522944501Smrg	 * on firing a vertex dma buffer.
12622944501Smrg	 */
12722944501Smrg	drm_mach64_context_regs_t context_state;
12822944501Smrg	unsigned int dirty;
12922944501Smrg	unsigned int vertsize;
13022944501Smrg
13122944501Smrg	/* The current cliprects, or a subset thereof.
13222944501Smrg	 */
13322944501Smrg	struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS];
13422944501Smrg	unsigned int nbox;
13522944501Smrg
13622944501Smrg	/* Counters for client-side throttling of rendering clients.
13722944501Smrg	 */
13822944501Smrg	unsigned int frames_queued;
13922944501Smrg
14022944501Smrg	/* Texture memory LRU.
14122944501Smrg	 */
14222944501Smrg	struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
14322944501Smrg						       1];
14422944501Smrg	unsigned int tex_age[MACH64_NR_TEX_HEAPS];
14522944501Smrg	int ctx_owner;
14622944501Smrg} drm_mach64_sarea_t;
14722944501Smrg
14822944501Smrg/* WARNING: If you change any of these defines, make sure to change the
14922944501Smrg * defines in the Xserver file (mach64_common.h)
15022944501Smrg */
15122944501Smrg
15222944501Smrg/* Mach64 specific ioctls
15322944501Smrg * The device specific ioctl range is 0x40 to 0x79.
15422944501Smrg */
15522944501Smrg
15622944501Smrg#define DRM_MACH64_INIT           0x00
15722944501Smrg#define DRM_MACH64_IDLE           0x01
15822944501Smrg#define DRM_MACH64_RESET          0x02
15922944501Smrg#define DRM_MACH64_SWAP           0x03
16022944501Smrg#define DRM_MACH64_CLEAR          0x04
16122944501Smrg#define DRM_MACH64_VERTEX         0x05
16222944501Smrg#define DRM_MACH64_BLIT           0x06
16322944501Smrg#define DRM_MACH64_FLUSH          0x07
16422944501Smrg#define DRM_MACH64_GETPARAM       0x08
16522944501Smrg
16622944501Smrg#define DRM_IOCTL_MACH64_INIT           DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
16722944501Smrg#define DRM_IOCTL_MACH64_IDLE           DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_IDLE )
16822944501Smrg#define DRM_IOCTL_MACH64_RESET          DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_RESET )
16922944501Smrg#define DRM_IOCTL_MACH64_SWAP           DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_SWAP )
17022944501Smrg#define DRM_IOCTL_MACH64_CLEAR          DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
17122944501Smrg#define DRM_IOCTL_MACH64_VERTEX         DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
17222944501Smrg#define DRM_IOCTL_MACH64_BLIT           DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
17322944501Smrg#define DRM_IOCTL_MACH64_FLUSH          DRM_IO(  DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
17422944501Smrg#define DRM_IOCTL_MACH64_GETPARAM       DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
17522944501Smrg
17622944501Smrg/* Buffer flags for clears
17722944501Smrg */
17822944501Smrg#define MACH64_FRONT			0x1
17922944501Smrg#define MACH64_BACK			0x2
18022944501Smrg#define MACH64_DEPTH			0x4
18122944501Smrg
18222944501Smrg/* Primitive types for vertex buffers
18322944501Smrg */
18422944501Smrg#define MACH64_PRIM_POINTS		0x00000000
18522944501Smrg#define MACH64_PRIM_LINES		0x00000001
18622944501Smrg#define MACH64_PRIM_LINE_LOOP		0x00000002
18722944501Smrg#define MACH64_PRIM_LINE_STRIP		0x00000003
18822944501Smrg#define MACH64_PRIM_TRIANGLES		0x00000004
18922944501Smrg#define MACH64_PRIM_TRIANGLE_STRIP	0x00000005
19022944501Smrg#define MACH64_PRIM_TRIANGLE_FAN	0x00000006
19122944501Smrg#define MACH64_PRIM_QUADS		0x00000007
19222944501Smrg#define MACH64_PRIM_QUAD_STRIP		0x00000008
19322944501Smrg#define MACH64_PRIM_POLYGON		0x00000009
19422944501Smrg
19522944501Smrgtypedef enum _drm_mach64_dma_mode_t {
19622944501Smrg	MACH64_MODE_DMA_ASYNC,
19722944501Smrg	MACH64_MODE_DMA_SYNC,
19822944501Smrg	MACH64_MODE_MMIO
19922944501Smrg} drm_mach64_dma_mode_t;
20022944501Smrg
20122944501Smrgtypedef struct drm_mach64_init {
20222944501Smrg	enum {
20322944501Smrg		DRM_MACH64_INIT_DMA = 0x01,
20422944501Smrg		DRM_MACH64_CLEANUP_DMA = 0x02
20522944501Smrg	} func;
20622944501Smrg
20722944501Smrg	unsigned long sarea_priv_offset;
20822944501Smrg	int is_pci;
20922944501Smrg	drm_mach64_dma_mode_t dma_mode;
21022944501Smrg
21122944501Smrg	unsigned int fb_bpp;
21222944501Smrg	unsigned int front_offset, front_pitch;
21322944501Smrg	unsigned int back_offset, back_pitch;
21422944501Smrg
21522944501Smrg	unsigned int depth_bpp;
21622944501Smrg	unsigned int depth_offset, depth_pitch;
21722944501Smrg
21822944501Smrg	unsigned long fb_offset;
21922944501Smrg	unsigned long mmio_offset;
22022944501Smrg	unsigned long ring_offset;
22122944501Smrg	unsigned long buffers_offset;
22222944501Smrg	unsigned long agp_textures_offset;
22322944501Smrg} drm_mach64_init_t;
22422944501Smrg
22522944501Smrgtypedef struct drm_mach64_clear {
22622944501Smrg	unsigned int flags;
22722944501Smrg	int x, y, w, h;
22822944501Smrg	unsigned int clear_color;
22922944501Smrg	unsigned int clear_depth;
23022944501Smrg} drm_mach64_clear_t;
23122944501Smrg
23222944501Smrgtypedef struct drm_mach64_vertex {
23322944501Smrg	int prim;
23422944501Smrg	void *buf;		/* Address of vertex buffer */
23522944501Smrg	unsigned long used;	/* Number of bytes in buffer */
23622944501Smrg	int discard;		/* Client finished with buffer? */
23722944501Smrg} drm_mach64_vertex_t;
23822944501Smrg
23922944501Smrgtypedef struct drm_mach64_blit {
24022944501Smrg	void *buf;
24122944501Smrg	int pitch;
24222944501Smrg	int offset;
24322944501Smrg	int format;
24422944501Smrg	unsigned short x, y;
24522944501Smrg	unsigned short width, height;
24622944501Smrg} drm_mach64_blit_t;
24722944501Smrg
24822944501Smrgtypedef struct drm_mach64_getparam {
24922944501Smrg	enum {
25022944501Smrg		MACH64_PARAM_FRAMES_QUEUED = 0x01,
25122944501Smrg		MACH64_PARAM_IRQ_NR = 0x02
25222944501Smrg	} param;
25322944501Smrg	void *value;
25422944501Smrg} drm_mach64_getparam_t;
25522944501Smrg
25622944501Smrg#endif
257