nouveau_drm.h revision 3f012e29 
1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRM_H__
26#define __NOUVEAU_DRM_H__
27
28#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
29
30struct drm_nouveau_channel_alloc {
31	uint32_t     fb_ctxdma_handle;
32	uint32_t     tt_ctxdma_handle;
33
34	int          channel;
35	uint32_t     pushbuf_domains;
36
37	/* Notifier memory */
38	uint32_t     notifier_handle;
39
40	/* DRM-enforced subchannel assignments */
41	struct {
42		uint32_t handle;
43		uint32_t grclass;
44	} subchan[8];
45	uint32_t nr_subchan;
46};
47
48struct drm_nouveau_channel_free {
49	int channel;
50};
51
52struct drm_nouveau_grobj_alloc {
53	int      channel;
54	uint32_t handle;
55	int      class;
56};
57
58struct drm_nouveau_notifierobj_alloc {
59	uint32_t channel;
60	uint32_t handle;
61	uint32_t size;
62	uint32_t offset;
63};
64
65struct drm_nouveau_gpuobj_free {
66	int      channel;
67	uint32_t handle;
68};
69
70/* FIXME : maybe unify {GET,SET}PARAMs */
71#define NOUVEAU_GETPARAM_PCI_VENDOR      3
72#define NOUVEAU_GETPARAM_PCI_DEVICE      4
73#define NOUVEAU_GETPARAM_BUS_TYPE        5
74#define NOUVEAU_GETPARAM_FB_PHYSICAL     6
75#define NOUVEAU_GETPARAM_AGP_PHYSICAL    7
76#define NOUVEAU_GETPARAM_FB_SIZE         8
77#define NOUVEAU_GETPARAM_AGP_SIZE        9
78#define NOUVEAU_GETPARAM_PCI_PHYSICAL    10
79#define NOUVEAU_GETPARAM_CHIPSET_ID      11
80#define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
81#define NOUVEAU_GETPARAM_GRAPH_UNITS     13
82#define NOUVEAU_GETPARAM_PTIMER_TIME     14
83#define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
84#define NOUVEAU_GETPARAM_HAS_PAGEFLIP    16
85struct drm_nouveau_getparam {
86	uint64_t param;
87	uint64_t value;
88};
89
90struct drm_nouveau_setparam {
91	uint64_t param;
92	uint64_t value;
93};
94
95#define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
96#define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
97#define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
98#define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
99#define NOUVEAU_GEM_DOMAIN_COHERENT  (1 << 4)
100
101#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
102#define NOUVEAU_GEM_TILE_16BPP       0x00000001
103#define NOUVEAU_GEM_TILE_32BPP       0x00000002
104#define NOUVEAU_GEM_TILE_ZETA        0x00000004
105#define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
106
107struct drm_nouveau_gem_info {
108	uint32_t handle;
109	uint32_t domain;
110	uint64_t size;
111	uint64_t offset;
112	uint64_t map_handle;
113	uint32_t tile_mode;
114	uint32_t tile_flags;
115};
116
117struct drm_nouveau_gem_new {
118	struct drm_nouveau_gem_info info;
119	uint32_t channel_hint;
120	uint32_t align;
121};
122
123#define NOUVEAU_GEM_MAX_BUFFERS 1024
124struct drm_nouveau_gem_pushbuf_bo_presumed {
125	uint32_t valid;
126	uint32_t domain;
127	uint64_t offset;
128};
129
130struct drm_nouveau_gem_pushbuf_bo {
131	uint64_t user_priv;
132	uint32_t handle;
133	uint32_t read_domains;
134	uint32_t write_domains;
135	uint32_t valid_domains;
136	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
137};
138
139#define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
140#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
141#define NOUVEAU_GEM_RELOC_OR   (1 << 2)
142#define NOUVEAU_GEM_MAX_RELOCS 1024
143struct drm_nouveau_gem_pushbuf_reloc {
144	uint32_t reloc_bo_index;
145	uint32_t reloc_bo_offset;
146	uint32_t bo_index;
147	uint32_t flags;
148	uint32_t data;
149	uint32_t vor;
150	uint32_t tor;
151};
152
153#define NOUVEAU_GEM_MAX_PUSH 512
154struct drm_nouveau_gem_pushbuf_push {
155	uint32_t bo_index;
156	uint32_t pad;
157	uint64_t offset;
158	uint64_t length;
159};
160
161struct drm_nouveau_gem_pushbuf {
162	uint32_t channel;
163	uint32_t nr_buffers;
164	uint64_t buffers;
165	uint32_t nr_relocs;
166	uint32_t nr_push;
167	uint64_t relocs;
168	uint64_t push;
169	uint32_t suffix0;
170	uint32_t suffix1;
171	uint64_t vram_available;
172	uint64_t gart_available;
173};
174
175#define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
176#define NOUVEAU_GEM_CPU_PREP_NOBLOCK                                 0x00000002
177#define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
178struct drm_nouveau_gem_cpu_prep {
179	uint32_t handle;
180	uint32_t flags;
181};
182
183struct drm_nouveau_gem_cpu_fini {
184	uint32_t handle;
185};
186
187enum nouveau_bus_type {
188	NV_AGP     = 0,
189	NV_PCI     = 1,
190	NV_PCIE    = 2,
191};
192
193struct drm_nouveau_sarea {
194};
195
196#define DRM_NOUVEAU_GETPARAM           0x00
197#define DRM_NOUVEAU_SETPARAM           0x01
198#define DRM_NOUVEAU_CHANNEL_ALLOC      0x02
199#define DRM_NOUVEAU_CHANNEL_FREE       0x03
200#define DRM_NOUVEAU_GROBJ_ALLOC        0x04
201#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05
202#define DRM_NOUVEAU_GPUOBJ_FREE        0x06
203#define DRM_NOUVEAU_NVIF               0x07
204#define DRM_NOUVEAU_GEM_NEW            0x40
205#define DRM_NOUVEAU_GEM_PUSHBUF        0x41
206#define DRM_NOUVEAU_GEM_CPU_PREP       0x42
207#define DRM_NOUVEAU_GEM_CPU_FINI       0x43
208#define DRM_NOUVEAU_GEM_INFO           0x44
209
210#endif /* __NOUVEAU_DRM_H__ */
211