nouveau_drm.h revision 7cdc0497 
1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRM_H__
26#define __NOUVEAU_DRM_H__
27
28#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
29
30#include "drm.h"
31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
36struct drm_nouveau_channel_alloc {
37	uint32_t     fb_ctxdma_handle;
38	uint32_t     tt_ctxdma_handle;
39
40	int          channel;
41	uint32_t     pushbuf_domains;
42
43	/* Notifier memory */
44	uint32_t     notifier_handle;
45
46	/* DRM-enforced subchannel assignments */
47	struct {
48		uint32_t handle;
49		uint32_t grclass;
50	} subchan[8];
51	uint32_t nr_subchan;
52};
53
54struct drm_nouveau_channel_free {
55	int channel;
56};
57
58struct drm_nouveau_grobj_alloc {
59	int      channel;
60	uint32_t handle;
61	int      class;
62};
63
64struct drm_nouveau_notifierobj_alloc {
65	uint32_t channel;
66	uint32_t handle;
67	uint32_t size;
68	uint32_t offset;
69};
70
71struct drm_nouveau_gpuobj_free {
72	int      channel;
73	uint32_t handle;
74};
75
76/* FIXME : maybe unify {GET,SET}PARAMs */
77#define NOUVEAU_GETPARAM_PCI_VENDOR      3
78#define NOUVEAU_GETPARAM_PCI_DEVICE      4
79#define NOUVEAU_GETPARAM_BUS_TYPE        5
80#define NOUVEAU_GETPARAM_FB_PHYSICAL     6
81#define NOUVEAU_GETPARAM_AGP_PHYSICAL    7
82#define NOUVEAU_GETPARAM_FB_SIZE         8
83#define NOUVEAU_GETPARAM_AGP_SIZE        9
84#define NOUVEAU_GETPARAM_PCI_PHYSICAL    10
85#define NOUVEAU_GETPARAM_CHIPSET_ID      11
86#define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
87#define NOUVEAU_GETPARAM_GRAPH_UNITS     13
88#define NOUVEAU_GETPARAM_PTIMER_TIME     14
89#define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
90#define NOUVEAU_GETPARAM_HAS_PAGEFLIP    16
91struct drm_nouveau_getparam {
92	uint64_t param;
93	uint64_t value;
94};
95
96struct drm_nouveau_setparam {
97	uint64_t param;
98	uint64_t value;
99};
100
101#define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
102#define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
103#define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
104#define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
105#define NOUVEAU_GEM_DOMAIN_COHERENT  (1 << 4)
106
107#define NOUVEAU_GEM_TILE_COMP        0x00030000 /* nv50-only */
108#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
109#define NOUVEAU_GEM_TILE_16BPP       0x00000001
110#define NOUVEAU_GEM_TILE_32BPP       0x00000002
111#define NOUVEAU_GEM_TILE_ZETA        0x00000004
112#define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
113
114struct drm_nouveau_gem_info {
115	__u32 handle;
116	__u32 domain;
117	__u64 size;
118	__u64 offset;
119	__u64 map_handle;
120	__u32 tile_mode;
121	__u32 tile_flags;
122};
123
124struct drm_nouveau_gem_new {
125	struct drm_nouveau_gem_info info;
126	__u32 channel_hint;
127	__u32 align;
128};
129
130#define NOUVEAU_GEM_MAX_BUFFERS 1024
131struct drm_nouveau_gem_pushbuf_bo_presumed {
132	__u32 valid;
133	__u32 domain;
134	__u64 offset;
135};
136
137struct drm_nouveau_gem_pushbuf_bo {
138	__u64 user_priv;
139	__u32 handle;
140	__u32 read_domains;
141	__u32 write_domains;
142	__u32 valid_domains;
143	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
144};
145
146#define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
147#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
148#define NOUVEAU_GEM_RELOC_OR   (1 << 2)
149#define NOUVEAU_GEM_MAX_RELOCS 1024
150struct drm_nouveau_gem_pushbuf_reloc {
151	__u32 reloc_bo_index;
152	__u32 reloc_bo_offset;
153	__u32 bo_index;
154	__u32 flags;
155	__u32 data;
156	__u32 vor;
157	__u32 tor;
158};
159
160#define NOUVEAU_GEM_MAX_PUSH 512
161struct drm_nouveau_gem_pushbuf_push {
162	__u32 bo_index;
163	__u32 pad;
164	__u64 offset;
165	__u64 length;
166};
167
168struct drm_nouveau_gem_pushbuf {
169	__u32 channel;
170	__u32 nr_buffers;
171	__u64 buffers;
172	__u32 nr_relocs;
173	__u32 nr_push;
174	__u64 relocs;
175	__u64 push;
176	__u32 suffix0;
177	__u32 suffix1;
178	__u64 vram_available;
179	__u64 gart_available;
180};
181
182#define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
183#define NOUVEAU_GEM_CPU_PREP_NOBLOCK                                 0x00000002
184#define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
185struct drm_nouveau_gem_cpu_prep {
186	__u32 handle;
187	__u32 flags;
188};
189
190struct drm_nouveau_gem_cpu_fini {
191	__u32 handle;
192};
193
194enum nouveau_bus_type {
195	NV_AGP     = 0,
196	NV_PCI     = 1,
197	NV_PCIE    = 2,
198};
199
200struct drm_nouveau_sarea {
201};
202
203#define DRM_NOUVEAU_GETPARAM           0x00
204#define DRM_NOUVEAU_SETPARAM           0x01
205#define DRM_NOUVEAU_CHANNEL_ALLOC      0x02
206#define DRM_NOUVEAU_CHANNEL_FREE       0x03
207#define DRM_NOUVEAU_GROBJ_ALLOC        0x04
208#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05
209#define DRM_NOUVEAU_GPUOBJ_FREE        0x06
210#define DRM_NOUVEAU_NVIF               0x07
211#define DRM_NOUVEAU_GEM_NEW            0x40
212#define DRM_NOUVEAU_GEM_PUSHBUF        0x41
213#define DRM_NOUVEAU_GEM_CPU_PREP       0x42
214#define DRM_NOUVEAU_GEM_CPU_FINI       0x43
215#define DRM_NOUVEAU_GEM_INFO           0x44
216
217#if defined(__cplusplus)
218}
219#endif
220
221#endif /* __NOUVEAU_DRM_H__ */
222