via_drm.h revision 00a23bda
122944501Smrg/*
222944501Smrg * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
322944501Smrg * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
422944501Smrg *
522944501Smrg * Permission is hereby granted, free of charge, to any person obtaining a
622944501Smrg * copy of this software and associated documentation files (the "Software"),
722944501Smrg * to deal in the Software without restriction, including without limitation
822944501Smrg * the rights to use, copy, modify, merge, publish, distribute, sub license,
922944501Smrg * and/or sell copies of the Software, and to permit persons to whom the
1022944501Smrg * Software is furnished to do so, subject to the following conditions:
1122944501Smrg *
1222944501Smrg * The above copyright notice and this permission notice (including the
1322944501Smrg * next paragraph) shall be included in all copies or substantial portions
1422944501Smrg * of the Software.
1522944501Smrg *
1622944501Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1722944501Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1822944501Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
1922944501Smrg * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
2022944501Smrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2122944501Smrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
2222944501Smrg * DEALINGS IN THE SOFTWARE.
2322944501Smrg */
2422944501Smrg#ifndef _VIA_DRM_H_
2522944501Smrg#define _VIA_DRM_H_
2622944501Smrg
2722944501Smrg#include "drm.h"
2822944501Smrg
2900a23bdaSmrg#if defined(__cplusplus)
3000a23bdaSmrgextern "C" {
3100a23bdaSmrg#endif
3200a23bdaSmrg
3322944501Smrg/* WARNING: These defines must be the same as what the Xserver uses.
3422944501Smrg * if you change them, you must change the defines in the Xserver.
3522944501Smrg */
3622944501Smrg
3722944501Smrg#ifndef _VIA_DEFINES_
3822944501Smrg#define _VIA_DEFINES_
3922944501Smrg
4022944501Smrg#include "via_drmclient.h"
4122944501Smrg
4222944501Smrg#define VIA_NR_SAREA_CLIPRECTS		8
4322944501Smrg#define VIA_NR_XVMC_PORTS               10
4422944501Smrg#define VIA_NR_XVMC_LOCKS               5
4522944501Smrg#define VIA_MAX_CACHELINE_SIZE          64
4622944501Smrg#define XVMCLOCKPTR(saPriv,lockNo)					\
4722944501Smrg	((__volatile__ struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
4822944501Smrg				      (VIA_MAX_CACHELINE_SIZE - 1)) &	\
4922944501Smrg				     ~(VIA_MAX_CACHELINE_SIZE - 1)) +	\
5022944501Smrg				    VIA_MAX_CACHELINE_SIZE*(lockNo)))
5122944501Smrg
5222944501Smrg/* Each region is a minimum of 64k, and there are at most 64 of them.
5322944501Smrg */
5422944501Smrg#define VIA_NR_TEX_REGIONS 64
5522944501Smrg#define VIA_LOG_MIN_TEX_REGION_SIZE 16
5622944501Smrg#endif
5722944501Smrg
5822944501Smrg#define VIA_UPLOAD_TEX0IMAGE  0x1	/* handled clientside */
5922944501Smrg#define VIA_UPLOAD_TEX1IMAGE  0x2	/* handled clientside */
6022944501Smrg#define VIA_UPLOAD_CTX        0x4
6122944501Smrg#define VIA_UPLOAD_BUFFERS    0x8
6222944501Smrg#define VIA_UPLOAD_TEX0       0x10
6322944501Smrg#define VIA_UPLOAD_TEX1       0x20
6422944501Smrg#define VIA_UPLOAD_CLIPRECTS  0x40
6522944501Smrg#define VIA_UPLOAD_ALL        0xff
6622944501Smrg
6722944501Smrg/* VIA specific ioctls */
6822944501Smrg#define DRM_VIA_ALLOCMEM	0x00
6922944501Smrg#define DRM_VIA_FREEMEM	        0x01
7022944501Smrg#define DRM_VIA_AGP_INIT	0x02
7122944501Smrg#define DRM_VIA_FB_INIT	        0x03
7222944501Smrg#define DRM_VIA_MAP_INIT	0x04
7322944501Smrg#define DRM_VIA_DEC_FUTEX       0x05
7422944501Smrg#define NOT_USED
7522944501Smrg#define DRM_VIA_DMA_INIT	0x07
7622944501Smrg#define DRM_VIA_CMDBUFFER	0x08
7722944501Smrg#define DRM_VIA_FLUSH	        0x09
7822944501Smrg#define DRM_VIA_PCICMD	        0x0a
7922944501Smrg#define DRM_VIA_CMDBUF_SIZE	0x0b
8022944501Smrg#define NOT_USED
8122944501Smrg#define DRM_VIA_WAIT_IRQ        0x0d
8222944501Smrg#define DRM_VIA_DMA_BLIT        0x0e
8322944501Smrg#define DRM_VIA_BLIT_SYNC       0x0f
8422944501Smrg
8522944501Smrg#define DRM_IOCTL_VIA_ALLOCMEM	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
8622944501Smrg#define DRM_IOCTL_VIA_FREEMEM	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
8722944501Smrg#define DRM_IOCTL_VIA_AGP_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
8822944501Smrg#define DRM_IOCTL_VIA_FB_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
8922944501Smrg#define DRM_IOCTL_VIA_MAP_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
9022944501Smrg#define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
9122944501Smrg#define DRM_IOCTL_VIA_DMA_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
9222944501Smrg#define DRM_IOCTL_VIA_CMDBUFFER	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
9322944501Smrg#define DRM_IOCTL_VIA_FLUSH	  DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
9422944501Smrg#define DRM_IOCTL_VIA_PCICMD	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
9522944501Smrg#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
9622944501Smrg					    drm_via_cmdbuf_size_t)
9722944501Smrg#define DRM_IOCTL_VIA_WAIT_IRQ    DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
9822944501Smrg#define DRM_IOCTL_VIA_DMA_BLIT    DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
9922944501Smrg#define DRM_IOCTL_VIA_BLIT_SYNC   DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
10022944501Smrg
10122944501Smrg/* Indices into buf.Setup where various bits of state are mirrored per
10222944501Smrg * context and per buffer.  These can be fired at the card as a unit,
10322944501Smrg * or in a piecewise fashion as required.
10422944501Smrg */
10522944501Smrg
10622944501Smrg#define VIA_TEX_SETUP_SIZE 8
10722944501Smrg
10822944501Smrg/* Flags for clear ioctl
10922944501Smrg */
11022944501Smrg#define VIA_FRONT   0x1
11122944501Smrg#define VIA_BACK    0x2
11222944501Smrg#define VIA_DEPTH   0x4
11322944501Smrg#define VIA_STENCIL 0x8
11422944501Smrg#define VIA_MEM_VIDEO   0	/* matches drm constant */
11522944501Smrg#define VIA_MEM_AGP     1	/* matches drm constant */
11622944501Smrg#define VIA_MEM_SYSTEM  2
11722944501Smrg#define VIA_MEM_MIXED   3
11822944501Smrg#define VIA_MEM_UNKNOWN 4
11922944501Smrg
12022944501Smrgtypedef struct {
12122944501Smrg	__u32 offset;
12222944501Smrg	__u32 size;
12322944501Smrg} drm_via_agp_t;
12422944501Smrg
12522944501Smrgtypedef struct {
12622944501Smrg	__u32 offset;
12722944501Smrg	__u32 size;
12822944501Smrg} drm_via_fb_t;
12922944501Smrg
13022944501Smrgtypedef struct {
13122944501Smrg	__u32 context;
13222944501Smrg	__u32 type;
13322944501Smrg	__u32 size;
13422944501Smrg	unsigned long index;
13522944501Smrg	unsigned long offset;
13622944501Smrg} drm_via_mem_t;
13722944501Smrg
13822944501Smrgtypedef struct _drm_via_init {
13922944501Smrg	enum {
14022944501Smrg		VIA_INIT_MAP = 0x01,
14122944501Smrg		VIA_CLEANUP_MAP = 0x02
14222944501Smrg	} func;
14322944501Smrg
14422944501Smrg	unsigned long sarea_priv_offset;
14522944501Smrg	unsigned long fb_offset;
14622944501Smrg	unsigned long mmio_offset;
14722944501Smrg	unsigned long agpAddr;
14822944501Smrg} drm_via_init_t;
14922944501Smrg
15022944501Smrgtypedef struct _drm_via_futex {
15122944501Smrg	enum {
15222944501Smrg		VIA_FUTEX_WAIT = 0x00,
15322944501Smrg		VIA_FUTEX_WAKE = 0X01
15422944501Smrg	} func;
15522944501Smrg	__u32 ms;
15622944501Smrg	__u32 lock;
15722944501Smrg	__u32 val;
15822944501Smrg} drm_via_futex_t;
15922944501Smrg
16022944501Smrgtypedef struct _drm_via_dma_init {
16122944501Smrg	enum {
16222944501Smrg		VIA_INIT_DMA = 0x01,
16322944501Smrg		VIA_CLEANUP_DMA = 0x02,
16422944501Smrg		VIA_DMA_INITIALIZED = 0x03
16522944501Smrg	} func;
16622944501Smrg
16722944501Smrg	unsigned long offset;
16822944501Smrg	unsigned long size;
16922944501Smrg	unsigned long reg_pause_addr;
17022944501Smrg} drm_via_dma_init_t;
17122944501Smrg
17222944501Smrgtypedef struct _drm_via_cmdbuffer {
17322944501Smrg	char *buf;
17422944501Smrg	unsigned long size;
17522944501Smrg} drm_via_cmdbuffer_t;
17622944501Smrg
17722944501Smrg/* Warning: If you change the SAREA structure you must change the Xserver
17822944501Smrg * structure as well */
17922944501Smrg
18022944501Smrgtypedef struct _drm_via_tex_region {
18122944501Smrg	unsigned char next, prev;	/* indices to form a circular LRU  */
18222944501Smrg	unsigned char inUse;	/* owned by a client, or free? */
18322944501Smrg	int age;		/* tracked by clients to update local LRU's */
18422944501Smrg} drm_via_tex_region_t;
18522944501Smrg
18622944501Smrgtypedef struct _drm_via_sarea {
18722944501Smrg	unsigned int dirty;
18822944501Smrg	unsigned int nbox;
18922944501Smrg	struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
19022944501Smrg	drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
19122944501Smrg	int texAge;		/* last time texture was uploaded */
19222944501Smrg	int ctxOwner;		/* last context to upload state */
19322944501Smrg	int vertexPrim;
19422944501Smrg
19522944501Smrg	/*
19622944501Smrg	 * Below is for XvMC.
19722944501Smrg	 * We want the lock integers alone on, and aligned to, a cache line.
19822944501Smrg	 * Therefore this somewhat strange construct.
19922944501Smrg	 */
20022944501Smrg
20122944501Smrg	char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
20222944501Smrg
20322944501Smrg	unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
20422944501Smrg	unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
20522944501Smrg	unsigned int XvMCCtxNoGrabbed;	/* Last context to hold decoder */
20622944501Smrg
20722944501Smrg	/* Used by the 3d driver only at this point, for pageflipping:
20822944501Smrg	 */
20922944501Smrg	unsigned int pfCurrentOffset;
21022944501Smrg} drm_via_sarea_t;
21122944501Smrg
21222944501Smrgtypedef struct _drm_via_cmdbuf_size {
21322944501Smrg	enum {
21422944501Smrg		VIA_CMDBUF_SPACE = 0x01,
21522944501Smrg		VIA_CMDBUF_LAG = 0x02
21622944501Smrg	} func;
21722944501Smrg	int wait;
21822944501Smrg	__u32 size;
21922944501Smrg} drm_via_cmdbuf_size_t;
22022944501Smrg
22122944501Smrgtypedef enum {
22222944501Smrg	VIA_IRQ_ABSOLUTE = 0x0,
22322944501Smrg	VIA_IRQ_RELATIVE = 0x1,
22422944501Smrg	VIA_IRQ_SIGNAL = 0x10000000,
22522944501Smrg	VIA_IRQ_FORCE_SEQUENCE = 0x20000000
22622944501Smrg} via_irq_seq_type_t;
22722944501Smrg
22822944501Smrg#define VIA_IRQ_FLAGS_MASK 0xF0000000
22922944501Smrg
23022944501Smrgenum drm_via_irqs {
23122944501Smrg	drm_via_irq_hqv0 = 0,
23222944501Smrg	drm_via_irq_hqv1,
23322944501Smrg	drm_via_irq_dma0_dd,
23422944501Smrg	drm_via_irq_dma0_td,
23522944501Smrg	drm_via_irq_dma1_dd,
23622944501Smrg	drm_via_irq_dma1_td,
23722944501Smrg	drm_via_irq_num
23822944501Smrg};
23922944501Smrg
24022944501Smrgstruct drm_via_wait_irq_request {
24122944501Smrg	unsigned irq;
24222944501Smrg	via_irq_seq_type_t type;
24322944501Smrg	__u32 sequence;
24422944501Smrg	__u32 signal;
24522944501Smrg};
24622944501Smrg
24722944501Smrgtypedef union drm_via_irqwait {
24822944501Smrg	struct drm_via_wait_irq_request request;
24922944501Smrg	struct drm_wait_vblank_reply reply;
25022944501Smrg} drm_via_irqwait_t;
25122944501Smrg
25222944501Smrgtypedef struct drm_via_blitsync {
25322944501Smrg	__u32 sync_handle;
25422944501Smrg	unsigned engine;
25522944501Smrg} drm_via_blitsync_t;
25622944501Smrg
25722944501Smrg/* - * Below,"flags" is currently unused but will be used for possible future
25822944501Smrg * extensions like kernel space bounce buffers for bad alignments and
25922944501Smrg * blit engine busy-wait polling for better latency in the absence of
26022944501Smrg * interrupts.
26122944501Smrg */
26222944501Smrg
26322944501Smrgtypedef struct drm_via_dmablit {
26422944501Smrg	__u32 num_lines;
26522944501Smrg	__u32 line_length;
26622944501Smrg
26722944501Smrg	__u32 fb_addr;
26822944501Smrg	__u32 fb_stride;
26922944501Smrg
27022944501Smrg	unsigned char *mem_addr;
27122944501Smrg	__u32 mem_stride;
27222944501Smrg
27322944501Smrg	__u32 flags;
27422944501Smrg	int to_fb;
27522944501Smrg
27622944501Smrg	drm_via_blitsync_t sync;
27722944501Smrg} drm_via_dmablit_t;
27822944501Smrg
27900a23bdaSmrg#if defined(__cplusplus)
28000a23bdaSmrg}
28100a23bdaSmrg#endif
28200a23bdaSmrg
28322944501Smrg#endif				/* _VIA_DRM_H_ */
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