intel_bufmgr.c revision 13d1d17d 
1/*
2 * Copyright © 2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 *    Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#ifdef HAVE_CONFIG_H
29#include "config.h"
30#endif
31
32#include <string.h>
33#include <stdlib.h>
34#include <stdint.h>
35#include <assert.h>
36#include <errno.h>
37#include <drm.h>
38#include <i915_drm.h>
39#include "intel_bufmgr.h"
40#include "intel_bufmgr_priv.h"
41
42/** @file intel_bufmgr.c
43 *
44 * Convenience functions for buffer management methods.
45 */
46
47drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
48				 unsigned long size, unsigned int alignment)
49{
50	return bufmgr->bo_alloc(bufmgr, name, size, alignment);
51}
52
53drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
54					    const char *name,
55					    unsigned long size,
56					    unsigned int alignment)
57{
58	return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
59}
60
61drm_intel_bo *
62drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
63                        int x, int y, int cpp, uint32_t *tiling_mode,
64                        unsigned long *pitch, unsigned long flags)
65{
66	return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
67				      tiling_mode, pitch, flags);
68}
69
70void drm_intel_bo_reference(drm_intel_bo *bo)
71{
72	bo->bufmgr->bo_reference(bo);
73}
74
75void drm_intel_bo_unreference(drm_intel_bo *bo)
76{
77	if (bo == NULL)
78		return;
79
80	bo->bufmgr->bo_unreference(bo);
81}
82
83int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
84{
85	return buf->bufmgr->bo_map(buf, write_enable);
86}
87
88int drm_intel_bo_unmap(drm_intel_bo *buf)
89{
90	return buf->bufmgr->bo_unmap(buf);
91}
92
93int
94drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
95		     unsigned long size, const void *data)
96{
97	int ret;
98
99	if (bo->bufmgr->bo_subdata)
100		return bo->bufmgr->bo_subdata(bo, offset, size, data);
101	if (size == 0 || data == NULL)
102		return 0;
103
104	ret = drm_intel_bo_map(bo, 1);
105	if (ret)
106		return ret;
107	memcpy((unsigned char *)bo->virtual + offset, data, size);
108	drm_intel_bo_unmap(bo);
109	return 0;
110}
111
112int
113drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
114			 unsigned long size, void *data)
115{
116	int ret;
117	if (bo->bufmgr->bo_subdata)
118		return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
119
120	if (size == 0 || data == NULL)
121		return 0;
122
123	ret = drm_intel_bo_map(bo, 0);
124	if (ret)
125		return ret;
126	memcpy(data, (unsigned char *)bo->virtual + offset, size);
127	drm_intel_bo_unmap(bo);
128	return 0;
129}
130
131void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
132{
133	bo->bufmgr->bo_wait_rendering(bo);
134}
135
136void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
137{
138	bufmgr->destroy(bufmgr);
139}
140
141int
142drm_intel_bo_exec(drm_intel_bo *bo, int used,
143		  drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
144{
145	return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
146}
147
148int
149drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
150		drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
151		int ring_flag)
152{
153	if (bo->bufmgr->bo_mrb_exec)
154		return bo->bufmgr->bo_mrb_exec(bo, used,
155					cliprects, num_cliprects, DR4,
156					ring_flag);
157
158	return -ENODEV;
159}
160
161void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
162{
163	bufmgr->debug = enable_debug;
164}
165
166int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
167{
168	return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
169}
170
171int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
172{
173	if (bo->bufmgr->bo_flink)
174		return bo->bufmgr->bo_flink(bo, name);
175
176	return -ENODEV;
177}
178
179int
180drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
181			drm_intel_bo *target_bo, uint32_t target_offset,
182			uint32_t read_domains, uint32_t write_domain)
183{
184	return bo->bufmgr->bo_emit_reloc(bo, offset,
185					 target_bo, target_offset,
186					 read_domains, write_domain);
187}
188
189/* For fence registers, not GL fences */
190int
191drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
192			      drm_intel_bo *target_bo, uint32_t target_offset,
193			      uint32_t read_domains, uint32_t write_domain)
194{
195	return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
196					       target_bo, target_offset,
197					       read_domains, write_domain);
198}
199
200
201int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
202{
203	if (bo->bufmgr->bo_pin)
204		return bo->bufmgr->bo_pin(bo, alignment);
205
206	return -ENODEV;
207}
208
209int drm_intel_bo_unpin(drm_intel_bo *bo)
210{
211	if (bo->bufmgr->bo_unpin)
212		return bo->bufmgr->bo_unpin(bo);
213
214	return -ENODEV;
215}
216
217int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
218			    uint32_t stride)
219{
220	if (bo->bufmgr->bo_set_tiling)
221		return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
222
223	*tiling_mode = I915_TILING_NONE;
224	return 0;
225}
226
227int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
228			    uint32_t * swizzle_mode)
229{
230	if (bo->bufmgr->bo_get_tiling)
231		return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
232
233	*tiling_mode = I915_TILING_NONE;
234	*swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
235	return 0;
236}
237
238int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
239{
240	if (bo->bufmgr->bo_disable_reuse)
241		return bo->bufmgr->bo_disable_reuse(bo);
242	return 0;
243}
244
245int drm_intel_bo_is_reusable(drm_intel_bo *bo)
246{
247	if (bo->bufmgr->bo_is_reusable)
248		return bo->bufmgr->bo_is_reusable(bo);
249	return 0;
250}
251
252int drm_intel_bo_busy(drm_intel_bo *bo)
253{
254	if (bo->bufmgr->bo_busy)
255		return bo->bufmgr->bo_busy(bo);
256	return 0;
257}
258
259int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
260{
261	if (bo->bufmgr->bo_madvise)
262		return bo->bufmgr->bo_madvise(bo, madv);
263	return -1;
264}
265
266int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
267{
268	return bo->bufmgr->bo_references(bo, target_bo);
269}
270
271int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
272{
273	if (bufmgr->get_pipe_from_crtc_id)
274		return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id);
275	return -1;
276}
277