intel_bufmgr.h revision 69dda199
122944501Smrg/* 222944501Smrg * Copyright © 2008 Intel Corporation 322944501Smrg * 422944501Smrg * Permission is hereby granted, free of charge, to any person obtaining a 522944501Smrg * copy of this software and associated documentation files (the "Software"), 622944501Smrg * to deal in the Software without restriction, including without limitation 722944501Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 822944501Smrg * and/or sell copies of the Software, and to permit persons to whom the 922944501Smrg * Software is furnished to do so, subject to the following conditions: 1022944501Smrg * 1122944501Smrg * The above copyright notice and this permission notice (including the next 1222944501Smrg * paragraph) shall be included in all copies or substantial portions of the 1322944501Smrg * Software. 1422944501Smrg * 1522944501Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1622944501Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1722944501Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1822944501Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1922944501Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2022944501Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 2122944501Smrg * IN THE SOFTWARE. 2222944501Smrg * 2322944501Smrg * Authors: 2422944501Smrg * Eric Anholt <eric@anholt.net> 2522944501Smrg * 2622944501Smrg */ 2722944501Smrg 2822944501Smrg/** 2922944501Smrg * @file intel_bufmgr.h 3022944501Smrg * 3122944501Smrg * Public definitions of Intel-specific bufmgr functions. 3222944501Smrg */ 3322944501Smrg 3422944501Smrg#ifndef INTEL_BUFMGR_H 3522944501Smrg#define INTEL_BUFMGR_H 3622944501Smrg 3722944501Smrg#include <stdint.h> 3822944501Smrg 3969dda199Smrgstruct drm_clip_rect; 4069dda199Smrg 4122944501Smrgtypedef struct _drm_intel_bufmgr drm_intel_bufmgr; 4222944501Smrgtypedef struct _drm_intel_bo drm_intel_bo; 4322944501Smrg 4422944501Smrgstruct _drm_intel_bo { 4522944501Smrg /** 4622944501Smrg * Size in bytes of the buffer object. 4722944501Smrg * 4822944501Smrg * The size may be larger than the size originally requested for the 4922944501Smrg * allocation, such as being aligned to page size. 5022944501Smrg */ 5122944501Smrg unsigned long size; 5222944501Smrg 5322944501Smrg /** 5422944501Smrg * Alignment requirement for object 5522944501Smrg * 5622944501Smrg * Used for GTT mapping & pinning the object. 5722944501Smrg */ 5822944501Smrg unsigned long align; 5922944501Smrg 6022944501Smrg /** 6122944501Smrg * Last seen card virtual address (offset from the beginning of the 6222944501Smrg * aperture) for the object. This should be used to fill relocation 6322944501Smrg * entries when calling drm_intel_bo_emit_reloc() 6422944501Smrg */ 6522944501Smrg unsigned long offset; 6622944501Smrg 6722944501Smrg /** 6822944501Smrg * Virtual address for accessing the buffer data. Only valid while 6922944501Smrg * mapped. 7022944501Smrg */ 71d049871aSmrg#ifdef __cplusplus 72d049871aSmrg void *virt; 73d049871aSmrg#else 7422944501Smrg void *virtual; 75d049871aSmrg#endif 7622944501Smrg 7722944501Smrg /** Buffer manager context associated with this buffer object */ 7822944501Smrg drm_intel_bufmgr *bufmgr; 7922944501Smrg 8022944501Smrg /** 8122944501Smrg * MM-specific handle for accessing object 8222944501Smrg */ 8322944501Smrg int handle; 8422944501Smrg}; 8522944501Smrg 8622944501Smrg#define BO_ALLOC_FOR_RENDER (1<<0) 8722944501Smrg 8822944501Smrgdrm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, 8922944501Smrg unsigned long size, unsigned int alignment); 9022944501Smrgdrm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, 9122944501Smrg const char *name, 9222944501Smrg unsigned long size, 9322944501Smrg unsigned int alignment); 9422944501Smrgdrm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, 9522944501Smrg const char *name, 9622944501Smrg int x, int y, int cpp, 9722944501Smrg uint32_t *tiling_mode, 9822944501Smrg unsigned long *pitch, 9922944501Smrg unsigned long flags); 10022944501Smrgvoid drm_intel_bo_reference(drm_intel_bo *bo); 10122944501Smrgvoid drm_intel_bo_unreference(drm_intel_bo *bo); 10222944501Smrgint drm_intel_bo_map(drm_intel_bo *bo, int write_enable); 10322944501Smrgint drm_intel_bo_unmap(drm_intel_bo *bo); 10422944501Smrg 10522944501Smrgint drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, 10622944501Smrg unsigned long size, const void *data); 10722944501Smrgint drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, 10822944501Smrg unsigned long size, void *data); 10922944501Smrgvoid drm_intel_bo_wait_rendering(drm_intel_bo *bo); 11022944501Smrg 11122944501Smrgvoid drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug); 11222944501Smrgvoid drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr); 11322944501Smrgint drm_intel_bo_exec(drm_intel_bo *bo, int used, 11469dda199Smrg struct drm_clip_rect *cliprects, int num_cliprects, int DR4); 11513d1d17dSmrgint drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used, 11669dda199Smrg struct drm_clip_rect *cliprects, int num_cliprects, int DR4, 11713d1d17dSmrg int ring_flag); 11822944501Smrgint drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count); 11922944501Smrg 12022944501Smrgint drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, 12122944501Smrg drm_intel_bo *target_bo, uint32_t target_offset, 12222944501Smrg uint32_t read_domains, uint32_t write_domain); 12322944501Smrgint drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, 12422944501Smrg drm_intel_bo *target_bo, 12522944501Smrg uint32_t target_offset, 12622944501Smrg uint32_t read_domains, uint32_t write_domain); 12722944501Smrgint drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment); 12822944501Smrgint drm_intel_bo_unpin(drm_intel_bo *bo); 12922944501Smrgint drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 13022944501Smrg uint32_t stride); 13122944501Smrgint drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 13222944501Smrg uint32_t * swizzle_mode); 13322944501Smrgint drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name); 13422944501Smrgint drm_intel_bo_busy(drm_intel_bo *bo); 13522944501Smrgint drm_intel_bo_madvise(drm_intel_bo *bo, int madv); 13622944501Smrg 13722944501Smrgint drm_intel_bo_disable_reuse(drm_intel_bo *bo); 13813d1d17dSmrgint drm_intel_bo_is_reusable(drm_intel_bo *bo); 13922944501Smrgint drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo); 14022944501Smrg 14122944501Smrg/* drm_intel_bufmgr_gem.c */ 14222944501Smrgdrm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size); 14322944501Smrgdrm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, 14422944501Smrg const char *name, 14522944501Smrg unsigned int handle); 14622944501Smrgvoid drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr); 14722944501Smrgvoid drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr); 14822944501Smrgint drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); 14922944501Smrgint drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo); 15022944501Smrgvoid drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); 15122944501Smrg 15222944501Smrgint drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id); 15322944501Smrg 15422944501Smrg/* drm_intel_bufmgr_fake.c */ 15522944501Smrgdrm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, 15622944501Smrg unsigned long low_offset, 15722944501Smrg void *low_virtual, 15822944501Smrg unsigned long size, 15922944501Smrg volatile unsigned int 16022944501Smrg *last_dispatch); 16122944501Smrgvoid drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr, 16222944501Smrg volatile unsigned int 16322944501Smrg *last_dispatch); 16422944501Smrgvoid drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr, 16522944501Smrg int (*exec) (drm_intel_bo *bo, 16622944501Smrg unsigned int used, 16722944501Smrg void *priv), 16822944501Smrg void *priv); 16922944501Smrgvoid drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr, 17022944501Smrg unsigned int (*emit) (void *priv), 17122944501Smrg void (*wait) (unsigned int fence, 17222944501Smrg void *priv), 17322944501Smrg void *priv); 17422944501Smrgdrm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr, 17522944501Smrg const char *name, 17622944501Smrg unsigned long offset, 177d049871aSmrg unsigned long size, void *virt); 17822944501Smrgvoid drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo, 17922944501Smrg void (*invalidate_cb) (drm_intel_bo 18022944501Smrg * bo, 18122944501Smrg void *ptr), 18222944501Smrg void *ptr); 18322944501Smrg 18422944501Smrgvoid drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr); 18522944501Smrgvoid drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr); 18622944501Smrg 18722944501Smrg/** @{ Compatibility defines to keep old code building despite the symbol rename 18822944501Smrg * from dri_* to drm_intel_* 18922944501Smrg */ 19022944501Smrg#define dri_bo drm_intel_bo 19122944501Smrg#define dri_bufmgr drm_intel_bufmgr 19222944501Smrg#define dri_bo_alloc drm_intel_bo_alloc 19322944501Smrg#define dri_bo_reference drm_intel_bo_reference 19422944501Smrg#define dri_bo_unreference drm_intel_bo_unreference 19522944501Smrg#define dri_bo_map drm_intel_bo_map 19622944501Smrg#define dri_bo_unmap drm_intel_bo_unmap 19722944501Smrg#define dri_bo_subdata drm_intel_bo_subdata 19822944501Smrg#define dri_bo_get_subdata drm_intel_bo_get_subdata 19922944501Smrg#define dri_bo_wait_rendering drm_intel_bo_wait_rendering 20022944501Smrg#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug 20122944501Smrg#define dri_bufmgr_destroy drm_intel_bufmgr_destroy 20222944501Smrg#define dri_bo_exec drm_intel_bo_exec 20322944501Smrg#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space 20422944501Smrg#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \ 20522944501Smrg reloc_offset, target_bo) \ 20622944501Smrg drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \ 20722944501Smrg target_bo, target_offset, \ 20822944501Smrg read, write); 20922944501Smrg#define dri_bo_pin drm_intel_bo_pin 21022944501Smrg#define dri_bo_unpin drm_intel_bo_unpin 21122944501Smrg#define dri_bo_get_tiling drm_intel_bo_get_tiling 21222944501Smrg#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0) 21322944501Smrg#define dri_bo_flink drm_intel_bo_flink 21422944501Smrg#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init 21522944501Smrg#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name 21622944501Smrg#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse 21722944501Smrg#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init 21822944501Smrg#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch 21922944501Smrg#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback 22022944501Smrg#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback 22122944501Smrg#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static 22222944501Smrg#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store 22322944501Smrg#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take 22422944501Smrg#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all 22522944501Smrg 22622944501Smrg/** @{ */ 22722944501Smrg 22822944501Smrg#endif /* INTEL_BUFMGR_H */ 229