intel_bufmgr.h revision e88f27b3
1/* 2 * Copyright © 2008-2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28/** 29 * @file intel_bufmgr.h 30 * 31 * Public definitions of Intel-specific bufmgr functions. 32 */ 33 34#ifndef INTEL_BUFMGR_H 35#define INTEL_BUFMGR_H 36 37#include <stdio.h> 38#include <stdint.h> 39#include <stdio.h> 40 41struct drm_clip_rect; 42 43typedef struct _drm_intel_bufmgr drm_intel_bufmgr; 44typedef struct _drm_intel_context drm_intel_context; 45typedef struct _drm_intel_bo drm_intel_bo; 46 47struct _drm_intel_bo { 48 /** 49 * Size in bytes of the buffer object. 50 * 51 * The size may be larger than the size originally requested for the 52 * allocation, such as being aligned to page size. 53 */ 54 unsigned long size; 55 56 /** 57 * Alignment requirement for object 58 * 59 * Used for GTT mapping & pinning the object. 60 */ 61 unsigned long align; 62 63 /** 64 * Deprecated field containing (possibly the low 32-bits of) the last 65 * seen virtual card address. Use offset64 instead. 66 */ 67 unsigned long offset; 68 69 /** 70 * Virtual address for accessing the buffer data. Only valid while 71 * mapped. 72 */ 73#ifdef __cplusplus 74 void *virt; 75#else 76 void *virtual; 77#endif 78 79 /** Buffer manager context associated with this buffer object */ 80 drm_intel_bufmgr *bufmgr; 81 82 /** 83 * MM-specific handle for accessing object 84 */ 85 int handle; 86 87 /** 88 * Last seen card virtual address (offset from the beginning of the 89 * aperture) for the object. This should be used to fill relocation 90 * entries when calling drm_intel_bo_emit_reloc() 91 */ 92 uint64_t offset64; 93}; 94 95enum aub_dump_bmp_format { 96 AUB_DUMP_BMP_FORMAT_8BIT = 1, 97 AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4, 98 AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6, 99 AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7, 100}; 101 102typedef struct _drm_intel_aub_annotation { 103 uint32_t type; 104 uint32_t subtype; 105 uint32_t ending_offset; 106} drm_intel_aub_annotation; 107 108#define BO_ALLOC_FOR_RENDER (1<<0) 109 110drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, 111 unsigned long size, unsigned int alignment); 112drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, 113 const char *name, 114 unsigned long size, 115 unsigned int alignment); 116drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, 117 const char *name, 118 int x, int y, int cpp, 119 uint32_t *tiling_mode, 120 unsigned long *pitch, 121 unsigned long flags); 122void drm_intel_bo_reference(drm_intel_bo *bo); 123void drm_intel_bo_unreference(drm_intel_bo *bo); 124int drm_intel_bo_map(drm_intel_bo *bo, int write_enable); 125int drm_intel_bo_unmap(drm_intel_bo *bo); 126 127int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, 128 unsigned long size, const void *data); 129int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, 130 unsigned long size, void *data); 131void drm_intel_bo_wait_rendering(drm_intel_bo *bo); 132 133void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug); 134void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr); 135int drm_intel_bo_exec(drm_intel_bo *bo, int used, 136 struct drm_clip_rect *cliprects, int num_cliprects, int DR4); 137int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used, 138 struct drm_clip_rect *cliprects, int num_cliprects, int DR4, 139 unsigned int flags); 140int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count); 141 142int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, 143 drm_intel_bo *target_bo, uint32_t target_offset, 144 uint32_t read_domains, uint32_t write_domain); 145int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, 146 drm_intel_bo *target_bo, 147 uint32_t target_offset, 148 uint32_t read_domains, uint32_t write_domain); 149int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment); 150int drm_intel_bo_unpin(drm_intel_bo *bo); 151int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 152 uint32_t stride); 153int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 154 uint32_t * swizzle_mode); 155int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name); 156int drm_intel_bo_busy(drm_intel_bo *bo); 157int drm_intel_bo_madvise(drm_intel_bo *bo, int madv); 158 159int drm_intel_bo_disable_reuse(drm_intel_bo *bo); 160int drm_intel_bo_is_reusable(drm_intel_bo *bo); 161int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo); 162 163/* drm_intel_bufmgr_gem.c */ 164drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size); 165drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, 166 const char *name, 167 unsigned int handle); 168void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr); 169void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr); 170void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, 171 int limit); 172int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo); 173int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); 174int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo); 175 176int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo); 177void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start); 178void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); 179 180void 181drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr, 182 const char *filename); 183void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable); 184void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo, 185 int x1, int y1, int width, int height, 186 enum aub_dump_bmp_format format, 187 int pitch, int offset); 188void 189drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo, 190 drm_intel_aub_annotation *annotations, 191 unsigned count); 192 193int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id); 194 195int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total); 196int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr); 197int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns); 198 199drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr); 200void drm_intel_gem_context_destroy(drm_intel_context *ctx); 201int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx, 202 int used, unsigned int flags); 203 204int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd); 205drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, 206 int prime_fd, int size); 207 208/* drm_intel_bufmgr_fake.c */ 209drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, 210 unsigned long low_offset, 211 void *low_virtual, 212 unsigned long size, 213 volatile unsigned int 214 *last_dispatch); 215void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr, 216 volatile unsigned int 217 *last_dispatch); 218void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr, 219 int (*exec) (drm_intel_bo *bo, 220 unsigned int used, 221 void *priv), 222 void *priv); 223void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr, 224 unsigned int (*emit) (void *priv), 225 void (*wait) (unsigned int fence, 226 void *priv), 227 void *priv); 228drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr, 229 const char *name, 230 unsigned long offset, 231 unsigned long size, void *virt); 232void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo, 233 void (*invalidate_cb) (drm_intel_bo 234 * bo, 235 void *ptr), 236 void *ptr); 237 238void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr); 239void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr); 240 241struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid); 242void drm_intel_decode_context_free(struct drm_intel_decode *ctx); 243void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx, 244 void *data, uint32_t hw_offset, 245 int count); 246void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx, 247 int dump_past_end); 248void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx, 249 uint32_t head, uint32_t tail); 250void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out); 251void drm_intel_decode(struct drm_intel_decode *ctx); 252 253int drm_intel_reg_read(drm_intel_bufmgr *bufmgr, 254 uint32_t offset, 255 uint64_t *result); 256 257int drm_intel_get_reset_stats(drm_intel_context *ctx, 258 uint32_t *reset_count, 259 uint32_t *active, 260 uint32_t *pending); 261 262/** @{ Compatibility defines to keep old code building despite the symbol rename 263 * from dri_* to drm_intel_* 264 */ 265#define dri_bo drm_intel_bo 266#define dri_bufmgr drm_intel_bufmgr 267#define dri_bo_alloc drm_intel_bo_alloc 268#define dri_bo_reference drm_intel_bo_reference 269#define dri_bo_unreference drm_intel_bo_unreference 270#define dri_bo_map drm_intel_bo_map 271#define dri_bo_unmap drm_intel_bo_unmap 272#define dri_bo_subdata drm_intel_bo_subdata 273#define dri_bo_get_subdata drm_intel_bo_get_subdata 274#define dri_bo_wait_rendering drm_intel_bo_wait_rendering 275#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug 276#define dri_bufmgr_destroy drm_intel_bufmgr_destroy 277#define dri_bo_exec drm_intel_bo_exec 278#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space 279#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \ 280 reloc_offset, target_bo) \ 281 drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \ 282 target_bo, target_offset, \ 283 read, write); 284#define dri_bo_pin drm_intel_bo_pin 285#define dri_bo_unpin drm_intel_bo_unpin 286#define dri_bo_get_tiling drm_intel_bo_get_tiling 287#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0) 288#define dri_bo_flink drm_intel_bo_flink 289#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init 290#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name 291#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse 292#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init 293#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch 294#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback 295#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback 296#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static 297#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store 298#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take 299#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all 300 301/** @{ */ 302 303#endif /* INTEL_BUFMGR_H */ 304