intel_chipset.h revision 00a23bda 
1/*
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28#ifndef _INTEL_CHIPSET_H
29#define _INTEL_CHIPSET_H
30
31#define PCI_CHIP_I810			0x7121
32#define PCI_CHIP_I810_DC100		0x7123
33#define PCI_CHIP_I810_E			0x7125
34#define PCI_CHIP_I815			0x1132
35
36#define PCI_CHIP_I830_M			0x3577
37#define PCI_CHIP_845_G			0x2562
38#define PCI_CHIP_I855_GM		0x3582
39#define PCI_CHIP_I865_G			0x2572
40
41#define PCI_CHIP_I915_G			0x2582
42#define PCI_CHIP_E7221_G		0x258A
43#define PCI_CHIP_I915_GM		0x2592
44#define PCI_CHIP_I945_G			0x2772
45#define PCI_CHIP_I945_GM		0x27A2
46#define PCI_CHIP_I945_GME		0x27AE
47
48#define PCI_CHIP_Q35_G			0x29B2
49#define PCI_CHIP_G33_G			0x29C2
50#define PCI_CHIP_Q33_G			0x29D2
51
52#define PCI_CHIP_IGD_GM			0xA011
53#define PCI_CHIP_IGD_G			0xA001
54
55#define IS_IGDGM(devid)		((devid) == PCI_CHIP_IGD_GM)
56#define IS_IGDG(devid)		((devid) == PCI_CHIP_IGD_G)
57#define IS_IGD(devid)		(IS_IGDG(devid) || IS_IGDGM(devid))
58
59#define PCI_CHIP_I965_G			0x29A2
60#define PCI_CHIP_I965_Q			0x2992
61#define PCI_CHIP_I965_G_1		0x2982
62#define PCI_CHIP_I946_GZ		0x2972
63#define PCI_CHIP_I965_GM		0x2A02
64#define PCI_CHIP_I965_GME		0x2A12
65
66#define PCI_CHIP_GM45_GM		0x2A42
67
68#define PCI_CHIP_IGD_E_G		0x2E02
69#define PCI_CHIP_Q45_G			0x2E12
70#define PCI_CHIP_G45_G			0x2E22
71#define PCI_CHIP_G41_G			0x2E32
72
73#define PCI_CHIP_ILD_G			0x0042
74#define PCI_CHIP_ILM_G			0x0046
75
76#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102 /* desktop */
77#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
78#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
79#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106 /* mobile */
80#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
81#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
82#define PCI_CHIP_SANDYBRIDGE_S		0x010A /* server */
83
84#define PCI_CHIP_IVYBRIDGE_GT1		0x0152 /* desktop */
85#define PCI_CHIP_IVYBRIDGE_GT2		0x0162
86#define PCI_CHIP_IVYBRIDGE_M_GT1	0x0156 /* mobile */
87#define PCI_CHIP_IVYBRIDGE_M_GT2	0x0166
88#define PCI_CHIP_IVYBRIDGE_S		0x015a /* server */
89#define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a /* server */
90
91#define PCI_CHIP_HASWELL_GT1		0x0402 /* Desktop */
92#define PCI_CHIP_HASWELL_GT2		0x0412
93#define PCI_CHIP_HASWELL_GT3		0x0422
94#define PCI_CHIP_HASWELL_M_GT1		0x0406 /* Mobile */
95#define PCI_CHIP_HASWELL_M_GT2		0x0416
96#define PCI_CHIP_HASWELL_M_GT3		0x0426
97#define PCI_CHIP_HASWELL_S_GT1		0x040A /* Server */
98#define PCI_CHIP_HASWELL_S_GT2		0x041A
99#define PCI_CHIP_HASWELL_S_GT3		0x042A
100#define PCI_CHIP_HASWELL_B_GT1		0x040B /* Reserved */
101#define PCI_CHIP_HASWELL_B_GT2		0x041B
102#define PCI_CHIP_HASWELL_B_GT3		0x042B
103#define PCI_CHIP_HASWELL_E_GT1		0x040E /* Reserved */
104#define PCI_CHIP_HASWELL_E_GT2		0x041E
105#define PCI_CHIP_HASWELL_E_GT3		0x042E
106#define PCI_CHIP_HASWELL_SDV_GT1	0x0C02 /* Desktop */
107#define PCI_CHIP_HASWELL_SDV_GT2	0x0C12
108#define PCI_CHIP_HASWELL_SDV_GT3	0x0C22
109#define PCI_CHIP_HASWELL_SDV_M_GT1	0x0C06 /* Mobile */
110#define PCI_CHIP_HASWELL_SDV_M_GT2	0x0C16
111#define PCI_CHIP_HASWELL_SDV_M_GT3	0x0C26
112#define PCI_CHIP_HASWELL_SDV_S_GT1	0x0C0A /* Server */
113#define PCI_CHIP_HASWELL_SDV_S_GT2	0x0C1A
114#define PCI_CHIP_HASWELL_SDV_S_GT3	0x0C2A
115#define PCI_CHIP_HASWELL_SDV_B_GT1	0x0C0B /* Reserved */
116#define PCI_CHIP_HASWELL_SDV_B_GT2	0x0C1B
117#define PCI_CHIP_HASWELL_SDV_B_GT3	0x0C2B
118#define PCI_CHIP_HASWELL_SDV_E_GT1	0x0C0E /* Reserved */
119#define PCI_CHIP_HASWELL_SDV_E_GT2	0x0C1E
120#define PCI_CHIP_HASWELL_SDV_E_GT3	0x0C2E
121#define PCI_CHIP_HASWELL_ULT_GT1	0x0A02 /* Desktop */
122#define PCI_CHIP_HASWELL_ULT_GT2	0x0A12
123#define PCI_CHIP_HASWELL_ULT_GT3	0x0A22
124#define PCI_CHIP_HASWELL_ULT_M_GT1	0x0A06 /* Mobile */
125#define PCI_CHIP_HASWELL_ULT_M_GT2	0x0A16
126#define PCI_CHIP_HASWELL_ULT_M_GT3	0x0A26
127#define PCI_CHIP_HASWELL_ULT_S_GT1	0x0A0A /* Server */
128#define PCI_CHIP_HASWELL_ULT_S_GT2	0x0A1A
129#define PCI_CHIP_HASWELL_ULT_S_GT3	0x0A2A
130#define PCI_CHIP_HASWELL_ULT_B_GT1	0x0A0B /* Reserved */
131#define PCI_CHIP_HASWELL_ULT_B_GT2	0x0A1B
132#define PCI_CHIP_HASWELL_ULT_B_GT3	0x0A2B
133#define PCI_CHIP_HASWELL_ULT_E_GT1	0x0A0E /* Reserved */
134#define PCI_CHIP_HASWELL_ULT_E_GT2	0x0A1E
135#define PCI_CHIP_HASWELL_ULT_E_GT3	0x0A2E
136#define PCI_CHIP_HASWELL_CRW_GT1	0x0D02 /* Desktop */
137#define PCI_CHIP_HASWELL_CRW_GT2	0x0D12
138#define PCI_CHIP_HASWELL_CRW_GT3	0x0D22
139#define PCI_CHIP_HASWELL_CRW_M_GT1	0x0D06 /* Mobile */
140#define PCI_CHIP_HASWELL_CRW_M_GT2	0x0D16
141#define PCI_CHIP_HASWELL_CRW_M_GT3	0x0D26
142#define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D0A /* Server */
143#define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D1A
144#define PCI_CHIP_HASWELL_CRW_S_GT3	0x0D2A
145#define PCI_CHIP_HASWELL_CRW_B_GT1	0x0D0B /* Reserved */
146#define PCI_CHIP_HASWELL_CRW_B_GT2	0x0D1B
147#define PCI_CHIP_HASWELL_CRW_B_GT3	0x0D2B
148#define PCI_CHIP_HASWELL_CRW_E_GT1	0x0D0E /* Reserved */
149#define PCI_CHIP_HASWELL_CRW_E_GT2	0x0D1E
150#define PCI_CHIP_HASWELL_CRW_E_GT3	0x0D2E
151#define BDW_SPARE			0x2
152#define BDW_ULT				0x6
153#define BDW_SERVER			0xa
154#define BDW_IRIS			0xb
155#define BDW_WORKSTATION			0xd
156#define BDW_ULX				0xe
157
158#define PCI_CHIP_VALLEYVIEW_PO		0x0f30 /* VLV PO board */
159#define PCI_CHIP_VALLEYVIEW_1		0x0f31
160#define PCI_CHIP_VALLEYVIEW_2		0x0f32
161#define PCI_CHIP_VALLEYVIEW_3		0x0f33
162
163#define PCI_CHIP_CHERRYVIEW_0		0x22b0
164#define PCI_CHIP_CHERRYVIEW_1		0x22b1
165#define PCI_CHIP_CHERRYVIEW_2		0x22b2
166#define PCI_CHIP_CHERRYVIEW_3		0x22b3
167
168#define PCI_CHIP_SKYLAKE_DT_GT1		0x1902
169#define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906
170#define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A /* Reserved */
171#define PCI_CHIP_SKYLAKE_H_GT1		0x190B
172#define PCI_CHIP_SKYLAKE_ULX_GT1	0x190E /* Reserved */
173#define PCI_CHIP_SKYLAKE_DT_GT2		0x1912
174#define PCI_CHIP_SKYLAKE_FUSED0_GT2	0x1913 /* Reserved */
175#define PCI_CHIP_SKYLAKE_FUSED1_GT2	0x1915 /* Reserved */
176#define PCI_CHIP_SKYLAKE_ULT_GT2	0x1916
177#define PCI_CHIP_SKYLAKE_FUSED2_GT2	0x1917 /* Reserved */
178#define PCI_CHIP_SKYLAKE_SRV_GT2	0x191A /* Reserved */
179#define PCI_CHIP_SKYLAKE_HALO_GT2	0x191B
180#define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
181#define PCI_CHIP_SKYLAKE_ULX_GT2	0x191E
182#define PCI_CHIP_SKYLAKE_MOBILE_GT2	0x1921 /* Reserved */
183#define PCI_CHIP_SKYLAKE_ULT_GT3_0	0x1923
184#define PCI_CHIP_SKYLAKE_ULT_GT3_1	0x1926
185#define PCI_CHIP_SKYLAKE_ULT_GT3_2	0x1927
186#define PCI_CHIP_SKYLAKE_SRV_GT4	0x192A
187#define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B /* Reserved */
188#define PCI_CHIP_SKYLAKE_SRV_GT3	0x192D
189#define PCI_CHIP_SKYLAKE_DT_GT4		0x1932
190#define PCI_CHIP_SKYLAKE_SRV_GT4X	0x193A
191#define PCI_CHIP_SKYLAKE_H_GT4		0x193B
192#define PCI_CHIP_SKYLAKE_WKS_GT4	0x193D
193
194#define PCI_CHIP_KABYLAKE_ULT_GT2	0x5916
195#define PCI_CHIP_KABYLAKE_ULT_GT1_5	0x5913
196#define PCI_CHIP_KABYLAKE_ULT_GT1	0x5906
197#define PCI_CHIP_KABYLAKE_ULT_GT3_0	0x5923
198#define PCI_CHIP_KABYLAKE_ULT_GT3_1	0x5926
199#define PCI_CHIP_KABYLAKE_ULT_GT3_2	0x5927
200#define PCI_CHIP_KABYLAKE_ULT_GT2F	0x5921
201#define PCI_CHIP_KABYLAKE_ULX_GT1_5	0x5915
202#define PCI_CHIP_KABYLAKE_ULX_GT1	0x590E
203#define PCI_CHIP_KABYLAKE_ULX_GT2	0x591E
204#define PCI_CHIP_KABYLAKE_DT_GT2	0x5912
205#define PCI_CHIP_KABYLAKE_M_GT2		0x5917
206#define PCI_CHIP_KABYLAKE_DT_GT1	0x5902
207#define PCI_CHIP_KABYLAKE_HALO_GT2	0x591B
208#define PCI_CHIP_KABYLAKE_HALO_GT4	0x593B
209#define PCI_CHIP_KABYLAKE_HALO_GT1_0	0x5908
210#define PCI_CHIP_KABYLAKE_HALO_GT1_1	0x590B
211#define PCI_CHIP_KABYLAKE_SRV_GT2	0x591A
212#define PCI_CHIP_KABYLAKE_SRV_GT1	0x590A
213#define PCI_CHIP_KABYLAKE_WKS_GT2	0x591D
214
215#define PCI_CHIP_BROXTON_0		0x0A84
216#define PCI_CHIP_BROXTON_1		0x1A84
217#define PCI_CHIP_BROXTON_2		0x5A84
218#define PCI_CHIP_BROXTON_3		0x1A85
219#define PCI_CHIP_BROXTON_4		0x5A85
220
221#define PCI_CHIP_GLK			0x3184
222#define PCI_CHIP_GLK_2X6		0x3185
223
224#define PCI_CHIP_COFFEELAKE_S_GT1_1     0x3E90
225#define PCI_CHIP_COFFEELAKE_S_GT1_2     0x3E93
226#define PCI_CHIP_COFFEELAKE_S_GT1_3     0x3E99
227#define PCI_CHIP_COFFEELAKE_S_GT2_1     0x3E91
228#define PCI_CHIP_COFFEELAKE_S_GT2_2     0x3E92
229#define PCI_CHIP_COFFEELAKE_S_GT2_3     0x3E96
230#define PCI_CHIP_COFFEELAKE_S_GT2_4     0x3E9A
231#define PCI_CHIP_COFFEELAKE_H_GT2_1     0x3E9B
232#define PCI_CHIP_COFFEELAKE_H_GT2_2     0x3E94
233#define PCI_CHIP_COFFEELAKE_U_GT1_1     0x3EA1
234#define PCI_CHIP_COFFEELAKE_U_GT1_2     0x3EA4
235#define PCI_CHIP_COFFEELAKE_U_GT2_1     0x3EA0
236#define PCI_CHIP_COFFEELAKE_U_GT2_2     0x3EA3
237#define PCI_CHIP_COFFEELAKE_U_GT2_3     0x3EA9
238#define PCI_CHIP_COFFEELAKE_U_GT3_1     0x3EA2
239#define PCI_CHIP_COFFEELAKE_U_GT3_2     0x3EA5
240#define PCI_CHIP_COFFEELAKE_U_GT3_3     0x3EA6
241#define PCI_CHIP_COFFEELAKE_U_GT3_4     0x3EA7
242#define PCI_CHIP_COFFEELAKE_U_GT3_5     0x3EA8
243
244#define PCI_CHIP_CANNONLAKE_U_GT2_0	0x5A52
245#define PCI_CHIP_CANNONLAKE_U_GT2_1	0x5A5A
246#define PCI_CHIP_CANNONLAKE_U_GT2_2	0x5A42
247#define PCI_CHIP_CANNONLAKE_U_GT2_3	0x5A4A
248#define PCI_CHIP_CANNONLAKE_Y_GT2_0	0x5A51
249#define PCI_CHIP_CANNONLAKE_Y_GT2_1	0x5A59
250#define PCI_CHIP_CANNONLAKE_Y_GT2_2	0x5A41
251#define PCI_CHIP_CANNONLAKE_Y_GT2_3	0x5A49
252#define PCI_CHIP_CANNONLAKE_Y_GT2_4	0x5A71
253#define PCI_CHIP_CANNONLAKE_Y_GT2_5	0x5A79
254
255#define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
256				 (devid) == PCI_CHIP_I915_GM || \
257				 (devid) == PCI_CHIP_I945_GM || \
258				 (devid) == PCI_CHIP_I945_GME || \
259				 (devid) == PCI_CHIP_I965_GM || \
260				 (devid) == PCI_CHIP_I965_GME || \
261				 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
262				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
263				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
264
265#define IS_G45(devid)		((devid) == PCI_CHIP_IGD_E_G || \
266				 (devid) == PCI_CHIP_Q45_G || \
267				 (devid) == PCI_CHIP_G45_G || \
268				 (devid) == PCI_CHIP_G41_G)
269#define IS_GM45(devid)		((devid) == PCI_CHIP_GM45_GM)
270#define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
271
272#define IS_ILD(devid)		((devid) == PCI_CHIP_ILD_G)
273#define IS_ILM(devid)		((devid) == PCI_CHIP_ILM_G)
274
275#define IS_915(devid)		((devid) == PCI_CHIP_I915_G || \
276				 (devid) == PCI_CHIP_E7221_G || \
277				 (devid) == PCI_CHIP_I915_GM)
278
279#define IS_945GM(devid)		((devid) == PCI_CHIP_I945_GM || \
280				 (devid) == PCI_CHIP_I945_GME)
281
282#define IS_945(devid)		((devid) == PCI_CHIP_I945_G || \
283				 (devid) == PCI_CHIP_I945_GM || \
284				 (devid) == PCI_CHIP_I945_GME || \
285				 IS_G33(devid))
286
287#define IS_G33(devid)		((devid) == PCI_CHIP_G33_G || \
288				 (devid) == PCI_CHIP_Q33_G || \
289				 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
290
291#define IS_GEN2(devid)		((devid) == PCI_CHIP_I830_M || \
292				 (devid) == PCI_CHIP_845_G || \
293				 (devid) == PCI_CHIP_I855_GM || \
294				 (devid) == PCI_CHIP_I865_G)
295
296#define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))
297
298#define IS_GEN4(devid)		((devid) == PCI_CHIP_I965_G || \
299				 (devid) == PCI_CHIP_I965_Q || \
300				 (devid) == PCI_CHIP_I965_G_1 || \
301				 (devid) == PCI_CHIP_I965_GM || \
302				 (devid) == PCI_CHIP_I965_GME || \
303				 (devid) == PCI_CHIP_I946_GZ || \
304				 IS_G4X(devid))
305
306#define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))
307
308#define IS_GEN6(devid)		((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
309				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
310				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
311				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
312				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
313				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
314				 (devid) == PCI_CHIP_SANDYBRIDGE_S)
315
316#define IS_GEN7(devid)		(IS_IVYBRIDGE(devid) || \
317				 IS_HASWELL(devid) || \
318				 IS_VALLEYVIEW(devid))
319
320#define IS_IVYBRIDGE(devid)	((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
321				 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
322				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
323				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
324				 (devid) == PCI_CHIP_IVYBRIDGE_S || \
325				 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
326
327#define IS_VALLEYVIEW(devid)	((devid) == PCI_CHIP_VALLEYVIEW_PO || \
328				 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
329				 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
330				 (devid) == PCI_CHIP_VALLEYVIEW_3)
331
332#define IS_HSW_GT1(devid)	((devid) == PCI_CHIP_HASWELL_GT1 || \
333				 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
334				 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
335				 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
336				 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
337				 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
338				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
339				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
340				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
341				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
342				 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
343				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
344				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
345				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
346				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
347				 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
348				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
349				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
350				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
351				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
352#define IS_HSW_GT2(devid)	((devid) == PCI_CHIP_HASWELL_GT2 || \
353				 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
354				 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
355				 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
356				 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
357				 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
358				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
359				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
360				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
361				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
362				 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
363				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
364				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
365				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
366				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
367				 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
368				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
369				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
370				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
371				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
372#define IS_HSW_GT3(devid)	((devid) == PCI_CHIP_HASWELL_GT3 || \
373				 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
374				 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
375				 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
376				 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
377				 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
378				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
379				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
380				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
381				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
382				 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
383				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
384				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
385				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
386				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
387				 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
388				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
389				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
390				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
391				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
392
393#define IS_HASWELL(devid)	(IS_HSW_GT1(devid) || \
394				 IS_HSW_GT2(devid) || \
395				 IS_HSW_GT3(devid))
396
397#define IS_BROADWELL(devid)     (((devid & 0xff00) != 0x1600) ? 0 : \
398				(((devid & 0x00f0) >> 4) > 3) ? 0 : \
399				((devid & 0x000f) == BDW_SPARE) ? 1 : \
400				((devid & 0x000f) == BDW_ULT) ? 1 : \
401				((devid & 0x000f) == BDW_IRIS) ? 1 : \
402				((devid & 0x000f) == BDW_SERVER) ? 1 : \
403				((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
404				((devid & 0x000f) == BDW_ULX) ? 1 : 0)
405
406#define IS_CHERRYVIEW(devid)	((devid) == PCI_CHIP_CHERRYVIEW_0 || \
407				 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
408				 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
409				 (devid) == PCI_CHIP_CHERRYVIEW_3)
410
411#define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
412				 IS_CHERRYVIEW(devid))
413
414#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
415				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
416				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1	|| \
417				 (devid) == PCI_CHIP_SKYLAKE_H_GT1	|| \
418				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1)
419
420#define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
421				 (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2	|| \
422				 (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2	|| \
423				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
424				 (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2	|| \
425				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
426				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
427				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2	|| \
428				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
429				 (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2)
430
431#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0	|| \
432				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1	|| \
433				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2	|| \
434				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
435				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
436
437#define IS_SKL_GT4(devid)	((devid) == PCI_CHIP_SKYLAKE_SRV_GT4	|| \
438				 (devid) == PCI_CHIP_SKYLAKE_DT_GT4	|| \
439				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X	|| \
440				 (devid) == PCI_CHIP_SKYLAKE_H_GT4	|| \
441				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT4)
442
443#define IS_KBL_GT1(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5	|| \
444				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5	|| \
445				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT1	|| \
446				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1	|| \
447				 (devid) == PCI_CHIP_KABYLAKE_DT_GT1	|| \
448				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \
449				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \
450				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
451
452#define IS_KBL_GT2(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT2	|| \
453				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F	|| \
454				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2	|| \
455				 (devid) == PCI_CHIP_KABYLAKE_DT_GT2	|| \
456				 (devid) == PCI_CHIP_KABYLAKE_M_GT2	|| \
457				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2	|| \
458				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2	|| \
459				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
460
461#define IS_KBL_GT3(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0	|| \
462				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1	|| \
463				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2)
464
465#define IS_KBL_GT4(devid)	((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
466
467#define IS_KABYLAKE(devid)	(IS_KBL_GT1(devid) || \
468				 IS_KBL_GT2(devid) || \
469				 IS_KBL_GT3(devid) || \
470				 IS_KBL_GT4(devid))
471
472#define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \
473				 IS_SKL_GT2(devid) || \
474				 IS_SKL_GT3(devid) || \
475				 IS_SKL_GT4(devid))
476
477#define IS_BROXTON(devid)	((devid) == PCI_CHIP_BROXTON_0	|| \
478				 (devid) == PCI_CHIP_BROXTON_1	|| \
479				 (devid) == PCI_CHIP_BROXTON_2	|| \
480				 (devid) == PCI_CHIP_BROXTON_3	|| \
481				 (devid) == PCI_CHIP_BROXTON_4)
482
483#define IS_GEMINILAKE(devid)	((devid) == PCI_CHIP_GLK || \
484				 (devid) == PCI_CHIP_GLK_2X6)
485
486#define IS_CFL_S(devid)         ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
487                                 (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
488                                 (devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \
489                                 (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
490                                 (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
491                                 (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \
492                                 (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4)
493
494#define IS_CFL_H(devid)         ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
495                                 (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
496
497#define IS_CFL_U(devid)         ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \
498                                 (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \
499                                 (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
500                                 (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \
501                                 (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \
502                                 (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
503                                 (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
504                                 (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
505                                 (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
506                                 (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5)
507
508#define IS_COFFEELAKE(devid)   (IS_CFL_S(devid) || \
509				IS_CFL_H(devid) || \
510				IS_CFL_U(devid))
511
512#define IS_GEN9(devid)		(IS_SKYLAKE(devid)  || \
513				 IS_BROXTON(devid)  || \
514				 IS_KABYLAKE(devid) || \
515				 IS_GEMINILAKE(devid) || \
516				 IS_COFFEELAKE(devid))
517
518#define IS_CNL_Y(devid)		((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
519				 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
520				 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
521				 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \
522				 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \
523				 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
524
525#define IS_CNL_U(devid)		((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
526				 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
527				 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
528				 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
529
530#define IS_CANNONLAKE(devid)	(IS_CNL_U(devid) || \
531				 IS_CNL_Y(devid))
532
533#define IS_GEN10(devid)		(IS_CANNONLAKE(devid))
534
535#define IS_9XX(dev)		(IS_GEN3(dev) || \
536				 IS_GEN4(dev) || \
537				 IS_GEN5(dev) || \
538				 IS_GEN6(dev) || \
539				 IS_GEN7(dev) || \
540				 IS_GEN8(dev) || \
541				 IS_GEN9(dev) || \
542				 IS_GEN10(dev))
543
544#endif /* _INTEL_CHIPSET_H */
545