1e88f27b3Smrg/* 2e88f27b3Smrg * Copyright 2012 Red Hat Inc. 3e88f27b3Smrg * 4e88f27b3Smrg * Permission is hereby granted, free of charge, to any person obtaining a 5e88f27b3Smrg * copy of this software and associated documentation files (the "Software"), 6e88f27b3Smrg * to deal in the Software without restriction, including without limitation 7e88f27b3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e88f27b3Smrg * and/or sell copies of the Software, and to permit persons to whom the 9e88f27b3Smrg * Software is furnished to do so, subject to the following conditions: 10e88f27b3Smrg * 11e88f27b3Smrg * The above copyright notice and this permission notice shall be included in 12e88f27b3Smrg * all copies or substantial portions of the Software. 13e88f27b3Smrg * 14e88f27b3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e88f27b3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e88f27b3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e88f27b3Smrg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e88f27b3Smrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e88f27b3Smrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e88f27b3Smrg * OTHER DEALINGS IN THE SOFTWARE. 21e88f27b3Smrg * 22e88f27b3Smrg * Authors: Ben Skeggs 23e88f27b3Smrg */ 24e88f27b3Smrg 25e88f27b3Smrg#include <stdlib.h> 26e88f27b3Smrg#include <stdint.h> 27e88f27b3Smrg#include <stddef.h> 283f012e29Smrg#include <errno.h> 29e88f27b3Smrg 30e88f27b3Smrg#include "private.h" 31e88f27b3Smrg 323f012e29Smrg#include "nvif/class.h" 33e88f27b3Smrg 343f012e29Smrgstatic int 35e88f27b3Smrgabi16_chan_nv04(struct nouveau_object *obj) 36e88f27b3Smrg{ 373f012e29Smrg struct nouveau_drm *drm = nouveau_drm(obj); 38e88f27b3Smrg struct nv04_fifo *nv04 = obj->data; 393f012e29Smrg struct drm_nouveau_channel_alloc req = { 403f012e29Smrg .fb_ctxdma_handle = nv04->vram, 413f012e29Smrg .tt_ctxdma_handle = nv04->gart 423f012e29Smrg }; 43e88f27b3Smrg int ret; 44e88f27b3Smrg 453f012e29Smrg ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC, 46e88f27b3Smrg &req, sizeof(req)); 47e88f27b3Smrg if (ret) 48e88f27b3Smrg return ret; 49e88f27b3Smrg 50e88f27b3Smrg nv04->base.channel = req.channel; 51e88f27b3Smrg nv04->base.pushbuf = req.pushbuf_domains; 52e88f27b3Smrg nv04->notify = req.notifier_handle; 53e88f27b3Smrg nv04->base.object->handle = req.channel; 54e88f27b3Smrg nv04->base.object->length = sizeof(*nv04); 55e88f27b3Smrg return 0; 56e88f27b3Smrg} 57e88f27b3Smrg 583f012e29Smrgstatic int 59e88f27b3Smrgabi16_chan_nvc0(struct nouveau_object *obj) 60e88f27b3Smrg{ 613f012e29Smrg struct nouveau_drm *drm = nouveau_drm(obj); 62e88f27b3Smrg struct drm_nouveau_channel_alloc req = {}; 63e88f27b3Smrg struct nvc0_fifo *nvc0 = obj->data; 64e88f27b3Smrg int ret; 65e88f27b3Smrg 663f012e29Smrg ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC, 67e88f27b3Smrg &req, sizeof(req)); 68e88f27b3Smrg if (ret) 69e88f27b3Smrg return ret; 70e88f27b3Smrg 71e88f27b3Smrg nvc0->base.channel = req.channel; 72e88f27b3Smrg nvc0->base.pushbuf = req.pushbuf_domains; 73e88f27b3Smrg nvc0->notify = req.notifier_handle; 74e88f27b3Smrg nvc0->base.object->handle = req.channel; 75e88f27b3Smrg nvc0->base.object->length = sizeof(*nvc0); 76e88f27b3Smrg return 0; 77e88f27b3Smrg} 78e88f27b3Smrg 793f012e29Smrgstatic int 80e88f27b3Smrgabi16_chan_nve0(struct nouveau_object *obj) 81e88f27b3Smrg{ 823f012e29Smrg struct nouveau_drm *drm = nouveau_drm(obj); 83e88f27b3Smrg struct drm_nouveau_channel_alloc req = {}; 84e88f27b3Smrg struct nve0_fifo *nve0 = obj->data; 85e88f27b3Smrg int ret; 86e88f27b3Smrg 87e88f27b3Smrg if (obj->length > offsetof(struct nve0_fifo, engine)) { 88e88f27b3Smrg req.fb_ctxdma_handle = 0xffffffff; 89e88f27b3Smrg req.tt_ctxdma_handle = nve0->engine; 90e88f27b3Smrg } 91e88f27b3Smrg 923f012e29Smrg ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_CHANNEL_ALLOC, 93e88f27b3Smrg &req, sizeof(req)); 94e88f27b3Smrg if (ret) 95e88f27b3Smrg return ret; 96e88f27b3Smrg 97e88f27b3Smrg nve0->base.channel = req.channel; 98e88f27b3Smrg nve0->base.pushbuf = req.pushbuf_domains; 99e88f27b3Smrg nve0->notify = req.notifier_handle; 100e88f27b3Smrg nve0->base.object->handle = req.channel; 101e88f27b3Smrg nve0->base.object->length = sizeof(*nve0); 102e88f27b3Smrg return 0; 103e88f27b3Smrg} 104e88f27b3Smrg 1053f012e29Smrgstatic int 106e88f27b3Smrgabi16_engobj(struct nouveau_object *obj) 107e88f27b3Smrg{ 1083f012e29Smrg struct nouveau_drm *drm = nouveau_drm(obj); 109e88f27b3Smrg struct drm_nouveau_grobj_alloc req = { 1103f012e29Smrg .channel = obj->parent->handle, 1113f012e29Smrg .handle = obj->handle, 1123f012e29Smrg .class = obj->oclass, 113e88f27b3Smrg }; 114e88f27b3Smrg int ret; 115e88f27b3Smrg 1163f012e29Smrg /* Older kernel versions did not have the concept of nouveau- 1173f012e29Smrg * specific classes and abused some NVIDIA-assigned ones for 1183f012e29Smrg * a SW class. The ABI16 layer has compatibility in place to 1193f012e29Smrg * translate these older identifiers to the newer ones. 1203f012e29Smrg * 1213f012e29Smrg * Clients that have been updated to use NVIF are required to 1223f012e29Smrg * use the newer class identifiers, which means that they'll 1233f012e29Smrg * break if running on an older kernel. 1243f012e29Smrg * 1253f012e29Smrg * To handle this case, when using ABI16, we translate to the 1263f012e29Smrg * older values which work on any kernel. 1273f012e29Smrg */ 1283f012e29Smrg switch (req.class) { 1293f012e29Smrg case NVIF_CLASS_SW_NV04 : req.class = 0x006e; break; 1303f012e29Smrg case NVIF_CLASS_SW_NV10 : req.class = 0x016e; break; 1313f012e29Smrg case NVIF_CLASS_SW_NV50 : req.class = 0x506e; break; 1323f012e29Smrg case NVIF_CLASS_SW_GF100: req.class = 0x906e; break; 1333f012e29Smrg default: 1343f012e29Smrg break; 1353f012e29Smrg } 1363f012e29Smrg 1373f012e29Smrg ret = drmCommandWrite(drm->fd, DRM_NOUVEAU_GROBJ_ALLOC, 138e88f27b3Smrg &req, sizeof(req)); 139e88f27b3Smrg if (ret) 140e88f27b3Smrg return ret; 141e88f27b3Smrg 142e88f27b3Smrg obj->length = sizeof(struct nouveau_object *); 143e88f27b3Smrg return 0; 144e88f27b3Smrg} 145e88f27b3Smrg 1463f012e29Smrgstatic int 147e88f27b3Smrgabi16_ntfy(struct nouveau_object *obj) 148e88f27b3Smrg{ 1493f012e29Smrg struct nouveau_drm *drm = nouveau_drm(obj); 150e88f27b3Smrg struct nv04_notify *ntfy = obj->data; 151e88f27b3Smrg struct drm_nouveau_notifierobj_alloc req = { 1523f012e29Smrg .channel = obj->parent->handle, 1533f012e29Smrg .handle = ntfy->object->handle, 1543f012e29Smrg .size = ntfy->length, 155e88f27b3Smrg }; 156e88f27b3Smrg int ret; 157e88f27b3Smrg 1583f012e29Smrg ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, 159e88f27b3Smrg &req, sizeof(req)); 160e88f27b3Smrg if (ret) 161e88f27b3Smrg return ret; 162e88f27b3Smrg 163e88f27b3Smrg ntfy->offset = req.offset; 164e88f27b3Smrg ntfy->object->length = sizeof(*ntfy); 165e88f27b3Smrg return 0; 166e88f27b3Smrg} 167e88f27b3Smrg 1683f012e29Smrgdrm_private int 1693f012e29Smrgabi16_sclass(struct nouveau_object *obj, struct nouveau_sclass **psclass) 1703f012e29Smrg{ 1713f012e29Smrg struct nouveau_sclass *sclass; 1723f012e29Smrg struct nouveau_device *dev; 1733f012e29Smrg 1743f012e29Smrg if (!(sclass = calloc(8, sizeof(*sclass)))) 1753f012e29Smrg return -ENOMEM; 1763f012e29Smrg *psclass = sclass; 1773f012e29Smrg 1783f012e29Smrg switch (obj->oclass) { 1793f012e29Smrg case NOUVEAU_FIFO_CHANNEL_CLASS: 1803f012e29Smrg /* Older kernel versions were exposing the wrong video engine 1813f012e29Smrg * classes on certain G98:GF100 boards. This has since been 1823f012e29Smrg * corrected, but ABI16 has compatibility in place to avoid 1833f012e29Smrg * breaking older userspace. 1843f012e29Smrg * 1853f012e29Smrg * Clients that have been updated to use NVIF are required to 1863f012e29Smrg * use the correct classes, which means that they'll break if 1873f012e29Smrg * running on an older kernel. 1883f012e29Smrg * 1893f012e29Smrg * To handle this issue, if using the older kernel interfaces, 1903f012e29Smrg * we'll magic up a list containing the vdec classes that the 1913f012e29Smrg * kernel will accept for these boards. Clients should make 1923f012e29Smrg * use of this information instead of hardcoding classes for 1933f012e29Smrg * specific chipsets. 1943f012e29Smrg */ 1953f012e29Smrg dev = (struct nouveau_device *)obj->parent; 1963f012e29Smrg if (dev->chipset >= 0x98 && 1973f012e29Smrg dev->chipset != 0xa0 && 1983f012e29Smrg dev->chipset < 0xc0) { 1993f012e29Smrg *sclass++ = (struct nouveau_sclass){ 2003f012e29Smrg GT212_MSVLD, -1, -1 2013f012e29Smrg }; 2023f012e29Smrg *sclass++ = (struct nouveau_sclass){ 2033f012e29Smrg GT212_MSPDEC, -1, -1 2043f012e29Smrg }; 2053f012e29Smrg *sclass++ = (struct nouveau_sclass){ 2063f012e29Smrg GT212_MSPPP, -1, -1 2073f012e29Smrg }; 2083f012e29Smrg } 2093f012e29Smrg break; 2103f012e29Smrg default: 2113f012e29Smrg break; 2123f012e29Smrg } 2133f012e29Smrg 2143f012e29Smrg return sclass - *psclass; 2153f012e29Smrg} 2163f012e29Smrg 2173f012e29Smrgdrm_private void 2183f012e29Smrgabi16_delete(struct nouveau_object *obj) 2193f012e29Smrg{ 2203f012e29Smrg struct nouveau_drm *drm = nouveau_drm(obj); 2213f012e29Smrg if (obj->oclass == NOUVEAU_FIFO_CHANNEL_CLASS) { 2223f012e29Smrg struct drm_nouveau_channel_free req; 2233f012e29Smrg req.channel = obj->handle; 2243f012e29Smrg drmCommandWrite(drm->fd, DRM_NOUVEAU_CHANNEL_FREE, 2253f012e29Smrg &req, sizeof(req)); 2263f012e29Smrg } else { 2273f012e29Smrg struct drm_nouveau_gpuobj_free req; 2283f012e29Smrg req.channel = obj->parent->handle; 2293f012e29Smrg req.handle = obj->handle; 2303f012e29Smrg drmCommandWrite(drm->fd, DRM_NOUVEAU_GPUOBJ_FREE, 2313f012e29Smrg &req, sizeof(req)); 2323f012e29Smrg } 2333f012e29Smrg} 2343f012e29Smrg 2353f012e29Smrgdrm_private bool 2363f012e29Smrgabi16_object(struct nouveau_object *obj, int (**func)(struct nouveau_object *)) 2373f012e29Smrg{ 2383f012e29Smrg struct nouveau_object *parent = obj->parent; 2393f012e29Smrg 2403f012e29Smrg /* nouveau_object::length is (ab)used to determine whether the 2413f012e29Smrg * object is a legacy object (!=0), or a real NVIF object. 2423f012e29Smrg */ 2433f012e29Smrg if ((parent->length != 0 && parent->oclass == NOUVEAU_DEVICE_CLASS) || 2443f012e29Smrg (parent->length == 0 && parent->oclass == NV_DEVICE)) { 2453f012e29Smrg if (obj->oclass == NOUVEAU_FIFO_CHANNEL_CLASS) { 2463f012e29Smrg struct nouveau_device *dev = (void *)parent; 2473f012e29Smrg if (dev->chipset < 0xc0) 2483f012e29Smrg *func = abi16_chan_nv04; 2493f012e29Smrg else 2503f012e29Smrg if (dev->chipset < 0xe0) 2513f012e29Smrg *func = abi16_chan_nvc0; 2523f012e29Smrg else 2533f012e29Smrg *func = abi16_chan_nve0; 2543f012e29Smrg return true; 2553f012e29Smrg } 2563f012e29Smrg } else 2573f012e29Smrg if ((parent->length != 0 && 2583f012e29Smrg parent->oclass == NOUVEAU_FIFO_CHANNEL_CLASS)) { 2593f012e29Smrg if (obj->oclass == NOUVEAU_NOTIFIER_CLASS) { 2603f012e29Smrg *func = abi16_ntfy; 2613f012e29Smrg return true; 2623f012e29Smrg } 2633f012e29Smrg 2643f012e29Smrg *func = abi16_engobj; 2653f012e29Smrg return false; /* try NVIF, if supported, before calling func */ 2663f012e29Smrg } 2673f012e29Smrg 2683f012e29Smrg *func = NULL; 2693f012e29Smrg return false; 2703f012e29Smrg} 2713f012e29Smrg 272e6188e58Smrgdrm_private void 273e88f27b3Smrgabi16_bo_info(struct nouveau_bo *bo, struct drm_nouveau_gem_info *info) 274e88f27b3Smrg{ 275e88f27b3Smrg struct nouveau_bo_priv *nvbo = nouveau_bo(bo); 276e88f27b3Smrg 277e88f27b3Smrg nvbo->map_handle = info->map_handle; 278e88f27b3Smrg bo->handle = info->handle; 279e88f27b3Smrg bo->size = info->size; 280e88f27b3Smrg bo->offset = info->offset; 281e88f27b3Smrg 282e88f27b3Smrg bo->flags = 0; 283e88f27b3Smrg if (info->domain & NOUVEAU_GEM_DOMAIN_VRAM) 284e88f27b3Smrg bo->flags |= NOUVEAU_BO_VRAM; 285e88f27b3Smrg if (info->domain & NOUVEAU_GEM_DOMAIN_GART) 286e88f27b3Smrg bo->flags |= NOUVEAU_BO_GART; 287e88f27b3Smrg if (!(info->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)) 288e88f27b3Smrg bo->flags |= NOUVEAU_BO_CONTIG; 289e88f27b3Smrg if (nvbo->map_handle) 290e88f27b3Smrg bo->flags |= NOUVEAU_BO_MAP; 291e88f27b3Smrg 292e88f27b3Smrg if (bo->device->chipset >= 0xc0) { 293e88f27b3Smrg bo->config.nvc0.memtype = (info->tile_flags & 0xff00) >> 8; 294e88f27b3Smrg bo->config.nvc0.tile_mode = info->tile_mode; 295e88f27b3Smrg } else 296e88f27b3Smrg if (bo->device->chipset >= 0x80 || bo->device->chipset == 0x50) { 297e88f27b3Smrg bo->config.nv50.memtype = (info->tile_flags & 0x07f00) >> 8 | 298e88f27b3Smrg (info->tile_flags & 0x30000) >> 9; 299e88f27b3Smrg bo->config.nv50.tile_mode = info->tile_mode << 4; 300e88f27b3Smrg } else { 301e88f27b3Smrg bo->config.nv04.surf_flags = info->tile_flags & 7; 302e88f27b3Smrg bo->config.nv04.surf_pitch = info->tile_mode; 303e88f27b3Smrg } 304e88f27b3Smrg} 305e88f27b3Smrg 306e6188e58Smrgdrm_private int 307e88f27b3Smrgabi16_bo_init(struct nouveau_bo *bo, uint32_t alignment, 308e88f27b3Smrg union nouveau_bo_config *config) 309e88f27b3Smrg{ 310e88f27b3Smrg struct nouveau_device *dev = bo->device; 3113f012e29Smrg struct nouveau_drm *drm = nouveau_drm(&dev->object); 312e88f27b3Smrg struct drm_nouveau_gem_new req = {}; 313e88f27b3Smrg struct drm_nouveau_gem_info *info = &req.info; 314e88f27b3Smrg int ret; 315e88f27b3Smrg 316e88f27b3Smrg if (bo->flags & NOUVEAU_BO_VRAM) 317e88f27b3Smrg info->domain |= NOUVEAU_GEM_DOMAIN_VRAM; 318e88f27b3Smrg if (bo->flags & NOUVEAU_BO_GART) 319e88f27b3Smrg info->domain |= NOUVEAU_GEM_DOMAIN_GART; 320e88f27b3Smrg if (!info->domain) 321e88f27b3Smrg info->domain |= NOUVEAU_GEM_DOMAIN_VRAM | 322e88f27b3Smrg NOUVEAU_GEM_DOMAIN_GART; 323e88f27b3Smrg 324e88f27b3Smrg if (bo->flags & NOUVEAU_BO_MAP) 325e88f27b3Smrg info->domain |= NOUVEAU_GEM_DOMAIN_MAPPABLE; 326e88f27b3Smrg 327e6188e58Smrg if (bo->flags & NOUVEAU_BO_COHERENT) 328e6188e58Smrg info->domain |= NOUVEAU_GEM_DOMAIN_COHERENT; 329e6188e58Smrg 330e88f27b3Smrg if (!(bo->flags & NOUVEAU_BO_CONTIG)) 331e88f27b3Smrg info->tile_flags = NOUVEAU_GEM_TILE_NONCONTIG; 332e88f27b3Smrg 333e88f27b3Smrg info->size = bo->size; 334e88f27b3Smrg req.align = alignment; 335e88f27b3Smrg 336e88f27b3Smrg if (config) { 337e88f27b3Smrg if (dev->chipset >= 0xc0) { 338e88f27b3Smrg info->tile_flags = (config->nvc0.memtype & 0xff) << 8; 339e88f27b3Smrg info->tile_mode = config->nvc0.tile_mode; 340e88f27b3Smrg } else 341e88f27b3Smrg if (dev->chipset >= 0x80 || dev->chipset == 0x50) { 342e88f27b3Smrg info->tile_flags = (config->nv50.memtype & 0x07f) << 8 | 343e88f27b3Smrg (config->nv50.memtype & 0x180) << 9; 344e88f27b3Smrg info->tile_mode = config->nv50.tile_mode >> 4; 345e88f27b3Smrg } else { 346e88f27b3Smrg info->tile_flags = config->nv04.surf_flags & 7; 347e88f27b3Smrg info->tile_mode = config->nv04.surf_pitch; 348e88f27b3Smrg } 349e88f27b3Smrg } 350e88f27b3Smrg 351e88f27b3Smrg if (!nouveau_device(dev)->have_bo_usage) 352e88f27b3Smrg info->tile_flags &= 0x0000ff00; 353e88f27b3Smrg 3543f012e29Smrg ret = drmCommandWriteRead(drm->fd, DRM_NOUVEAU_GEM_NEW, 355e88f27b3Smrg &req, sizeof(req)); 356e88f27b3Smrg if (ret == 0) 357e88f27b3Smrg abi16_bo_info(bo, &req.info); 358e88f27b3Smrg return ret; 359e88f27b3Smrg} 360