abi16.c revision baaff307
1e88f27b3Smrg/*
2e88f27b3Smrg * Copyright 2012 Red Hat Inc.
3e88f27b3Smrg *
4e88f27b3Smrg * Permission is hereby granted, free of charge, to any person obtaining a
5e88f27b3Smrg * copy of this software and associated documentation files (the "Software"),
6e88f27b3Smrg * to deal in the Software without restriction, including without limitation
7e88f27b3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e88f27b3Smrg * and/or sell copies of the Software, and to permit persons to whom the
9e88f27b3Smrg * Software is furnished to do so, subject to the following conditions:
10e88f27b3Smrg *
11e88f27b3Smrg * The above copyright notice and this permission notice shall be included in
12e88f27b3Smrg * all copies or substantial portions of the Software.
13e88f27b3Smrg *
14e88f27b3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e88f27b3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e88f27b3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17e88f27b3Smrg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e88f27b3Smrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e88f27b3Smrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e88f27b3Smrg * OTHER DEALINGS IN THE SOFTWARE.
21e88f27b3Smrg *
22e88f27b3Smrg * Authors: Ben Skeggs
23e88f27b3Smrg */
24e88f27b3Smrg
25baaff307Smrg#ifdef HAVE_CONFIG_H
26baaff307Smrg# include <config.h>
27baaff307Smrg#endif
28baaff307Smrg
29e88f27b3Smrg#include <stdlib.h>
30e88f27b3Smrg#include <stdint.h>
31e88f27b3Smrg#include <stddef.h>
32e88f27b3Smrg
33e88f27b3Smrg#include "private.h"
34e88f27b3Smrg
35e88f27b3Smrg
36e88f27b3Smrgint
37e88f27b3Smrgabi16_chan_nv04(struct nouveau_object *obj)
38e88f27b3Smrg{
39e88f27b3Smrg	struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
40e88f27b3Smrg	struct nv04_fifo *nv04 = obj->data;
41e88f27b3Smrg	struct drm_nouveau_channel_alloc req = {nv04->vram, nv04->gart};
42e88f27b3Smrg	int ret;
43e88f27b3Smrg
44e88f27b3Smrg	ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
45e88f27b3Smrg				  &req, sizeof(req));
46e88f27b3Smrg	if (ret)
47e88f27b3Smrg		return ret;
48e88f27b3Smrg
49e88f27b3Smrg	nv04->base.channel = req.channel;
50e88f27b3Smrg	nv04->base.pushbuf = req.pushbuf_domains;
51e88f27b3Smrg	nv04->notify = req.notifier_handle;
52e88f27b3Smrg	nv04->base.object->handle = req.channel;
53e88f27b3Smrg	nv04->base.object->length = sizeof(*nv04);
54e88f27b3Smrg	return 0;
55e88f27b3Smrg}
56e88f27b3Smrg
57e88f27b3Smrgint
58e88f27b3Smrgabi16_chan_nvc0(struct nouveau_object *obj)
59e88f27b3Smrg{
60e88f27b3Smrg	struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
61e88f27b3Smrg	struct drm_nouveau_channel_alloc req = {};
62e88f27b3Smrg	struct nvc0_fifo *nvc0 = obj->data;
63e88f27b3Smrg	int ret;
64e88f27b3Smrg
65e88f27b3Smrg	ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
66e88f27b3Smrg				  &req, sizeof(req));
67e88f27b3Smrg	if (ret)
68e88f27b3Smrg		return ret;
69e88f27b3Smrg
70e88f27b3Smrg	nvc0->base.channel = req.channel;
71e88f27b3Smrg	nvc0->base.pushbuf = req.pushbuf_domains;
72e88f27b3Smrg	nvc0->notify = req.notifier_handle;
73e88f27b3Smrg	nvc0->base.object->handle = req.channel;
74e88f27b3Smrg	nvc0->base.object->length = sizeof(*nvc0);
75e88f27b3Smrg	return 0;
76e88f27b3Smrg}
77e88f27b3Smrg
78e88f27b3Smrgint
79e88f27b3Smrgabi16_chan_nve0(struct nouveau_object *obj)
80e88f27b3Smrg{
81e88f27b3Smrg	struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
82e88f27b3Smrg	struct drm_nouveau_channel_alloc req = {};
83e88f27b3Smrg	struct nve0_fifo *nve0 = obj->data;
84e88f27b3Smrg	int ret;
85e88f27b3Smrg
86e88f27b3Smrg	if (obj->length > offsetof(struct nve0_fifo, engine)) {
87e88f27b3Smrg		req.fb_ctxdma_handle = 0xffffffff;
88e88f27b3Smrg		req.tt_ctxdma_handle = nve0->engine;
89e88f27b3Smrg	}
90e88f27b3Smrg
91e88f27b3Smrg	ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
92e88f27b3Smrg				  &req, sizeof(req));
93e88f27b3Smrg	if (ret)
94e88f27b3Smrg		return ret;
95e88f27b3Smrg
96e88f27b3Smrg	nve0->base.channel = req.channel;
97e88f27b3Smrg	nve0->base.pushbuf = req.pushbuf_domains;
98e88f27b3Smrg	nve0->notify = req.notifier_handle;
99e88f27b3Smrg	nve0->base.object->handle = req.channel;
100e88f27b3Smrg	nve0->base.object->length = sizeof(*nve0);
101e88f27b3Smrg	return 0;
102e88f27b3Smrg}
103e88f27b3Smrg
104e88f27b3Smrgint
105e88f27b3Smrgabi16_engobj(struct nouveau_object *obj)
106e88f27b3Smrg{
107e88f27b3Smrg	struct drm_nouveau_grobj_alloc req = {
108e88f27b3Smrg		obj->parent->handle, obj->handle, obj->oclass
109e88f27b3Smrg	};
110e88f27b3Smrg	struct nouveau_device *dev;
111e88f27b3Smrg	int ret;
112e88f27b3Smrg
113e88f27b3Smrg	dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS);
114e88f27b3Smrg	ret = drmCommandWrite(dev->fd, DRM_NOUVEAU_GROBJ_ALLOC,
115e88f27b3Smrg			      &req, sizeof(req));
116e88f27b3Smrg	if (ret)
117e88f27b3Smrg		return ret;
118e88f27b3Smrg
119e88f27b3Smrg	obj->length = sizeof(struct nouveau_object *);
120e88f27b3Smrg	return 0;
121e88f27b3Smrg}
122e88f27b3Smrg
123e88f27b3Smrgint
124e88f27b3Smrgabi16_ntfy(struct nouveau_object *obj)
125e88f27b3Smrg{
126e88f27b3Smrg	struct nv04_notify *ntfy = obj->data;
127e88f27b3Smrg	struct drm_nouveau_notifierobj_alloc req = {
128e88f27b3Smrg		obj->parent->handle, ntfy->object->handle, ntfy->length
129e88f27b3Smrg	};
130e88f27b3Smrg	struct nouveau_device *dev;
131e88f27b3Smrg	int ret;
132e88f27b3Smrg
133e88f27b3Smrg	dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS);
134e88f27b3Smrg	ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC,
135e88f27b3Smrg				  &req, sizeof(req));
136e88f27b3Smrg	if (ret)
137e88f27b3Smrg		return ret;
138e88f27b3Smrg
139e88f27b3Smrg	ntfy->offset = req.offset;
140e88f27b3Smrg	ntfy->object->length = sizeof(*ntfy);
141e88f27b3Smrg	return 0;
142e88f27b3Smrg}
143e88f27b3Smrg
144e88f27b3Smrgvoid
145e88f27b3Smrgabi16_bo_info(struct nouveau_bo *bo, struct drm_nouveau_gem_info *info)
146e88f27b3Smrg{
147e88f27b3Smrg	struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
148e88f27b3Smrg
149e88f27b3Smrg	nvbo->map_handle = info->map_handle;
150e88f27b3Smrg	bo->handle = info->handle;
151e88f27b3Smrg	bo->size = info->size;
152e88f27b3Smrg	bo->offset = info->offset;
153e88f27b3Smrg
154e88f27b3Smrg	bo->flags = 0;
155e88f27b3Smrg	if (info->domain & NOUVEAU_GEM_DOMAIN_VRAM)
156e88f27b3Smrg		bo->flags |= NOUVEAU_BO_VRAM;
157e88f27b3Smrg	if (info->domain & NOUVEAU_GEM_DOMAIN_GART)
158e88f27b3Smrg		bo->flags |= NOUVEAU_BO_GART;
159e88f27b3Smrg	if (!(info->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG))
160e88f27b3Smrg		bo->flags |= NOUVEAU_BO_CONTIG;
161e88f27b3Smrg	if (nvbo->map_handle)
162e88f27b3Smrg		bo->flags |= NOUVEAU_BO_MAP;
163e88f27b3Smrg
164e88f27b3Smrg	if (bo->device->chipset >= 0xc0) {
165e88f27b3Smrg		bo->config.nvc0.memtype   = (info->tile_flags & 0xff00) >> 8;
166e88f27b3Smrg		bo->config.nvc0.tile_mode = info->tile_mode;
167e88f27b3Smrg	} else
168e88f27b3Smrg	if (bo->device->chipset >= 0x80 || bo->device->chipset == 0x50) {
169e88f27b3Smrg		bo->config.nv50.memtype   = (info->tile_flags & 0x07f00) >> 8 |
170e88f27b3Smrg					    (info->tile_flags & 0x30000) >> 9;
171e88f27b3Smrg		bo->config.nv50.tile_mode = info->tile_mode << 4;
172e88f27b3Smrg	} else {
173e88f27b3Smrg		bo->config.nv04.surf_flags = info->tile_flags & 7;
174e88f27b3Smrg		bo->config.nv04.surf_pitch = info->tile_mode;
175e88f27b3Smrg	}
176e88f27b3Smrg}
177e88f27b3Smrg
178e88f27b3Smrgint
179e88f27b3Smrgabi16_bo_init(struct nouveau_bo *bo, uint32_t alignment,
180e88f27b3Smrg	      union nouveau_bo_config *config)
181e88f27b3Smrg{
182e88f27b3Smrg	struct nouveau_device *dev = bo->device;
183e88f27b3Smrg	struct drm_nouveau_gem_new req = {};
184e88f27b3Smrg	struct drm_nouveau_gem_info *info = &req.info;
185e88f27b3Smrg	int ret;
186e88f27b3Smrg
187e88f27b3Smrg	if (bo->flags & NOUVEAU_BO_VRAM)
188e88f27b3Smrg		info->domain |= NOUVEAU_GEM_DOMAIN_VRAM;
189e88f27b3Smrg	if (bo->flags & NOUVEAU_BO_GART)
190e88f27b3Smrg		info->domain |= NOUVEAU_GEM_DOMAIN_GART;
191e88f27b3Smrg	if (!info->domain)
192e88f27b3Smrg		info->domain |= NOUVEAU_GEM_DOMAIN_VRAM |
193e88f27b3Smrg				NOUVEAU_GEM_DOMAIN_GART;
194e88f27b3Smrg
195e88f27b3Smrg	if (bo->flags & NOUVEAU_BO_MAP)
196e88f27b3Smrg		info->domain |= NOUVEAU_GEM_DOMAIN_MAPPABLE;
197e88f27b3Smrg
198e88f27b3Smrg	if (!(bo->flags & NOUVEAU_BO_CONTIG))
199e88f27b3Smrg		info->tile_flags = NOUVEAU_GEM_TILE_NONCONTIG;
200e88f27b3Smrg
201e88f27b3Smrg	info->size = bo->size;
202e88f27b3Smrg	req.align = alignment;
203e88f27b3Smrg
204e88f27b3Smrg	if (config) {
205e88f27b3Smrg		if (dev->chipset >= 0xc0) {
206e88f27b3Smrg			info->tile_flags = (config->nvc0.memtype & 0xff) << 8;
207e88f27b3Smrg			info->tile_mode  = config->nvc0.tile_mode;
208e88f27b3Smrg		} else
209e88f27b3Smrg		if (dev->chipset >= 0x80 || dev->chipset == 0x50) {
210e88f27b3Smrg			info->tile_flags = (config->nv50.memtype & 0x07f) << 8 |
211e88f27b3Smrg					   (config->nv50.memtype & 0x180) << 9;
212e88f27b3Smrg			info->tile_mode  = config->nv50.tile_mode >> 4;
213e88f27b3Smrg		} else {
214e88f27b3Smrg			info->tile_flags = config->nv04.surf_flags & 7;
215e88f27b3Smrg			info->tile_mode  = config->nv04.surf_pitch;
216e88f27b3Smrg		}
217e88f27b3Smrg	}
218e88f27b3Smrg
219e88f27b3Smrg	if (!nouveau_device(dev)->have_bo_usage)
220e88f27b3Smrg		info->tile_flags &= 0x0000ff00;
221e88f27b3Smrg
222e88f27b3Smrg	ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_GEM_NEW,
223e88f27b3Smrg				  &req, sizeof(req));
224e88f27b3Smrg	if (ret == 0)
225e88f27b3Smrg		abi16_bo_info(bo, &req.info);
226e88f27b3Smrg	return ret;
227e88f27b3Smrg}
228