vce_tests.c revision d8807b2f
1/* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22*/ 23 24#ifdef HAVE_CONFIG_H 25#include "config.h" 26#endif 27 28#include <stdio.h> 29#include <inttypes.h> 30 31#include "CUnit/Basic.h" 32 33#include "util_math.h" 34 35#include "amdgpu_test.h" 36#include "amdgpu_drm.h" 37#include "amdgpu_internal.h" 38 39#include "vce_ib.h" 40#include "frame.h" 41 42#define IB_SIZE 4096 43#define MAX_RESOURCES 16 44 45struct amdgpu_vce_bo { 46 amdgpu_bo_handle handle; 47 amdgpu_va_handle va_handle; 48 uint64_t addr; 49 uint64_t size; 50 uint8_t *ptr; 51}; 52 53struct amdgpu_vce_encode { 54 unsigned width; 55 unsigned height; 56 struct amdgpu_vce_bo vbuf; 57 struct amdgpu_vce_bo bs[2]; 58 struct amdgpu_vce_bo fb[2]; 59 struct amdgpu_vce_bo cpb; 60 unsigned ib_len; 61 bool two_instance; 62}; 63 64static amdgpu_device_handle device_handle; 65static uint32_t major_version; 66static uint32_t minor_version; 67static uint32_t family_id; 68static uint32_t vce_harvest_config; 69 70static amdgpu_context_handle context_handle; 71static amdgpu_bo_handle ib_handle; 72static amdgpu_va_handle ib_va_handle; 73static uint64_t ib_mc_address; 74static uint32_t *ib_cpu; 75 76static struct amdgpu_vce_encode enc; 77static amdgpu_bo_handle resources[MAX_RESOURCES]; 78static unsigned num_resources; 79 80static void amdgpu_cs_vce_create(void); 81static void amdgpu_cs_vce_encode(void); 82static void amdgpu_cs_vce_destroy(void); 83 84CU_TestInfo vce_tests[] = { 85 { "VCE create", amdgpu_cs_vce_create }, 86 { "VCE encode", amdgpu_cs_vce_encode }, 87 { "VCE destroy", amdgpu_cs_vce_destroy }, 88 CU_TEST_INFO_NULL, 89}; 90 91int suite_vce_tests_init(void) 92{ 93 int r; 94 95 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, 96 &minor_version, &device_handle); 97 if (r) { 98 if ((r == -EACCES) && (errno == EACCES)) 99 printf("\n\nError:%s. " 100 "Hint:Try to run this test program as root.", 101 strerror(errno)); 102 103 return CUE_SINIT_FAILED; 104 } 105 106 family_id = device_handle->info.family_id; 107 vce_harvest_config = device_handle->info.vce_harvest_config; 108 109 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { 110 printf("\n\nThe ASIC NOT support VCE, all sub-tests will pass\n"); 111 return CUE_SUCCESS; 112 } 113 114 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 115 if (r) 116 return CUE_SINIT_FAILED; 117 118 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, 119 AMDGPU_GEM_DOMAIN_GTT, 0, 120 &ib_handle, (void**)&ib_cpu, 121 &ib_mc_address, &ib_va_handle); 122 if (r) 123 return CUE_SINIT_FAILED; 124 125 memset(&enc, 0, sizeof(struct amdgpu_vce_encode)); 126 127 return CUE_SUCCESS; 128} 129 130int suite_vce_tests_clean(void) 131{ 132 int r; 133 134 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { 135 r = amdgpu_device_deinitialize(device_handle); 136 if (r) 137 return CUE_SCLEAN_FAILED; 138 } else { 139 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, 140 ib_mc_address, IB_SIZE); 141 if (r) 142 return CUE_SCLEAN_FAILED; 143 144 r = amdgpu_cs_ctx_free(context_handle); 145 if (r) 146 return CUE_SCLEAN_FAILED; 147 148 r = amdgpu_device_deinitialize(device_handle); 149 if (r) 150 return CUE_SCLEAN_FAILED; 151 } 152 153 return CUE_SUCCESS; 154} 155 156static int submit(unsigned ndw, unsigned ip) 157{ 158 struct amdgpu_cs_request ibs_request = {0}; 159 struct amdgpu_cs_ib_info ib_info = {0}; 160 struct amdgpu_cs_fence fence_status = {0}; 161 uint32_t expired; 162 int r; 163 164 ib_info.ib_mc_address = ib_mc_address; 165 ib_info.size = ndw; 166 167 ibs_request.ip_type = ip; 168 169 r = amdgpu_bo_list_create(device_handle, num_resources, resources, 170 NULL, &ibs_request.resources); 171 if (r) 172 return r; 173 174 ibs_request.number_of_ibs = 1; 175 ibs_request.ibs = &ib_info; 176 ibs_request.fence_info.handle = NULL; 177 178 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); 179 if (r) 180 return r; 181 182 r = amdgpu_bo_list_destroy(ibs_request.resources); 183 if (r) 184 return r; 185 186 fence_status.context = context_handle; 187 fence_status.ip_type = ip; 188 fence_status.fence = ibs_request.seq_no; 189 190 r = amdgpu_cs_query_fence_status(&fence_status, 191 AMDGPU_TIMEOUT_INFINITE, 192 0, &expired); 193 if (r) 194 return r; 195 196 return 0; 197} 198 199static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned size, unsigned domain) 200{ 201 struct amdgpu_bo_alloc_request req = {0}; 202 amdgpu_bo_handle buf_handle; 203 amdgpu_va_handle va_handle; 204 uint64_t va = 0; 205 int r; 206 207 req.alloc_size = ALIGN(size, 4096); 208 req.preferred_heap = domain; 209 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); 210 CU_ASSERT_EQUAL(r, 0); 211 r = amdgpu_va_range_alloc(device_handle, 212 amdgpu_gpu_va_range_general, 213 req.alloc_size, 1, 0, &va, 214 &va_handle, 0); 215 CU_ASSERT_EQUAL(r, 0); 216 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, 217 AMDGPU_VA_OP_MAP); 218 CU_ASSERT_EQUAL(r, 0); 219 vce_bo->addr = va; 220 vce_bo->handle = buf_handle; 221 vce_bo->size = req.alloc_size; 222 vce_bo->va_handle = va_handle; 223 r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr); 224 CU_ASSERT_EQUAL(r, 0); 225 memset(vce_bo->ptr, 0, size); 226 r = amdgpu_bo_cpu_unmap(vce_bo->handle); 227 CU_ASSERT_EQUAL(r, 0); 228} 229 230static void free_resource(struct amdgpu_vce_bo *vce_bo) 231{ 232 int r; 233 234 r = amdgpu_bo_va_op(vce_bo->handle, 0, vce_bo->size, 235 vce_bo->addr, 0, AMDGPU_VA_OP_UNMAP); 236 CU_ASSERT_EQUAL(r, 0); 237 238 r = amdgpu_va_range_free(vce_bo->va_handle); 239 CU_ASSERT_EQUAL(r, 0); 240 241 r = amdgpu_bo_free(vce_bo->handle); 242 CU_ASSERT_EQUAL(r, 0); 243 memset(vce_bo, 0, sizeof(*vce_bo)); 244} 245 246static void amdgpu_cs_vce_create(void) 247{ 248 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; 249 int len, r; 250 251 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) 252 return; 253 254 enc.width = vce_create[6]; 255 enc.height = vce_create[7]; 256 257 num_resources = 0; 258 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 259 resources[num_resources++] = enc.fb[0].handle; 260 resources[num_resources++] = ib_handle; 261 262 len = 0; 263 memcpy(ib_cpu, vce_session, sizeof(vce_session)); 264 len += sizeof(vce_session) / 4; 265 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 266 len += sizeof(vce_taskinfo) / 4; 267 memcpy((ib_cpu + len), vce_create, sizeof(vce_create)); 268 ib_cpu[len + 8] = ALIGN(enc.width, align); 269 ib_cpu[len + 9] = ALIGN(enc.width, align); 270 len += sizeof(vce_create) / 4; 271 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 272 ib_cpu[len + 2] = enc.fb[0].addr >> 32; 273 ib_cpu[len + 3] = enc.fb[0].addr; 274 len += sizeof(vce_feedback) / 4; 275 276 r = submit(len, AMDGPU_HW_IP_VCE); 277 CU_ASSERT_EQUAL(r, 0); 278 279 free_resource(&enc.fb[0]); 280} 281 282static void amdgpu_cs_vce_config(void) 283{ 284 int len = 0, r; 285 286 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 287 len += sizeof(vce_session) / 4; 288 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 289 ib_cpu[len + 3] = 2; 290 ib_cpu[len + 6] = 0xffffffff; 291 len += sizeof(vce_taskinfo) / 4; 292 memcpy((ib_cpu + len), vce_rate_ctrl, sizeof(vce_rate_ctrl)); 293 len += sizeof(vce_rate_ctrl) / 4; 294 memcpy((ib_cpu + len), vce_config_ext, sizeof(vce_config_ext)); 295 len += sizeof(vce_config_ext) / 4; 296 memcpy((ib_cpu + len), vce_motion_est, sizeof(vce_motion_est)); 297 len += sizeof(vce_motion_est) / 4; 298 memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo)); 299 len += sizeof(vce_rdo) / 4; 300 memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl)); 301 len += sizeof(vce_pic_ctrl) / 4; 302 303 r = submit(len, AMDGPU_HW_IP_VCE); 304 CU_ASSERT_EQUAL(r, 0); 305} 306 307static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc) 308{ 309 310 uint64_t luma_offset, chroma_offset; 311 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; 312 unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16); 313 int len = 0, i, r; 314 315 luma_offset = enc->vbuf.addr; 316 chroma_offset = luma_offset + luma_size; 317 318 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 319 len += sizeof(vce_session) / 4; 320 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 321 len += sizeof(vce_taskinfo) / 4; 322 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); 323 ib_cpu[len + 2] = enc->bs[0].addr >> 32; 324 ib_cpu[len + 3] = enc->bs[0].addr; 325 len += sizeof(vce_bs_buffer) / 4; 326 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); 327 ib_cpu[len + 2] = enc->cpb.addr >> 32; 328 ib_cpu[len + 3] = enc->cpb.addr; 329 len += sizeof(vce_context_buffer) / 4; 330 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); 331 for (i = 0; i < 8; ++i) 332 ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2); 333 for (i = 0; i < 8; ++i) 334 ib_cpu[len + 10 + i] = luma_size * 1.5; 335 len += sizeof(vce_aux_buffer) / 4; 336 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 337 ib_cpu[len + 2] = enc->fb[0].addr >> 32; 338 ib_cpu[len + 3] = enc->fb[0].addr; 339 len += sizeof(vce_feedback) / 4; 340 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); 341 ib_cpu[len + 9] = luma_offset >> 32; 342 ib_cpu[len + 10] = luma_offset; 343 ib_cpu[len + 11] = chroma_offset >> 32; 344 ib_cpu[len + 12] = chroma_offset; 345 ib_cpu[len + 14] = ALIGN(enc->width, align); 346 ib_cpu[len + 15] = ALIGN(enc->width, align); 347 ib_cpu[len + 73] = luma_size * 1.5; 348 ib_cpu[len + 74] = luma_size * 2.5; 349 len += sizeof(vce_encode) / 4; 350 enc->ib_len = len; 351 if (!enc->two_instance) { 352 r = submit(len, AMDGPU_HW_IP_VCE); 353 CU_ASSERT_EQUAL(r, 0); 354 } 355} 356 357static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc) 358{ 359 uint64_t luma_offset, chroma_offset; 360 int len, i, r; 361 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; 362 unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16); 363 364 len = (enc->two_instance) ? enc->ib_len : 0; 365 luma_offset = enc->vbuf.addr; 366 chroma_offset = luma_offset + luma_size; 367 368 if (!enc->two_instance) { 369 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 370 len += sizeof(vce_session) / 4; 371 } 372 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 373 len += sizeof(vce_taskinfo) / 4; 374 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); 375 ib_cpu[len + 2] = enc->bs[1].addr >> 32; 376 ib_cpu[len + 3] = enc->bs[1].addr; 377 len += sizeof(vce_bs_buffer) / 4; 378 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); 379 ib_cpu[len + 2] = enc->cpb.addr >> 32; 380 ib_cpu[len + 3] = enc->cpb.addr; 381 len += sizeof(vce_context_buffer) / 4; 382 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); 383 for (i = 0; i < 8; ++i) 384 ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2); 385 for (i = 0; i < 8; ++i) 386 ib_cpu[len + 10 + i] = luma_size * 1.5; 387 len += sizeof(vce_aux_buffer) / 4; 388 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 389 ib_cpu[len + 2] = enc->fb[1].addr >> 32; 390 ib_cpu[len + 3] = enc->fb[1].addr; 391 len += sizeof(vce_feedback) / 4; 392 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); 393 ib_cpu[len + 2] = 0; 394 ib_cpu[len + 9] = luma_offset >> 32; 395 ib_cpu[len + 10] = luma_offset; 396 ib_cpu[len + 11] = chroma_offset >> 32; 397 ib_cpu[len + 12] = chroma_offset; 398 ib_cpu[len + 14] = ALIGN(enc->width, align); 399 ib_cpu[len + 15] = ALIGN(enc->width, align); 400 ib_cpu[len + 18] = 0; 401 ib_cpu[len + 19] = 0; 402 ib_cpu[len + 56] = 3; 403 ib_cpu[len + 57] = 0; 404 ib_cpu[len + 58] = 0; 405 ib_cpu[len + 59] = luma_size * 1.5; 406 ib_cpu[len + 60] = luma_size * 2.5; 407 ib_cpu[len + 73] = 0; 408 ib_cpu[len + 74] = luma_size; 409 ib_cpu[len + 81] = 1; 410 ib_cpu[len + 82] = 1; 411 len += sizeof(vce_encode) / 4; 412 413 r = submit(len, AMDGPU_HW_IP_VCE); 414 CU_ASSERT_EQUAL(r, 0); 415} 416 417static void check_result(struct amdgpu_vce_encode *enc) 418{ 419 uint64_t sum; 420 uint32_t s[2] = {180325, 15946}; 421 uint32_t *ptr, size; 422 int i, j, r; 423 424 for (i = 0; i < 2; ++i) { 425 r = amdgpu_bo_cpu_map(enc->fb[i].handle, (void **)&enc->fb[i].ptr); 426 CU_ASSERT_EQUAL(r, 0); 427 ptr = (uint32_t *)enc->fb[i].ptr; 428 size = ptr[4] - ptr[9]; 429 r = amdgpu_bo_cpu_unmap(enc->fb[i].handle); 430 CU_ASSERT_EQUAL(r, 0); 431 r = amdgpu_bo_cpu_map(enc->bs[i].handle, (void **)&enc->bs[i].ptr); 432 CU_ASSERT_EQUAL(r, 0); 433 for (j = 0, sum = 0; j < size; ++j) 434 sum += enc->bs[i].ptr[j]; 435 CU_ASSERT_EQUAL(sum, s[i]); 436 r = amdgpu_bo_cpu_unmap(enc->bs[i].handle); 437 CU_ASSERT_EQUAL(r, 0); 438 } 439} 440 441static void amdgpu_cs_vce_encode(void) 442{ 443 uint32_t vbuf_size, bs_size = 0x154000, cpb_size; 444 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; 445 int i, r; 446 447 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) 448 return; 449 450 vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; 451 cpb_size = vbuf_size * 10; 452 num_resources = 0; 453 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 454 resources[num_resources++] = enc.fb[0].handle; 455 alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT); 456 resources[num_resources++] = enc.fb[1].handle; 457 alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT); 458 resources[num_resources++] = enc.bs[0].handle; 459 alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT); 460 resources[num_resources++] = enc.bs[1].handle; 461 alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); 462 resources[num_resources++] = enc.vbuf.handle; 463 alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); 464 resources[num_resources++] = enc.cpb.handle; 465 resources[num_resources++] = ib_handle; 466 467 r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); 468 CU_ASSERT_EQUAL(r, 0); 469 470 memset(enc.vbuf.ptr, 0, vbuf_size); 471 for (i = 0; i < enc.height; ++i) { 472 memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width); 473 enc.vbuf.ptr += ALIGN(enc.width, align); 474 } 475 for (i = 0; i < enc.height / 2; ++i) { 476 memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width); 477 enc.vbuf.ptr += ALIGN(enc.width, align); 478 } 479 480 r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); 481 CU_ASSERT_EQUAL(r, 0); 482 483 amdgpu_cs_vce_config(); 484 485 if (family_id >= AMDGPU_FAMILY_VI) { 486 vce_taskinfo[3] = 3; 487 amdgpu_cs_vce_encode_idr(&enc); 488 amdgpu_cs_vce_encode_p(&enc); 489 check_result(&enc); 490 491 /* two pipes */ 492 vce_encode[16] = 0; 493 amdgpu_cs_vce_encode_idr(&enc); 494 amdgpu_cs_vce_encode_p(&enc); 495 check_result(&enc); 496 497 /* two instances */ 498 if (vce_harvest_config == 0) { 499 enc.two_instance = true; 500 vce_taskinfo[2] = 0x83; 501 vce_taskinfo[4] = 1; 502 amdgpu_cs_vce_encode_idr(&enc); 503 vce_taskinfo[2] = 0xffffffff; 504 vce_taskinfo[4] = 2; 505 amdgpu_cs_vce_encode_p(&enc); 506 check_result(&enc); 507 } 508 } else { 509 vce_taskinfo[3] = 3; 510 vce_encode[16] = 0; 511 amdgpu_cs_vce_encode_idr(&enc); 512 amdgpu_cs_vce_encode_p(&enc); 513 check_result(&enc); 514 } 515 516 free_resource(&enc.fb[0]); 517 free_resource(&enc.fb[1]); 518 free_resource(&enc.bs[0]); 519 free_resource(&enc.bs[1]); 520 free_resource(&enc.vbuf); 521 free_resource(&enc.cpb); 522} 523 524static void amdgpu_cs_vce_destroy(void) 525{ 526 int len, r; 527 528 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) 529 return; 530 531 num_resources = 0; 532 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 533 resources[num_resources++] = enc.fb[0].handle; 534 resources[num_resources++] = ib_handle; 535 536 len = 0; 537 memcpy(ib_cpu, vce_session, sizeof(vce_session)); 538 len += sizeof(vce_session) / 4; 539 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 540 ib_cpu[len + 3] = 1; 541 len += sizeof(vce_taskinfo) / 4; 542 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 543 ib_cpu[len + 2] = enc.fb[0].addr >> 32; 544 ib_cpu[len + 3] = enc.fb[0].addr; 545 len += sizeof(vce_feedback) / 4; 546 memcpy((ib_cpu + len), vce_destroy, sizeof(vce_destroy)); 547 len += sizeof(vce_destroy) / 4; 548 549 r = submit(len, AMDGPU_HW_IP_VCE); 550 CU_ASSERT_EQUAL(r, 0); 551 552 free_resource(&enc.fb[0]); 553} 554