vm_tests.c revision 7cdc0497
1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22*/ 23 24#include "CUnit/Basic.h" 25 26#include "amdgpu_test.h" 27#include "amdgpu_drm.h" 28#include "amdgpu_internal.h" 29 30static amdgpu_device_handle device_handle; 31static uint32_t major_version; 32static uint32_t minor_version; 33 34static void amdgpu_vmid_reserve_test(void); 35static void amdgpu_vm_unaligned_map(void); 36 37CU_BOOL suite_vm_tests_enable(void) 38{ 39 CU_BOOL enable = CU_TRUE; 40 41 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, 42 &minor_version, &device_handle)) 43 return CU_FALSE; 44 45 if (device_handle->info.family_id == AMDGPU_FAMILY_SI) { 46 printf("\n\nCurrently hangs the CP on this ASIC, VM suite disabled\n"); 47 enable = CU_FALSE; 48 } 49 50 if (amdgpu_device_deinitialize(device_handle)) 51 return CU_FALSE; 52 53 return enable; 54} 55 56int suite_vm_tests_init(void) 57{ 58 int r; 59 60 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, 61 &minor_version, &device_handle); 62 63 if (r) { 64 if ((r == -EACCES) && (errno == EACCES)) 65 printf("\n\nError:%s. " 66 "Hint:Try to run this test program as root.", 67 strerror(errno)); 68 return CUE_SINIT_FAILED; 69 } 70 71 return CUE_SUCCESS; 72} 73 74int suite_vm_tests_clean(void) 75{ 76 int r = amdgpu_device_deinitialize(device_handle); 77 78 if (r == 0) 79 return CUE_SUCCESS; 80 else 81 return CUE_SCLEAN_FAILED; 82} 83 84 85CU_TestInfo vm_tests[] = { 86 { "resere vmid test", amdgpu_vmid_reserve_test }, 87 { "unaligned map", amdgpu_vm_unaligned_map }, 88 CU_TEST_INFO_NULL, 89}; 90 91static void amdgpu_vmid_reserve_test(void) 92{ 93 amdgpu_context_handle context_handle; 94 amdgpu_bo_handle ib_result_handle; 95 void *ib_result_cpu; 96 uint64_t ib_result_mc_address; 97 struct amdgpu_cs_request ibs_request; 98 struct amdgpu_cs_ib_info ib_info; 99 struct amdgpu_cs_fence fence_status; 100 uint32_t expired, flags; 101 int i, r; 102 amdgpu_bo_list_handle bo_list; 103 amdgpu_va_handle va_handle; 104 static uint32_t *ptr; 105 106 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 107 CU_ASSERT_EQUAL(r, 0); 108 109 flags = 0; 110 r = amdgpu_vm_reserve_vmid(device_handle, flags); 111 CU_ASSERT_EQUAL(r, 0); 112 113 114 r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, 115 AMDGPU_GEM_DOMAIN_GTT, 0, 116 &ib_result_handle, &ib_result_cpu, 117 &ib_result_mc_address, &va_handle); 118 CU_ASSERT_EQUAL(r, 0); 119 120 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, 121 &bo_list); 122 CU_ASSERT_EQUAL(r, 0); 123 124 ptr = ib_result_cpu; 125 126 for (i = 0; i < 16; ++i) 127 ptr[i] = 0xffff1000; 128 129 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); 130 ib_info.ib_mc_address = ib_result_mc_address; 131 ib_info.size = 16; 132 133 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); 134 ibs_request.ip_type = AMDGPU_HW_IP_GFX; 135 ibs_request.ring = 0; 136 ibs_request.number_of_ibs = 1; 137 ibs_request.ibs = &ib_info; 138 ibs_request.resources = bo_list; 139 ibs_request.fence_info.handle = NULL; 140 141 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); 142 CU_ASSERT_EQUAL(r, 0); 143 144 145 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); 146 fence_status.context = context_handle; 147 fence_status.ip_type = AMDGPU_HW_IP_GFX; 148 fence_status.ip_instance = 0; 149 fence_status.ring = 0; 150 fence_status.fence = ibs_request.seq_no; 151 152 r = amdgpu_cs_query_fence_status(&fence_status, 153 AMDGPU_TIMEOUT_INFINITE,0, &expired); 154 CU_ASSERT_EQUAL(r, 0); 155 156 r = amdgpu_bo_list_destroy(bo_list); 157 CU_ASSERT_EQUAL(r, 0); 158 159 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, 160 ib_result_mc_address, 4096); 161 CU_ASSERT_EQUAL(r, 0); 162 163 flags = 0; 164 r = amdgpu_vm_unreserve_vmid(device_handle, flags); 165 CU_ASSERT_EQUAL(r, 0); 166 167 168 r = amdgpu_cs_ctx_free(context_handle); 169 CU_ASSERT_EQUAL(r, 0); 170} 171 172static void amdgpu_vm_unaligned_map(void) 173{ 174 const uint64_t map_size = (4ULL << 30) - (2 << 12); 175 struct amdgpu_bo_alloc_request request = {}; 176 amdgpu_bo_handle buf_handle; 177 amdgpu_va_handle handle; 178 uint64_t vmc_addr; 179 int r; 180 181 request.alloc_size = 4ULL << 30; 182 request.phys_alignment = 4096; 183 request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM; 184 request.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 185 186 r = amdgpu_bo_alloc(device_handle, &request, &buf_handle); 187 /* Don't let the test fail if the device doesn't have enough VRAM */ 188 if (r) 189 return; 190 191 r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general, 192 4ULL << 30, 1ULL << 30, 0, &vmc_addr, 193 &handle, 0); 194 CU_ASSERT_EQUAL(r, 0); 195 if (r) 196 goto error_va_alloc; 197 198 vmc_addr += 1 << 12; 199 200 r = amdgpu_bo_va_op(buf_handle, 0, map_size, vmc_addr, 0, 201 AMDGPU_VA_OP_MAP); 202 CU_ASSERT_EQUAL(r, 0); 203 if (r) 204 goto error_va_alloc; 205 206 amdgpu_bo_va_op(buf_handle, 0, map_size, vmc_addr, 0, 207 AMDGPU_VA_OP_UNMAP); 208 209error_va_alloc: 210 amdgpu_bo_free(buf_handle); 211 212} 213