drm-test-tegra.h revision 0ed5401b
10ed5401bSmrg/* 20ed5401bSmrg * Copyright © 2014 NVIDIA Corporation 30ed5401bSmrg * 40ed5401bSmrg * Permission is hereby granted, free of charge, to any person obtaining a 50ed5401bSmrg * copy of this software and associated documentation files (the "Software"), 60ed5401bSmrg * to deal in the Software without restriction, including without limitation 70ed5401bSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80ed5401bSmrg * and/or sell copies of the Software, and to permit persons to whom the 90ed5401bSmrg * Software is furnished to do so, subject to the following conditions: 100ed5401bSmrg * 110ed5401bSmrg * The above copyright notice and this permission notice shall be included in 120ed5401bSmrg * all copies or substantial portions of the Software. 130ed5401bSmrg * 140ed5401bSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 150ed5401bSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 160ed5401bSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 170ed5401bSmrg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 180ed5401bSmrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 190ed5401bSmrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 200ed5401bSmrg * OTHER DEALINGS IN THE SOFTWARE. 210ed5401bSmrg */ 220ed5401bSmrg 230ed5401bSmrg#ifndef TEGRA_DRM_TEST_TEGRA_H 240ed5401bSmrg#define TEGRA_DRM_TEST_TEGRA_H 250ed5401bSmrg 260ed5401bSmrg#include "drm-test.h" 270ed5401bSmrg#include "tegra.h" 280ed5401bSmrg 290ed5401bSmrg#define HOST1X_OPCODE_SETCL(offset, classid, mask) \ 300ed5401bSmrg ((0x0 << 28) | (((offset) & 0xfff) << 16) | (((classid) & 0x3ff) << 6) | ((mask) & 0x3f)) 310ed5401bSmrg#define HOST1X_OPCODE_INCR(offset, count) \ 320ed5401bSmrg ((0x1 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff)) 330ed5401bSmrg#define HOST1X_OPCODE_NONINCR(offset, count) \ 340ed5401bSmrg ((0x2 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff)) 350ed5401bSmrg#define HOST1X_OPCODE_MASK(offset, mask) \ 360ed5401bSmrg ((0x3 << 28) | (((offset) & 0xfff) << 16) | ((mask) & 0xffff)) 370ed5401bSmrg#define HOST1X_OPCODE_IMM(offset, data) \ 380ed5401bSmrg ((0x4 << 28) | (((offset) & 0xfff) << 16) | ((data) & 0xffff)) 390ed5401bSmrg#define HOST1X_OPCODE_EXTEND(subop, value) \ 400ed5401bSmrg ((0xe << 28) | (((subop) & 0xf) << 24) | ((value) & 0xffffff)) 410ed5401bSmrg 420ed5401bSmrg#define HOST1X_CLASS_GR2D 0x51 430ed5401bSmrg 440ed5401bSmrgstruct drm_tegra_gr2d { 450ed5401bSmrg struct drm_tegra *drm; 460ed5401bSmrg struct drm_tegra_channel *channel; 470ed5401bSmrg}; 480ed5401bSmrg 490ed5401bSmrgint drm_tegra_gr2d_open(struct drm_tegra *drm, struct drm_tegra_gr2d **gr2dp); 500ed5401bSmrgint drm_tegra_gr2d_close(struct drm_tegra_gr2d *gr2d); 510ed5401bSmrgint drm_tegra_gr2d_fill(struct drm_tegra_gr2d *gr2d, struct drm_framebuffer *fb, 520ed5401bSmrg unsigned int x, unsigned int y, unsigned int width, 530ed5401bSmrg unsigned int height, uint32_t color); 540ed5401bSmrg 550ed5401bSmrg#endif 56