10ed5401bSmrg/* 20ed5401bSmrg * Copyright © 2018 NVIDIA Corporation 30ed5401bSmrg * 40ed5401bSmrg * Permission is hereby granted, free of charge, to any person obtaining a 50ed5401bSmrg * copy of this software and associated documentation files (the "Software"), 60ed5401bSmrg * to deal in the Software without restriction, including without limitation 70ed5401bSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80ed5401bSmrg * and/or sell copies of the Software, and to permit persons to whom the 90ed5401bSmrg * Software is furnished to do so, subject to the following conditions: 100ed5401bSmrg * 110ed5401bSmrg * The above copyright notice and this permission notice shall be included in 120ed5401bSmrg * all copies or substantial portions of the Software. 130ed5401bSmrg * 140ed5401bSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 150ed5401bSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 160ed5401bSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 170ed5401bSmrg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 180ed5401bSmrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 190ed5401bSmrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 200ed5401bSmrg * OTHER DEALINGS IN THE SOFTWARE. 210ed5401bSmrg */ 220ed5401bSmrg 230ed5401bSmrg#include <errno.h> 240ed5401bSmrg#include <string.h> 250ed5401bSmrg 260ed5401bSmrg#include "private.h" 270ed5401bSmrg#include "tegra.h" 280ed5401bSmrg#include "vic.h" 290ed5401bSmrg#include "vic30.h" 300ed5401bSmrg 310ed5401bSmrgstruct vic30 { 320ed5401bSmrg struct vic base; 330ed5401bSmrg 340ed5401bSmrg struct { 350ed5401bSmrg struct drm_tegra_mapping *map; 360ed5401bSmrg struct drm_tegra_bo *bo; 370ed5401bSmrg } config; 380ed5401bSmrg 390ed5401bSmrg struct { 400ed5401bSmrg struct drm_tegra_mapping *map; 410ed5401bSmrg struct drm_tegra_bo *bo; 420ed5401bSmrg } filter; 430ed5401bSmrg 440ed5401bSmrg struct { 450ed5401bSmrg struct drm_tegra_mapping *map; 460ed5401bSmrg struct drm_tegra_bo *bo; 470ed5401bSmrg } hist; 480ed5401bSmrg}; 490ed5401bSmrg 500ed5401bSmrgstatic int vic30_fill(struct vic *v, struct vic_image *output, 510ed5401bSmrg unsigned int left, unsigned int top, 520ed5401bSmrg unsigned int right, unsigned int bottom, 530ed5401bSmrg unsigned int alpha, unsigned int red, 540ed5401bSmrg unsigned int green, unsigned int blue) 550ed5401bSmrg{ 560ed5401bSmrg struct vic30 *vic = container_of(v, struct vic30, base); 570ed5401bSmrg ConfigStruct *c; 580ed5401bSmrg int err; 590ed5401bSmrg 600ed5401bSmrg err = drm_tegra_bo_map(vic->config.bo, (void **)&c); 610ed5401bSmrg if (err < 0) { 620ed5401bSmrg fprintf(stderr, "failed to map configuration structure: %s\n", 630ed5401bSmrg strerror(-err)); 640ed5401bSmrg return err; 650ed5401bSmrg } 660ed5401bSmrg 670ed5401bSmrg memset(c, 0, sizeof(*c)); 680ed5401bSmrg 690ed5401bSmrg c->surfaceList0Struct.TargetRectLeft = left; 700ed5401bSmrg c->surfaceList0Struct.TargetRectTop = top; 710ed5401bSmrg c->surfaceList0Struct.TargetRectRight = right; 720ed5401bSmrg c->surfaceList0Struct.TargetRectBottom = bottom; 730ed5401bSmrg 740ed5401bSmrg c->blending0Struct.PixelFormat = output->format; 750ed5401bSmrg c->blending0Struct.BackgroundAlpha = alpha; 760ed5401bSmrg c->blending0Struct.BackgroundR = red; 770ed5401bSmrg c->blending0Struct.BackgroundG = green; 780ed5401bSmrg c->blending0Struct.BackgroundB = blue; 790ed5401bSmrg c->blending0Struct.LumaWidth = output->stride - 1; 800ed5401bSmrg c->blending0Struct.LumaHeight = output->height - 1; 810ed5401bSmrg c->blending0Struct.ChromaWidth = 16383; 820ed5401bSmrg c->blending0Struct.ChromaWidth = 16383; 830ed5401bSmrg c->blending0Struct.TargetRectLeft = left; 840ed5401bSmrg c->blending0Struct.TargetRectTop = top; 850ed5401bSmrg c->blending0Struct.TargetRectRight = right; 860ed5401bSmrg c->blending0Struct.TargetRectBottom = bottom; 870ed5401bSmrg c->blending0Struct.SurfaceWidth = output->width - 1; 880ed5401bSmrg c->blending0Struct.SurfaceHeight = output->height - 1; 890ed5401bSmrg c->blending0Struct.BlkKind = output->kind; 900ed5401bSmrg c->blending0Struct.BlkHeight = 0; 910ed5401bSmrg 920ed5401bSmrg c->fetchControl0Struct.TargetRectLeft = left; 930ed5401bSmrg c->fetchControl0Struct.TargetRectTop = top; 940ed5401bSmrg c->fetchControl0Struct.TargetRectRight = right; 950ed5401bSmrg c->fetchControl0Struct.TargetRectBottom = bottom; 960ed5401bSmrg 970ed5401bSmrg drm_tegra_bo_unmap(vic->config.bo); 980ed5401bSmrg 990ed5401bSmrg return 0; 1000ed5401bSmrg} 1010ed5401bSmrg 1020ed5401bSmrgstatic int vic30_blit(struct vic *v, struct vic_image *output, 1030ed5401bSmrg struct vic_image *input) 1040ed5401bSmrg{ 1050ed5401bSmrg struct vic30 *vic = container_of(v, struct vic30, base); 1060ed5401bSmrg ColorConversionLumaAlphaStruct *ccla; 1070ed5401bSmrg ColorConversionMatrixStruct *ccm; 1080ed5401bSmrg ColorConversionClampStruct *ccc; 1090ed5401bSmrg SurfaceListSurfaceStruct *s; 1100ed5401bSmrg BlendingSurfaceStruct *b; 1110ed5401bSmrg SurfaceCache0Struct *sc; 1120ed5401bSmrg ConfigStruct *c; 1130ed5401bSmrg int err; 1140ed5401bSmrg 1150ed5401bSmrg err = drm_tegra_bo_map(vic->config.bo, (void **)&c); 1160ed5401bSmrg if (err < 0) { 1170ed5401bSmrg fprintf(stderr, "failed to map configuration structure: %s\n", 1180ed5401bSmrg strerror(-err)); 1190ed5401bSmrg return err; 1200ed5401bSmrg } 1210ed5401bSmrg 1220ed5401bSmrg memset(c, 0, sizeof(*c)); 1230ed5401bSmrg 1240ed5401bSmrg c->surfaceList0Struct.TargetRectLeft = 0; 1250ed5401bSmrg c->surfaceList0Struct.TargetRectTop = 0; 1260ed5401bSmrg c->surfaceList0Struct.TargetRectRight = output->width - 1; 1270ed5401bSmrg c->surfaceList0Struct.TargetRectBottom = output->height - 1; 1280ed5401bSmrg 1290ed5401bSmrg c->blending0Struct.PixelFormat = output->format; 1300ed5401bSmrg c->blending0Struct.BackgroundAlpha = 0; 1310ed5401bSmrg c->blending0Struct.BackgroundR = 0; 1320ed5401bSmrg c->blending0Struct.BackgroundG = 0; 1330ed5401bSmrg c->blending0Struct.BackgroundB = 0; 1340ed5401bSmrg c->blending0Struct.LumaWidth = output->stride - 1; 1350ed5401bSmrg c->blending0Struct.LumaHeight = output->height - 1; 1360ed5401bSmrg c->blending0Struct.ChromaWidth = 16383; 1370ed5401bSmrg c->blending0Struct.ChromaWidth = 16383; 1380ed5401bSmrg c->blending0Struct.TargetRectLeft = 0; 1390ed5401bSmrg c->blending0Struct.TargetRectTop = 0; 1400ed5401bSmrg c->blending0Struct.TargetRectRight = output->width - 1; 1410ed5401bSmrg c->blending0Struct.TargetRectBottom = output->height - 1; 1420ed5401bSmrg c->blending0Struct.SurfaceWidth = output->width - 1; 1430ed5401bSmrg c->blending0Struct.SurfaceHeight = output->height - 1; 1440ed5401bSmrg c->blending0Struct.BlkKind = output->kind; 1450ed5401bSmrg c->blending0Struct.BlkHeight = 0; 1460ed5401bSmrg 1470ed5401bSmrg c->fetchControl0Struct.TargetRectLeft = 0; 1480ed5401bSmrg c->fetchControl0Struct.TargetRectTop = 0; 1490ed5401bSmrg c->fetchControl0Struct.TargetRectRight = output->width - 1; 1500ed5401bSmrg c->fetchControl0Struct.TargetRectBottom = output->height - 1; 1510ed5401bSmrg 1520ed5401bSmrg /* setup fetch parameters for slot 0 */ 1530ed5401bSmrg c->fetchControl0Struct.Enable0 = 0x1; 1540ed5401bSmrg c->fetchControl0Struct.Iir0 = 0x300; 1550ed5401bSmrg 1560ed5401bSmrg /* setup cache parameters for slot 0 */ 1570ed5401bSmrg sc = &c->surfaceCache0Struct; 1580ed5401bSmrg sc->PixelFormat0 = input->format; 1590ed5401bSmrg 1600ed5401bSmrg /* setup surface configuration for slot 0 */ 1610ed5401bSmrg s = &c->surfaceListSurfaceStruct[0]; 1620ed5401bSmrg s->Enable = 1; 1630ed5401bSmrg s->FrameFormat = DXVAHD_FRAME_FORMAT_PROGRESSIVE; 1640ed5401bSmrg s->PixelFormat = input->format; 1650ed5401bSmrg s->SurfaceWidth = input->width - 1; 1660ed5401bSmrg s->SurfaceHeight = input->height - 1; 1670ed5401bSmrg s->LumaWidth = input->stride - 1; 1680ed5401bSmrg s->LumaHeight = input->height - 1; 1690ed5401bSmrg s->ChromaWidth = 16383; 1700ed5401bSmrg s->ChromaHeight = 16383; 1710ed5401bSmrg s->CacheWidth = VIC_CACHE_WIDTH_256Bx1; //VIC_CACHE_WIDTH_16Bx16; 1720ed5401bSmrg s->BlkKind = input->kind; 1730ed5401bSmrg s->BlkHeight = 0; 1740ed5401bSmrg s->DestRectLeft = 0; 1750ed5401bSmrg s->DestRectTop = 0; 1760ed5401bSmrg s->DestRectRight = output->width - 1; 1770ed5401bSmrg s->DestRectBottom = output->height - 1; 1780ed5401bSmrg s->SourceRectLeft = 0 << 16; 1790ed5401bSmrg s->SourceRectTop = 0 << 16; 1800ed5401bSmrg s->SourceRectRight = (input->width - 1) << 16; 1810ed5401bSmrg s->SourceRectBottom = (input->height - 1) << 16; 1820ed5401bSmrg 1830ed5401bSmrg /* setup color conversion for slot 0 */ 1840ed5401bSmrg ccla = &c->colorConversionLumaAlphaStruct[0]; 1850ed5401bSmrg ccla->PlanarAlpha = 1023; 1860ed5401bSmrg ccla->ConstantAlpha = 0; 1870ed5401bSmrg 1880ed5401bSmrg ccm = &c->colorConversionMatrixStruct[0]; 1890ed5401bSmrg ccm->c00 = 1023; 1900ed5401bSmrg ccm->c11 = 1023; 1910ed5401bSmrg ccm->c22 = 1023; 1920ed5401bSmrg 1930ed5401bSmrg ccc = &c->colorConversionClampStruct[0]; 1940ed5401bSmrg ccc->low = 0; 1950ed5401bSmrg ccc->high = 1023; 1960ed5401bSmrg 1970ed5401bSmrg /* setup blending for slot 0 */ 1980ed5401bSmrg b = &c->blendingSurfaceStruct[0]; 1990ed5401bSmrg b->AlphaK1 = 1023; 2000ed5401bSmrg b->SrcFactCMatchSelect = VIC_BLEND_SRCFACTC_K1; 2010ed5401bSmrg b->SrcFactAMatchSelect = VIC_BLEND_SRCFACTA_K1; 2020ed5401bSmrg b->DstFactCMatchSelect = VIC_BLEND_DSTFACTC_NEG_K1_TIMES_SRC; 2030ed5401bSmrg b->DstFactAMatchSelect = VIC_BLEND_DSTFACTA_NEG_K1_TIMES_SRC; 2040ed5401bSmrg 2050ed5401bSmrg drm_tegra_bo_unmap(vic->config.bo); 2060ed5401bSmrg 2070ed5401bSmrg return 0; 2080ed5401bSmrg} 2090ed5401bSmrg 2100ed5401bSmrgstatic int vic30_flip(struct vic *v, struct vic_image *output, 2110ed5401bSmrg struct vic_image *input) 2120ed5401bSmrg{ 2130ed5401bSmrg struct vic30 *vic = container_of(v, struct vic30, base); 2140ed5401bSmrg ColorConversionLumaAlphaStruct *ccla; 2150ed5401bSmrg ColorConversionMatrixStruct *ccm; 2160ed5401bSmrg ColorConversionClampStruct *ccc; 2170ed5401bSmrg SurfaceListSurfaceStruct *s; 2180ed5401bSmrg BlendingSurfaceStruct *b; 2190ed5401bSmrg SurfaceCache0Struct *sc; 2200ed5401bSmrg ConfigStruct *c; 2210ed5401bSmrg int err; 2220ed5401bSmrg 2230ed5401bSmrg err = drm_tegra_bo_map(vic->config.bo, (void **)&c); 2240ed5401bSmrg if (err < 0) { 2250ed5401bSmrg fprintf(stderr, "failed to map configuration structure: %s\n", 2260ed5401bSmrg strerror(-err)); 2270ed5401bSmrg return err; 2280ed5401bSmrg } 2290ed5401bSmrg 2300ed5401bSmrg memset(c, 0, sizeof(*c)); 2310ed5401bSmrg 2320ed5401bSmrg c->surfaceList0Struct.TargetRectLeft = 0; 2330ed5401bSmrg c->surfaceList0Struct.TargetRectTop = 0; 2340ed5401bSmrg c->surfaceList0Struct.TargetRectRight = output->width - 1; 2350ed5401bSmrg c->surfaceList0Struct.TargetRectBottom = output->height - 1; 2360ed5401bSmrg 2370ed5401bSmrg c->blending0Struct.PixelFormat = output->format; 2380ed5401bSmrg c->blending0Struct.BackgroundAlpha = 0; 2390ed5401bSmrg c->blending0Struct.BackgroundR = 0; 2400ed5401bSmrg c->blending0Struct.BackgroundG = 0; 2410ed5401bSmrg c->blending0Struct.BackgroundB = 0; 2420ed5401bSmrg c->blending0Struct.LumaWidth = output->stride - 1; 2430ed5401bSmrg c->blending0Struct.LumaHeight = output->height - 1; 2440ed5401bSmrg c->blending0Struct.ChromaWidth = 16383; 2450ed5401bSmrg c->blending0Struct.ChromaWidth = 16383; 2460ed5401bSmrg c->blending0Struct.TargetRectLeft = 0; 2470ed5401bSmrg c->blending0Struct.TargetRectTop = 0; 2480ed5401bSmrg c->blending0Struct.TargetRectRight = output->width - 1; 2490ed5401bSmrg c->blending0Struct.TargetRectBottom = output->height - 1; 2500ed5401bSmrg c->blending0Struct.SurfaceWidth = output->width - 1; 2510ed5401bSmrg c->blending0Struct.SurfaceHeight = output->height - 1; 2520ed5401bSmrg c->blending0Struct.BlkKind = output->kind; 2530ed5401bSmrg c->blending0Struct.BlkHeight = 0; 2540ed5401bSmrg c->blending0Struct.OutputFlipY = 1; 2550ed5401bSmrg 2560ed5401bSmrg c->fetchControl0Struct.TargetRectLeft = 0; 2570ed5401bSmrg c->fetchControl0Struct.TargetRectTop = 0; 2580ed5401bSmrg c->fetchControl0Struct.TargetRectRight = output->width - 1; 2590ed5401bSmrg c->fetchControl0Struct.TargetRectBottom = output->height - 1; 2600ed5401bSmrg 2610ed5401bSmrg /* setup fetch parameters for slot 0 */ 2620ed5401bSmrg c->fetchControl0Struct.Enable0 = 0x1; 2630ed5401bSmrg c->fetchControl0Struct.Iir0 = 0x300; 2640ed5401bSmrg 2650ed5401bSmrg /* setup cache parameters for slot 0 */ 2660ed5401bSmrg sc = &c->surfaceCache0Struct; 2670ed5401bSmrg sc->PixelFormat0 = input->format; 2680ed5401bSmrg 2690ed5401bSmrg /* setup surface configuration for slot 0 */ 2700ed5401bSmrg s = &c->surfaceListSurfaceStruct[0]; 2710ed5401bSmrg s->Enable = 1; 2720ed5401bSmrg s->FrameFormat = DXVAHD_FRAME_FORMAT_PROGRESSIVE; 2730ed5401bSmrg s->PixelFormat = input->format; 2740ed5401bSmrg s->SurfaceWidth = input->width - 1; 2750ed5401bSmrg s->SurfaceHeight = input->height - 1; 2760ed5401bSmrg s->LumaWidth = input->stride - 1; 2770ed5401bSmrg s->LumaHeight = input->height - 1; 2780ed5401bSmrg s->ChromaWidth = 16383; 2790ed5401bSmrg s->ChromaHeight = 16383; 2800ed5401bSmrg s->CacheWidth = VIC_CACHE_WIDTH_256Bx1; 2810ed5401bSmrg s->BlkKind = input->kind; 2820ed5401bSmrg s->BlkHeight = 0; 2830ed5401bSmrg s->DestRectLeft = 0; 2840ed5401bSmrg s->DestRectTop = 0; 2850ed5401bSmrg s->DestRectRight = output->width - 1; 2860ed5401bSmrg s->DestRectBottom = output->height - 1; 2870ed5401bSmrg s->SourceRectLeft = 0 << 16; 2880ed5401bSmrg s->SourceRectTop = 0 << 16; 2890ed5401bSmrg s->SourceRectRight = (input->width - 1) << 16; 2900ed5401bSmrg s->SourceRectBottom = (input->height - 1) << 16; 2910ed5401bSmrg 2920ed5401bSmrg /* setup color conversion for slot 0 */ 2930ed5401bSmrg ccla = &c->colorConversionLumaAlphaStruct[0]; 2940ed5401bSmrg ccla->PlanarAlpha = 1023; 2950ed5401bSmrg ccla->ConstantAlpha = 0; 2960ed5401bSmrg 2970ed5401bSmrg ccm = &c->colorConversionMatrixStruct[0]; 2980ed5401bSmrg ccm->c00 = 1023; 2990ed5401bSmrg ccm->c11 = 1023; 3000ed5401bSmrg ccm->c22 = 1023; 3010ed5401bSmrg 3020ed5401bSmrg ccc = &c->colorConversionClampStruct[0]; 3030ed5401bSmrg ccc->low = 0; 3040ed5401bSmrg ccc->high = 1023; 3050ed5401bSmrg 3060ed5401bSmrg /* setup blending for slot 0 */ 3070ed5401bSmrg b = &c->blendingSurfaceStruct[0]; 3080ed5401bSmrg b->AlphaK1 = 1023; 3090ed5401bSmrg b->SrcFactCMatchSelect = VIC_BLEND_SRCFACTC_K1; 3100ed5401bSmrg b->SrcFactAMatchSelect = VIC_BLEND_SRCFACTA_K1; 3110ed5401bSmrg b->DstFactCMatchSelect = VIC_BLEND_DSTFACTC_NEG_K1_TIMES_SRC; 3120ed5401bSmrg b->DstFactAMatchSelect = VIC_BLEND_DSTFACTA_NEG_K1_TIMES_SRC; 3130ed5401bSmrg 3140ed5401bSmrg drm_tegra_bo_unmap(vic->config.bo); 3150ed5401bSmrg 3160ed5401bSmrg return 0; 3170ed5401bSmrg} 3180ed5401bSmrg 3190ed5401bSmrgstatic int vic30_execute(struct vic *v, struct drm_tegra_pushbuf *pushbuf, 3200ed5401bSmrg uint32_t **ptrp, struct vic_image *output, 3210ed5401bSmrg struct vic_image **inputs, unsigned int num_inputs) 3220ed5401bSmrg{ 3230ed5401bSmrg struct vic30 *vic = container_of(v, struct vic30, base); 3240ed5401bSmrg unsigned int i; 3250ed5401bSmrg 3260ed5401bSmrg if (num_inputs > 1) 3270ed5401bSmrg return -EINVAL; 3280ed5401bSmrg 3290ed5401bSmrg VIC_PUSH_METHOD(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID, 1); 3300ed5401bSmrg VIC_PUSH_METHOD(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS, (sizeof(ConfigStruct) / 16) << 16); 3310ed5401bSmrg VIC_PUSH_BUFFER(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET, vic->config.map, 0, 0); 3320ed5401bSmrg VIC_PUSH_BUFFER(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET, vic->hist.map, 0, 0); 3330ed5401bSmrg VIC_PUSH_BUFFER(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET, output->map, 0, 0); 3340ed5401bSmrg 3350ed5401bSmrg for (i = 0; i < num_inputs; i++) 3360ed5401bSmrg VIC_PUSH_BUFFER(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_LUMA_OFFSET, inputs[i]->map, 0, 0); 3370ed5401bSmrg 3380ed5401bSmrg VIC_PUSH_METHOD(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_EXECUTE, 1 << 8); 3390ed5401bSmrg 3400ed5401bSmrg return 0; 3410ed5401bSmrg} 3420ed5401bSmrg 3430ed5401bSmrgstatic void vic30_free(struct vic *v) 3440ed5401bSmrg{ 3450ed5401bSmrg struct vic30 *vic = container_of(v, struct vic30, base); 3460ed5401bSmrg 3470ed5401bSmrg drm_tegra_channel_unmap(vic->hist.map); 3480ed5401bSmrg drm_tegra_bo_unref(vic->hist.bo); 3490ed5401bSmrg 3500ed5401bSmrg drm_tegra_channel_unmap(vic->filter.map); 3510ed5401bSmrg drm_tegra_bo_unref(vic->filter.bo); 3520ed5401bSmrg 3530ed5401bSmrg drm_tegra_channel_unmap(vic->config.map); 3540ed5401bSmrg drm_tegra_bo_unref(vic->config.bo); 3550ed5401bSmrg 3560ed5401bSmrg drm_tegra_syncpoint_free(v->syncpt); 3570ed5401bSmrg 3580ed5401bSmrg free(vic); 3590ed5401bSmrg} 3600ed5401bSmrg 3610ed5401bSmrgstatic const struct vic_ops vic30_ops = { 3620ed5401bSmrg .fill = vic30_fill, 3630ed5401bSmrg .blit = vic30_blit, 3640ed5401bSmrg .flip = vic30_flip, 3650ed5401bSmrg .execute = vic30_execute, 3660ed5401bSmrg .free = vic30_free, 3670ed5401bSmrg}; 3680ed5401bSmrg 3690ed5401bSmrgint vic30_new(struct drm_tegra *drm, struct drm_tegra_channel *channel, 3700ed5401bSmrg struct vic **vicp) 3710ed5401bSmrg{ 3720ed5401bSmrg struct vic30 *vic; 3730ed5401bSmrg void *ptr; 3740ed5401bSmrg int err; 3750ed5401bSmrg 3760ed5401bSmrg vic = calloc(1, sizeof(*vic)); 3770ed5401bSmrg if (!vic) 3780ed5401bSmrg return -ENOMEM; 3790ed5401bSmrg 3800ed5401bSmrg vic->base.drm = drm; 3810ed5401bSmrg vic->base.channel = channel; 3820ed5401bSmrg vic->base.ops = &vic30_ops; 3830ed5401bSmrg vic->base.version = 0x40; 3840ed5401bSmrg 3850ed5401bSmrg err = drm_tegra_syncpoint_new(drm, &vic->base.syncpt); 3860ed5401bSmrg if (err < 0) { 3870ed5401bSmrg fprintf(stderr, "failed to allocate syncpoint: %s\n", strerror(-err)); 3880ed5401bSmrg return err; 3890ed5401bSmrg } 3900ed5401bSmrg 3910ed5401bSmrg err = drm_tegra_bo_new(drm, 0, 16384, &vic->config.bo); 3920ed5401bSmrg if (err < 0) { 3930ed5401bSmrg fprintf(stderr, "failed to allocate configuration structure: %s\n", 3940ed5401bSmrg strerror(-err)); 3950ed5401bSmrg return err; 3960ed5401bSmrg } 3970ed5401bSmrg 3980ed5401bSmrg err = drm_tegra_channel_map(channel, vic->config.bo, DRM_TEGRA_CHANNEL_MAP_READ, 3990ed5401bSmrg &vic->config.map); 4000ed5401bSmrg if (err < 0) { 4010ed5401bSmrg fprintf(stderr, "failed to map configuration structure: %s\n", 4020ed5401bSmrg strerror(-err)); 4030ed5401bSmrg return err; 4040ed5401bSmrg } 4050ed5401bSmrg 4060ed5401bSmrg err = drm_tegra_bo_new(drm, 0, 16384, &vic->filter.bo); 4070ed5401bSmrg if (err < 0) { 4080ed5401bSmrg fprintf(stderr, "failed to allocate filter buffer: %s\n", 4090ed5401bSmrg strerror(-err)); 4100ed5401bSmrg return err; 4110ed5401bSmrg } 4120ed5401bSmrg 4130ed5401bSmrg err = drm_tegra_bo_map(vic->filter.bo, &ptr); 4140ed5401bSmrg if (err < 0) { 4150ed5401bSmrg fprintf(stderr, "failed to map filter buffer: %s\n", strerror(-err)); 4160ed5401bSmrg return err; 4170ed5401bSmrg } 4180ed5401bSmrg 4190ed5401bSmrg memset(ptr, 0, 16384); 4200ed5401bSmrg drm_tegra_bo_unmap(vic->filter.bo); 4210ed5401bSmrg 4220ed5401bSmrg err = drm_tegra_channel_map(channel, vic->filter.bo, DRM_TEGRA_CHANNEL_MAP_READ, 4230ed5401bSmrg &vic->filter.map); 4240ed5401bSmrg if (err < 0) { 4250ed5401bSmrg fprintf(stderr, "failed to map filter buffer: %s\n", 4260ed5401bSmrg strerror(-err)); 4270ed5401bSmrg return err; 4280ed5401bSmrg } 4290ed5401bSmrg 4300ed5401bSmrg err = drm_tegra_bo_new(drm, 0, 4096, &vic->hist.bo); 4310ed5401bSmrg if (err < 0) { 4320ed5401bSmrg fprintf(stderr, "failed to allocate history buffer: %s\n", 4330ed5401bSmrg strerror(-err)); 4340ed5401bSmrg return err; 4350ed5401bSmrg } 4360ed5401bSmrg 4370ed5401bSmrg err = drm_tegra_bo_map(vic->hist.bo, &ptr); 4380ed5401bSmrg if (err < 0) { 4390ed5401bSmrg fprintf(stderr, "failed to map history buffer: %s\n", strerror(-err)); 4400ed5401bSmrg return err; 4410ed5401bSmrg } 4420ed5401bSmrg 4430ed5401bSmrg memset(ptr, 0, 4096); 4440ed5401bSmrg drm_tegra_bo_unmap(vic->hist.bo); 4450ed5401bSmrg 4460ed5401bSmrg err = drm_tegra_channel_map(channel, vic->hist.bo, DRM_TEGRA_CHANNEL_MAP_READ_WRITE, 4470ed5401bSmrg &vic->hist.map); 4480ed5401bSmrg if (err < 0) { 4490ed5401bSmrg fprintf(stderr, "failed to map histogram buffer: %s\n", 4500ed5401bSmrg strerror(-err)); 4510ed5401bSmrg return err; 4520ed5401bSmrg } 4530ed5401bSmrg 4540ed5401bSmrg if (vicp) 4550ed5401bSmrg *vicp = &vic->base; 4560ed5401bSmrg 4570ed5401bSmrg return 0; 4580ed5401bSmrg} 459