13f012e29Smrg/*
23f012e29Smrg * Copyright © 2014 Broadcom
33f012e29Smrg *
43f012e29Smrg * Permission is hereby granted, free of charge, to any person obtaining a
53f012e29Smrg * copy of this software and associated documentation files (the "Software"),
63f012e29Smrg * to deal in the Software without restriction, including without limitation
73f012e29Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
83f012e29Smrg * and/or sell copies of the Software, and to permit persons to whom the
93f012e29Smrg * Software is furnished to do so, subject to the following conditions:
103f012e29Smrg *
113f012e29Smrg * The above copyright notice and this permission notice (including the next
123f012e29Smrg * paragraph) shall be included in all copies or substantial portions of the
133f012e29Smrg * Software.
143f012e29Smrg *
153f012e29Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
163f012e29Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
173f012e29Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
183f012e29Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
193f012e29Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
203f012e29Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
213f012e29Smrg * IN THE SOFTWARE.
223f012e29Smrg */
233f012e29Smrg
243f012e29Smrg#ifndef VC4_PACKET_H
253f012e29Smrg#define VC4_PACKET_H
263f012e29Smrg
273f012e29Smrgenum vc4_packet {
283f012e29Smrg        VC4_PACKET_HALT = 0,
293f012e29Smrg        VC4_PACKET_NOP = 1,
303f012e29Smrg
313f012e29Smrg        VC4_PACKET_FLUSH = 4,
323f012e29Smrg        VC4_PACKET_FLUSH_ALL = 5,
333f012e29Smrg        VC4_PACKET_START_TILE_BINNING = 6,
343f012e29Smrg        VC4_PACKET_INCREMENT_SEMAPHORE = 7,
353f012e29Smrg        VC4_PACKET_WAIT_ON_SEMAPHORE = 8,
363f012e29Smrg
373f012e29Smrg        VC4_PACKET_BRANCH = 16,
383f012e29Smrg        VC4_PACKET_BRANCH_TO_SUB_LIST = 17,
393f012e29Smrg        VC4_PACKET_RETURN_FROM_SUB_LIST = 18,
403f012e29Smrg
413f012e29Smrg        VC4_PACKET_STORE_MS_TILE_BUFFER = 24,
423f012e29Smrg        VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25,
433f012e29Smrg        VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26,
443f012e29Smrg        VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27,
453f012e29Smrg        VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28,
463f012e29Smrg        VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29,
473f012e29Smrg
483f012e29Smrg        VC4_PACKET_GL_INDEXED_PRIMITIVE = 32,
493f012e29Smrg        VC4_PACKET_GL_ARRAY_PRIMITIVE = 33,
503f012e29Smrg
513f012e29Smrg        VC4_PACKET_COMPRESSED_PRIMITIVE = 48,
523f012e29Smrg        VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49,
533f012e29Smrg
543f012e29Smrg        VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56,
553f012e29Smrg
563f012e29Smrg        VC4_PACKET_GL_SHADER_STATE = 64,
573f012e29Smrg        VC4_PACKET_NV_SHADER_STATE = 65,
583f012e29Smrg        VC4_PACKET_VG_SHADER_STATE = 66,
593f012e29Smrg
603f012e29Smrg        VC4_PACKET_CONFIGURATION_BITS = 96,
613f012e29Smrg        VC4_PACKET_FLAT_SHADE_FLAGS = 97,
623f012e29Smrg        VC4_PACKET_POINT_SIZE = 98,
633f012e29Smrg        VC4_PACKET_LINE_WIDTH = 99,
643f012e29Smrg        VC4_PACKET_RHT_X_BOUNDARY = 100,
653f012e29Smrg        VC4_PACKET_DEPTH_OFFSET = 101,
663f012e29Smrg        VC4_PACKET_CLIP_WINDOW = 102,
673f012e29Smrg        VC4_PACKET_VIEWPORT_OFFSET = 103,
683f012e29Smrg        VC4_PACKET_Z_CLIPPING = 104,
693f012e29Smrg        VC4_PACKET_CLIPPER_XY_SCALING = 105,
703f012e29Smrg        VC4_PACKET_CLIPPER_Z_SCALING = 106,
713f012e29Smrg
723f012e29Smrg        VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112,
733f012e29Smrg        VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113,
743f012e29Smrg        VC4_PACKET_CLEAR_COLORS = 114,
753f012e29Smrg        VC4_PACKET_TILE_COORDINATES = 115,
763f012e29Smrg
773f012e29Smrg        /* Not an actual hardware packet -- this is what we use to put
783f012e29Smrg         * references to GEM bos in the command stream, since we need the u32
793f012e29Smrg         * int the actual address packet in order to store the offset from the
803f012e29Smrg         * start of the BO.
813f012e29Smrg         */
823f012e29Smrg        VC4_PACKET_GEM_HANDLES = 254,
833f012e29Smrg} __attribute__ ((__packed__));
843f012e29Smrg
853f012e29Smrg#define VC4_PACKET_HALT_SIZE						1
863f012e29Smrg#define VC4_PACKET_NOP_SIZE						1
873f012e29Smrg#define VC4_PACKET_FLUSH_SIZE						1
883f012e29Smrg#define VC4_PACKET_FLUSH_ALL_SIZE					1
893f012e29Smrg#define VC4_PACKET_START_TILE_BINNING_SIZE				1
903f012e29Smrg#define VC4_PACKET_INCREMENT_SEMAPHORE_SIZE				1
913f012e29Smrg#define VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE				1
923f012e29Smrg#define VC4_PACKET_BRANCH_SIZE						5
933f012e29Smrg#define VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE				5
943f012e29Smrg#define VC4_PACKET_RETURN_FROM_SUB_LIST_SIZE				1
953f012e29Smrg#define VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE				1
963f012e29Smrg#define VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF_SIZE			1
973f012e29Smrg#define VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE			5
983f012e29Smrg#define VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE			5
993f012e29Smrg#define VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE			7
1003f012e29Smrg#define VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE			7
1013f012e29Smrg#define VC4_PACKET_GL_INDEXED_PRIMITIVE_SIZE				14
1023f012e29Smrg#define VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE				10
1033f012e29Smrg#define VC4_PACKET_COMPRESSED_PRIMITIVE_SIZE				1
1043f012e29Smrg#define VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE_SIZE			1
1053f012e29Smrg#define VC4_PACKET_PRIMITIVE_LIST_FORMAT_SIZE				2
1063f012e29Smrg#define VC4_PACKET_GL_SHADER_STATE_SIZE					5
1073f012e29Smrg#define VC4_PACKET_NV_SHADER_STATE_SIZE					5
1083f012e29Smrg#define VC4_PACKET_VG_SHADER_STATE_SIZE					5
1093f012e29Smrg#define VC4_PACKET_CONFIGURATION_BITS_SIZE				4
1103f012e29Smrg#define VC4_PACKET_FLAT_SHADE_FLAGS_SIZE				5
1113f012e29Smrg#define VC4_PACKET_POINT_SIZE_SIZE					5
1123f012e29Smrg#define VC4_PACKET_LINE_WIDTH_SIZE					5
1133f012e29Smrg#define VC4_PACKET_RHT_X_BOUNDARY_SIZE					3
1143f012e29Smrg#define VC4_PACKET_DEPTH_OFFSET_SIZE					5
1153f012e29Smrg#define VC4_PACKET_CLIP_WINDOW_SIZE					9
1163f012e29Smrg#define VC4_PACKET_VIEWPORT_OFFSET_SIZE					5
1173f012e29Smrg#define VC4_PACKET_Z_CLIPPING_SIZE					9
1183f012e29Smrg#define VC4_PACKET_CLIPPER_XY_SCALING_SIZE				9
1193f012e29Smrg#define VC4_PACKET_CLIPPER_Z_SCALING_SIZE				9
1203f012e29Smrg#define VC4_PACKET_TILE_BINNING_MODE_CONFIG_SIZE			16
1213f012e29Smrg#define VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE			11
1223f012e29Smrg#define VC4_PACKET_CLEAR_COLORS_SIZE					14
1233f012e29Smrg#define VC4_PACKET_TILE_COORDINATES_SIZE				3
1243f012e29Smrg#define VC4_PACKET_GEM_HANDLES_SIZE					9
1253f012e29Smrg
1263f012e29Smrg#define VC4_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low))
1273f012e29Smrg/* Using the GNU statement expression extension */
1283f012e29Smrg#define VC4_SET_FIELD(value, field)                                       \
1293f012e29Smrg        ({                                                                \
1303f012e29Smrg                uint32_t fieldval = (value) << field ## _SHIFT;		  \
1313f012e29Smrg                assert((fieldval & ~ field ## _MASK) == 0);               \
1323f012e29Smrg                fieldval & field ## _MASK;                                \
1333f012e29Smrg         })
1343f012e29Smrg
1353f012e29Smrg#define VC4_GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)
1363f012e29Smrg
1373f012e29Smrg/** @{
1383f012e29Smrg * Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
1393f012e29Smrg * VC4_PACKET_TILE_RENDERING_MODE_CONFIG.
1403f012e29Smrg*/
1413f012e29Smrg#define VC4_TILING_FORMAT_LINEAR    0
1423f012e29Smrg#define VC4_TILING_FORMAT_T         1
1433f012e29Smrg#define VC4_TILING_FORMAT_LT        2
1443f012e29Smrg/** @} */
1453f012e29Smrg
1463f012e29Smrg/** @{
1473f012e29Smrg *
1483f012e29Smrg * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and
1493f012e29Smrg * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER.
1503f012e29Smrg */
1513f012e29Smrg#define VC4_LOADSTORE_FULL_RES_EOF                     (1 << 3)
1523f012e29Smrg#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL       (1 << 2)
1533f012e29Smrg#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS              (1 << 1)
1543f012e29Smrg#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR           (1 << 0)
1553f012e29Smrg
1563f012e29Smrg/** @{
1573f012e29Smrg *
1583f012e29Smrg * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
1593f012e29Smrg * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address)
1603f012e29Smrg */
1613f012e29Smrg
1623f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_EOF                  (1 << 3)
1633f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2)
1643f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS      (1 << 1)
1653f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR   (1 << 0)
1663f012e29Smrg
1673f012e29Smrg/** @} */
1683f012e29Smrg
1693f012e29Smrg/** @{
1703f012e29Smrg *
1713f012e29Smrg * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
1723f012e29Smrg * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
1733f012e29Smrg */
1743f012e29Smrg#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15)
1753f012e29Smrg#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR     (1 << 14)
1763f012e29Smrg#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR  (1 << 13)
1773f012e29Smrg#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP         (1 << 12)
1783f012e29Smrg
1793f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK      VC4_MASK(9, 8)
1803f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT     8
1813f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_RGBA8888         0
1823f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER    1
1833f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_BGR565           2
1843f012e29Smrg/** @} */
1853f012e29Smrg
1863f012e29Smrg/** @{
1873f012e29Smrg *
1883f012e29Smrg * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
1893f012e29Smrg * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
1903f012e29Smrg */
1913f012e29Smrg#define VC4_STORE_TILE_BUFFER_MODE_MASK            VC4_MASK(7, 6)
1923f012e29Smrg#define VC4_STORE_TILE_BUFFER_MODE_SHIFT           6
1933f012e29Smrg#define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0         (0 << 6)
1943f012e29Smrg#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4     (1 << 6)
1953f012e29Smrg#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16    (2 << 6)
1963f012e29Smrg
1973f012e29Smrg/** The values of the field are VC4_TILING_FORMAT_* */
1983f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK      VC4_MASK(5, 4)
1993f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT     4
2003f012e29Smrg
2013f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK      VC4_MASK(2, 0)
2023f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT     0
2033f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_NONE             0
2043f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_COLOR            1
2053f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_ZS               2
2063f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_Z                3
2073f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_VG_MASK          4
2083f012e29Smrg#define VC4_LOADSTORE_TILE_BUFFER_FULL             5
2093f012e29Smrg/** @} */
2103f012e29Smrg
2113f012e29Smrg#define VC4_INDEX_BUFFER_U8                        (0 << 4)
2123f012e29Smrg#define VC4_INDEX_BUFFER_U16                       (1 << 4)
2133f012e29Smrg
2143f012e29Smrg/* This flag is only present in NV shader state. */
2153f012e29Smrg#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS         (1 << 3)
2163f012e29Smrg#define VC4_SHADER_FLAG_ENABLE_CLIPPING            (1 << 2)
2173f012e29Smrg#define VC4_SHADER_FLAG_VS_POINT_SIZE              (1 << 1)
2183f012e29Smrg#define VC4_SHADER_FLAG_FS_SINGLE_THREAD           (1 << 0)
2193f012e29Smrg
2203f012e29Smrg/** @{ byte 2 of config bits. */
2213f012e29Smrg#define VC4_CONFIG_BITS_EARLY_Z_UPDATE             (1 << 1)
2223f012e29Smrg#define VC4_CONFIG_BITS_EARLY_Z                    (1 << 0)
2233f012e29Smrg/** @} */
2243f012e29Smrg
2253f012e29Smrg/** @{ byte 1 of config bits. */
2263f012e29Smrg#define VC4_CONFIG_BITS_Z_UPDATE                   (1 << 7)
2273f012e29Smrg/** same values in this 3-bit field as PIPE_FUNC_* */
2283f012e29Smrg#define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT           4
2293f012e29Smrg#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE        (1 << 3)
2303f012e29Smrg
2313f012e29Smrg#define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO    (0 << 1)
2323f012e29Smrg#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD        (1 << 1)
2333f012e29Smrg#define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR         (2 << 1)
2343f012e29Smrg#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO       (3 << 1)
2353f012e29Smrg
2363f012e29Smrg#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT       (1 << 0)
2373f012e29Smrg/** @} */
2383f012e29Smrg
2393f012e29Smrg/** @{ byte 0 of config bits. */
2403f012e29Smrg#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE (0 << 6)
2413f012e29Smrg#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X   (1 << 6)
2423f012e29Smrg#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X  (2 << 6)
2433f012e29Smrg#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_MASK (3 << 6)
2443f012e29Smrg
2453f012e29Smrg#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES        (1 << 4)
2463f012e29Smrg#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET        (1 << 3)
2473f012e29Smrg#define VC4_CONFIG_BITS_CW_PRIMITIVES              (1 << 2)
2483f012e29Smrg#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK           (1 << 1)
2493f012e29Smrg#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT          (1 << 0)
2503f012e29Smrg/** @} */
2513f012e29Smrg
2523f012e29Smrg/** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */
2533f012e29Smrg#define VC4_BIN_CONFIG_DB_NON_MS                   (1 << 7)
2543f012e29Smrg
2553f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK       VC4_MASK(6, 5)
2563f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT      5
2573f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32         0
2583f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64         1
2593f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128        2
2603f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256        3
2613f012e29Smrg
2623f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK  VC4_MASK(4, 3)
2633f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_SHIFT 3
2643f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32    0
2653f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64    1
2663f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128   2
2673f012e29Smrg#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256   3
2683f012e29Smrg
2693f012e29Smrg#define VC4_BIN_CONFIG_AUTO_INIT_TSDA              (1 << 2)
2703f012e29Smrg#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT           (1 << 1)
2713f012e29Smrg#define VC4_BIN_CONFIG_MS_MODE_4X                  (1 << 0)
2723f012e29Smrg/** @} */
2733f012e29Smrg
2743f012e29Smrg/** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */
2753f012e29Smrg#define VC4_RENDER_CONFIG_DB_NON_MS                (1 << 12)
2763f012e29Smrg#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11)
2773f012e29Smrg#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G      (1 << 10)
2783f012e29Smrg#define VC4_RENDER_CONFIG_COVERAGE_MODE            (1 << 9)
2793f012e29Smrg#define VC4_RENDER_CONFIG_ENABLE_VG_MASK           (1 << 8)
2803f012e29Smrg
2813f012e29Smrg/** The values of the field are VC4_TILING_FORMAT_* */
2823f012e29Smrg#define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK       VC4_MASK(7, 6)
2833f012e29Smrg#define VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT      6
2843f012e29Smrg
2853f012e29Smrg#define VC4_RENDER_CONFIG_DECIMATE_MODE_1X         (0 << 4)
2863f012e29Smrg#define VC4_RENDER_CONFIG_DECIMATE_MODE_4X         (1 << 4)
2873f012e29Smrg#define VC4_RENDER_CONFIG_DECIMATE_MODE_16X        (2 << 4)
2883f012e29Smrg#define VC4_RENDER_CONFIG_DECIMATE_MODE_MASK       (3 << 4)
2893f012e29Smrg
2903f012e29Smrg#define VC4_RENDER_CONFIG_FORMAT_MASK              VC4_MASK(3, 2)
2913f012e29Smrg#define VC4_RENDER_CONFIG_FORMAT_SHIFT             2
2923f012e29Smrg#define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED   0
2933f012e29Smrg#define VC4_RENDER_CONFIG_FORMAT_RGBA8888          1
2943f012e29Smrg#define VC4_RENDER_CONFIG_FORMAT_BGR565            2
2953f012e29Smrg
2963f012e29Smrg#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT        (1 << 1)
2973f012e29Smrg#define VC4_RENDER_CONFIG_MS_MODE_4X               (1 << 0)
2983f012e29Smrg
2993f012e29Smrg#define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX         (1 << 4)
3003f012e29Smrg#define VC4_PRIMITIVE_LIST_FORMAT_32_XY            (3 << 4)
3013f012e29Smrg#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_POINTS      (0 << 0)
3023f012e29Smrg#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_LINES       (1 << 0)
3033f012e29Smrg#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES   (2 << 0)
3043f012e29Smrg#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT         (3 << 0)
3053f012e29Smrg
3063f012e29Smrgenum vc4_texture_data_type {
3073f012e29Smrg        VC4_TEXTURE_TYPE_RGBA8888 = 0,
3083f012e29Smrg        VC4_TEXTURE_TYPE_RGBX8888 = 1,
3093f012e29Smrg        VC4_TEXTURE_TYPE_RGBA4444 = 2,
3103f012e29Smrg        VC4_TEXTURE_TYPE_RGBA5551 = 3,
3113f012e29Smrg        VC4_TEXTURE_TYPE_RGB565 = 4,
3123f012e29Smrg        VC4_TEXTURE_TYPE_LUMINANCE = 5,
3133f012e29Smrg        VC4_TEXTURE_TYPE_ALPHA = 6,
3143f012e29Smrg        VC4_TEXTURE_TYPE_LUMALPHA = 7,
3153f012e29Smrg        VC4_TEXTURE_TYPE_ETC1 = 8,
3163f012e29Smrg        VC4_TEXTURE_TYPE_S16F = 9,
3173f012e29Smrg        VC4_TEXTURE_TYPE_S8 = 10,
3183f012e29Smrg        VC4_TEXTURE_TYPE_S16 = 11,
3193f012e29Smrg        VC4_TEXTURE_TYPE_BW1 = 12,
3203f012e29Smrg        VC4_TEXTURE_TYPE_A4 = 13,
3213f012e29Smrg        VC4_TEXTURE_TYPE_A1 = 14,
3223f012e29Smrg        VC4_TEXTURE_TYPE_RGBA64 = 15,
3233f012e29Smrg        VC4_TEXTURE_TYPE_RGBA32R = 16,
3243f012e29Smrg        VC4_TEXTURE_TYPE_YUV422R = 17,
3253f012e29Smrg};
3263f012e29Smrg
3273f012e29Smrg#define VC4_TEX_P0_OFFSET_MASK                     VC4_MASK(31, 12)
3283f012e29Smrg#define VC4_TEX_P0_OFFSET_SHIFT                    12
3293f012e29Smrg#define VC4_TEX_P0_CSWIZ_MASK                      VC4_MASK(11, 10)
3303f012e29Smrg#define VC4_TEX_P0_CSWIZ_SHIFT                     10
3313f012e29Smrg#define VC4_TEX_P0_CMMODE_MASK                     VC4_MASK(9, 9)
3323f012e29Smrg#define VC4_TEX_P0_CMMODE_SHIFT                    9
3333f012e29Smrg#define VC4_TEX_P0_FLIPY_MASK                      VC4_MASK(8, 8)
3343f012e29Smrg#define VC4_TEX_P0_FLIPY_SHIFT                     8
3353f012e29Smrg#define VC4_TEX_P0_TYPE_MASK                       VC4_MASK(7, 4)
3363f012e29Smrg#define VC4_TEX_P0_TYPE_SHIFT                      4
3373f012e29Smrg#define VC4_TEX_P0_MIPLVLS_MASK                    VC4_MASK(3, 0)
3383f012e29Smrg#define VC4_TEX_P0_MIPLVLS_SHIFT                   0
3393f012e29Smrg
3403f012e29Smrg#define VC4_TEX_P1_TYPE4_MASK                      VC4_MASK(31, 31)
3413f012e29Smrg#define VC4_TEX_P1_TYPE4_SHIFT                     31
3423f012e29Smrg#define VC4_TEX_P1_HEIGHT_MASK                     VC4_MASK(30, 20)
3433f012e29Smrg#define VC4_TEX_P1_HEIGHT_SHIFT                    20
3443f012e29Smrg#define VC4_TEX_P1_ETCFLIP_MASK                    VC4_MASK(19, 19)
3453f012e29Smrg#define VC4_TEX_P1_ETCFLIP_SHIFT                   19
3463f012e29Smrg#define VC4_TEX_P1_WIDTH_MASK                      VC4_MASK(18, 8)
3473f012e29Smrg#define VC4_TEX_P1_WIDTH_SHIFT                     8
3483f012e29Smrg
3493f012e29Smrg#define VC4_TEX_P1_MAGFILT_MASK                    VC4_MASK(7, 7)
3503f012e29Smrg#define VC4_TEX_P1_MAGFILT_SHIFT                   7
3513f012e29Smrg# define VC4_TEX_P1_MAGFILT_LINEAR                 0
3523f012e29Smrg# define VC4_TEX_P1_MAGFILT_NEAREST                1
3533f012e29Smrg
3543f012e29Smrg#define VC4_TEX_P1_MINFILT_MASK                    VC4_MASK(6, 4)
3553f012e29Smrg#define VC4_TEX_P1_MINFILT_SHIFT                   4
3563f012e29Smrg# define VC4_TEX_P1_MINFILT_LINEAR                 0
3573f012e29Smrg# define VC4_TEX_P1_MINFILT_NEAREST                1
3583f012e29Smrg# define VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR          2
3593f012e29Smrg# define VC4_TEX_P1_MINFILT_NEAR_MIP_LIN           3
3603f012e29Smrg# define VC4_TEX_P1_MINFILT_LIN_MIP_NEAR           4
3613f012e29Smrg# define VC4_TEX_P1_MINFILT_LIN_MIP_LIN            5
3623f012e29Smrg
3633f012e29Smrg#define VC4_TEX_P1_WRAP_T_MASK                     VC4_MASK(3, 2)
3643f012e29Smrg#define VC4_TEX_P1_WRAP_T_SHIFT                    2
3653f012e29Smrg#define VC4_TEX_P1_WRAP_S_MASK                     VC4_MASK(1, 0)
3663f012e29Smrg#define VC4_TEX_P1_WRAP_S_SHIFT                    0
3673f012e29Smrg# define VC4_TEX_P1_WRAP_REPEAT                    0
3683f012e29Smrg# define VC4_TEX_P1_WRAP_CLAMP                     1
3693f012e29Smrg# define VC4_TEX_P1_WRAP_MIRROR                    2
3703f012e29Smrg# define VC4_TEX_P1_WRAP_BORDER                    3
3713f012e29Smrg
3723f012e29Smrg#define VC4_TEX_P2_PTYPE_MASK                      VC4_MASK(31, 30)
3733f012e29Smrg#define VC4_TEX_P2_PTYPE_SHIFT                     30
3743f012e29Smrg# define VC4_TEX_P2_PTYPE_IGNORED                  0
3753f012e29Smrg# define VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE          1
3763f012e29Smrg# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS   2
3773f012e29Smrg# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS      3
3783f012e29Smrg
3793f012e29Smrg/* VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE bits */
3803f012e29Smrg#define VC4_TEX_P2_CMST_MASK                       VC4_MASK(29, 12)
3813f012e29Smrg#define VC4_TEX_P2_CMST_SHIFT                      12
3823f012e29Smrg#define VC4_TEX_P2_BSLOD_MASK                      VC4_MASK(0, 0)
3833f012e29Smrg#define VC4_TEX_P2_BSLOD_SHIFT                     0
3843f012e29Smrg
3853f012e29Smrg/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS */
3863f012e29Smrg#define VC4_TEX_P2_CHEIGHT_MASK                    VC4_MASK(22, 12)
3873f012e29Smrg#define VC4_TEX_P2_CHEIGHT_SHIFT                   12
3883f012e29Smrg#define VC4_TEX_P2_CWIDTH_MASK                     VC4_MASK(10, 0)
3893f012e29Smrg#define VC4_TEX_P2_CWIDTH_SHIFT                    0
3903f012e29Smrg
3913f012e29Smrg/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS */
3923f012e29Smrg#define VC4_TEX_P2_CYOFF_MASK                      VC4_MASK(22, 12)
3933f012e29Smrg#define VC4_TEX_P2_CYOFF_SHIFT                     12
3943f012e29Smrg#define VC4_TEX_P2_CXOFF_MASK                      VC4_MASK(10, 0)
3953f012e29Smrg#define VC4_TEX_P2_CXOFF_SHIFT                     0
3963f012e29Smrg
3973f012e29Smrg#endif /* VC4_PACKET_H */
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