ChangeLog revision 504d986f
1504d986fSmrgcommit a00032050873fc99f3ceaa3293468dad1d94d4b1 2504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 3504d986fSmrgDate: Thu Nov 17 15:17:10 2016 +0900 4504d986fSmrg 5504d986fSmrg Bump version for 1.2.0 release 6504d986fSmrg 7504d986fSmrgcommit a446b3af9b055056e9fb0f37069b08b979eba277 8504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 9504d986fSmrgDate: Thu Nov 17 15:13:59 2016 +0900 10504d986fSmrg 11504d986fSmrg manpage updates for the 1.2.0 release 12504d986fSmrg 13504d986fSmrg Option "TearFree" is now effective for arbitrary transforms as well. 14504d986fSmrg 15504d986fSmrg Point to the amd-gfx mailing list instead of xorg-driver-ati. 16504d986fSmrg 17504d986fSmrgcommit 24e36c7044a24294d5709c0306efacc8de6df072 18504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 19504d986fSmrgDate: Thu Nov 10 12:30:10 2016 +0900 20504d986fSmrg 21504d986fSmrg Use pAMDGPUEnt to find both screens of a GPU in amdgpu_mode_hotplug 22504d986fSmrg 23504d986fSmrg Fixes misbehaviour when hotplugging DisplayPort connectors on secondary 24504d986fSmrg GPUs. 25504d986fSmrg 26504d986fSmrg Fixes: 14606e127f4b ("Handle Zaphod mode correctly in amdgpu_mode_hotplug") 27504d986fSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98626 28504d986fSmrg (Ported from radeon commit 9760ef33cba5795eddeda4d5c2fcbe2dcce21689) 29504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 30504d986fSmrg 31504d986fSmrgcommit 257be5b0853814a557a5337878a4311acbc89856 32504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 33504d986fSmrgDate: Thu Nov 10 12:28:03 2016 +0900 34504d986fSmrg 35504d986fSmrg Refactor amdgpu_mode_hotplug 36504d986fSmrg 37504d986fSmrg Preparation for the next change, no functional change intended. 38504d986fSmrg 39504d986fSmrg (Cherry picked from radeon commit 35bec4937d89b48a79acfcb4f814b7370cb631b2) 40504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 41504d986fSmrg 42504d986fSmrgcommit 1352a1d2f78cb0433d421ef86bfce2a5a1646807 43504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 44504d986fSmrgDate: Wed Nov 2 12:35:55 2016 +0900 45504d986fSmrg 46504d986fSmrg Check Xorg version at runtime instead of build time in two places 47504d986fSmrg 48504d986fSmrg This means that all possible paths can be handled as intended, no matter 49504d986fSmrg which Xorg version the driver happened to be compiled against. 50504d986fSmrg 51504d986fSmrg (Ported from radeon commit 350a2645a1b127227ff294c0b62d20000d0fd48a) 52504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 53504d986fSmrg 54504d986fSmrgcommit 5da43c5da8adc139d57d89975a52eef91a5595e1 55504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 56504d986fSmrgDate: Tue Nov 1 16:01:24 2016 +0900 57504d986fSmrg 58504d986fSmrg Require xserver 1.10 or newer 59504d986fSmrg 60504d986fSmrg 1.10.0 was released in February 2011. 61504d986fSmrg 62504d986fSmrg We've been accidentally requiring 1.10 or newer since c7d27c94cb65 ("Keep 63504d986fSmrg track of damage event related flushes per-client"). 64504d986fSmrg 65504d986fSmrg (Ported from radeon commit 5df36de39952c3a26cb2fbc125f298139a9dd5bc) 66504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 67504d986fSmrg 68504d986fSmrgcommit dd4a740714e481b09312a04883aa6e0f5200ca81 69504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 70504d986fSmrgDate: Thu Oct 27 11:22:36 2016 +0900 71504d986fSmrg 72504d986fSmrg present: Check tiling info for flips 73504d986fSmrg 74504d986fSmrg The kernel driver doesn't handle flipping between buffers with 75504d986fSmrg different tiling parameters correctly. 76504d986fSmrg 77504d986fSmrg Fixes display corruption with fullscreen apps using different tiling 78504d986fSmrg modes (e.g. due to R600_DEBUG=notiling or R600_DEBUG=no2d) via DRI3. 79504d986fSmrg 80504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 81504d986fSmrg 82504d986fSmrgcommit 3c1f4386ba7d0b6c16bdd2b2178f978f2f154ba8 83504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 84504d986fSmrgDate: Wed Oct 26 16:19:01 2016 +0900 85504d986fSmrg 86504d986fSmrg Consume all available udev events at once 87504d986fSmrg 88504d986fSmrg We get multiple udev events for actions like docking a laptop into its 89504d986fSmrg station or plugging a monitor to the station. By consuming as many 90504d986fSmrg events as we can, we reduce the number of output re-evalutions. 91504d986fSmrg 92504d986fSmrg It depends on the timing how many events can be consumed at once. 93504d986fSmrg 94504d986fSmrg (Inspired by xserver commit 363f4273dd4aec3e26cc57ecb6c20f27e6c813d8) 95504d986fSmrg (Ported from radeon commit 22b5ce9548393ba2ff73ee234ecd82eeaf0ef6c4) 96504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 97504d986fSmrg 98504d986fSmrgcommit c87dff3257e797cfd80d208c9a612b21978ff4eb 99504d986fSmrgAuthor: Hans de Goede <hdegoede@redhat.com> 100504d986fSmrgDate: Wed Oct 26 16:17:04 2016 +0900 101504d986fSmrg 102504d986fSmrg PRIME: Fix swapping of provider sink / source capabilities 103504d986fSmrg 104504d986fSmrg When a card has import capability it can be an offload _sink_, not a 105504d986fSmrg source and vice versa for export capability. 106504d986fSmrg 107504d986fSmrg This went unnoticed sofar because most gpus have both import and export 108504d986fSmrg capability. 109504d986fSmrg 110504d986fSmrg Signed-off-by: Hans de Goede <hdegoede@redhat.com> 111504d986fSmrg (Ported from xserver commit 94a1c77259ce39ba59ad87615df39b570ffab435) 112504d986fSmrg (Ported from radeon commit 82d3c8f5500d2a6fb1495e217a0b79c396f1534c) 113504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 114504d986fSmrg 115504d986fSmrgcommit 9c4416422f2d07dbfa7c0b18beb1353f122fc1a1 116504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 117504d986fSmrgDate: Wed Oct 26 16:15:42 2016 +0900 118504d986fSmrg 119504d986fSmrg Always call PixmapStopDirtyTracking in drmmode_set_scanout_pixmap 120504d986fSmrg 121504d986fSmrg Otherwise, we may leak screen->pixmap_dirty_list entries if 122504d986fSmrg drmmode_set_scanout_pixmap is called repatedly with ppix != NULL, which 123504d986fSmrg can happen from RRReplaceScanoutPixmap. 124504d986fSmrg 125504d986fSmrg (Inspired by xserver commit b773a9c8126222e5fed2904d012fbf917a9f22fd) 126504d986fSmrg (Ported from radeon commit 6c940446ddadf418ee4959e46fa552b6c1cf6704) 127504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 128504d986fSmrg 129504d986fSmrgcommit 0a91f11c03400e3f92a2b048505f39e7de7e87fc 130504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 131504d986fSmrgDate: Wed Oct 26 16:14:45 2016 +0900 132504d986fSmrg 133504d986fSmrg Don't rely on randr_crtc->scanout_pixmap in drmmode_set_scanout_pixmap 134504d986fSmrg 135504d986fSmrg RRReplaceScanoutPixmap may set randr_crtc->scanout_pixmap = NULL before 136504d986fSmrg we get here. 137504d986fSmrg 138504d986fSmrg (Inspired by xserver commit f4c37eeee7953df1fe0e3196eda452acf0078e61) 139504d986fSmrg v2: Always return TRUE in the if (!ppix) block. 140504d986fSmrg (Cherry picked from radeon commit 61df12e2377cbb19a19ca9d5624df8959822da9f) 141504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 142504d986fSmrg 143504d986fSmrgcommit b37f4774880bfd0cbe50273ac0d9c539d81995f9 144504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 145504d986fSmrgDate: Tue Oct 25 16:30:46 2016 +0900 146504d986fSmrg 147504d986fSmrg Sayōnara, AM_MAINTAINER_MODE! 148504d986fSmrg 149504d986fSmrg If --enable-maintainer-mode got lost from config.status for any reason, 150504d986fSmrg builds would fail in mysterious ways after changing between different 151504d986fSmrg Git commits. 152504d986fSmrg 153504d986fSmrg There are more reasons for dropping it in the automake manual: 154504d986fSmrg 155504d986fSmrg https://www.gnu.org/software/automake/manual/html_node/maintainer_002dmode.html 156504d986fSmrg 157504d986fSmrg I'm not aware of any reason why --disable-maintainer-mode would ever be 158504d986fSmrg useful with this project. 159504d986fSmrg 160504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 161504d986fSmrg (Cherry picked from radeon commit 49cf3b5032a7ce40afe514b7092440e3e19e05aa) 162504d986fSmrg 163504d986fSmrgcommit c8d9ad0e188d3da3a35006a00536d61e23305830 164504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 165504d986fSmrgDate: Wed Oct 19 18:16:47 2016 +0900 166504d986fSmrg 167504d986fSmrg Order unique chipsets according to first appearance in ati_pciids.csv 168504d986fSmrg 169504d986fSmrg Instead of lexically. This makes it more likely for similar generations 170504d986fSmrg to be close to each other in the list of unique chipsets. 171504d986fSmrg 172504d986fSmrg (Ported from radeon commit 1ce1b1656acc6211deb2091ff7f28d51b6daf86b, 173504d986fSmrg plus change $numunique++ => ++$numunique to fix OLAND getting listed 174504d986fSmrg twice) 175504d986fSmrg 176504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 177504d986fSmrg 178504d986fSmrgcommit 7cc04035c55788261cda89a915c433c2add6cad9 179504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 180504d986fSmrgDate: Wed Sep 28 15:59:22 2016 +0900 181504d986fSmrg 182504d986fSmrg Enable HW cursor support with PRIME slave output & Xorg > 1.18.99.901 183504d986fSmrg 184504d986fSmrg Supported since Xorg 1.18.99.2, but buggy until 1.18.99.901. 185504d986fSmrg 186504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 187504d986fSmrg 188504d986fSmrgcommit d42773eb45baff5933730e26878a0b45fcf07b65 189504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 190504d986fSmrgDate: Wed Sep 28 18:17:53 2016 +0900 191504d986fSmrg 192504d986fSmrg Rotate and reflect cursor hotspot position for drmModeSetCursor2 193504d986fSmrg 194504d986fSmrg We were always passing the hotspot position in the X screen coordinate 195504d986fSmrg space, but drmModeSetCursor2 needs it in the CRTC coordinate space. The 196504d986fSmrg wrong hotspot position would cause the kernel driver to adjust the 197504d986fSmrg HW cursor position incorrectly when the hotspot position changed. 198504d986fSmrg 199504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 200504d986fSmrg 201504d986fSmrgcommit bdee9f4dd4f21015e7696e06c4b485ab2b3a16dc 202504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 203504d986fSmrgDate: Wed Aug 31 16:46:56 2016 +0900 204504d986fSmrg 205504d986fSmrg Add support for ScreenPtr::SyncSharedPixmap 206504d986fSmrg 207504d986fSmrg This allows deferring shared pixmap updates between different drivers. 208504d986fSmrg 209504d986fSmrg (Ported from radeon commit 53be26b00e83f871f0afd39caa5a7a1d6ec4aea1) 210504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 211504d986fSmrg 212504d986fSmrgcommit 97d7386caf7ba53d2cf398b8a9bb65d0a2a4770a 213504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 214504d986fSmrgDate: Fri Sep 16 16:36:23 2016 +0900 215504d986fSmrg 216504d986fSmrg Untangle HAS_XORG_CONF_DIR / --with-xorg-conf-dir lines in configure.ac 217504d986fSmrg 218504d986fSmrg $sysconfigdir used to be part of the default --with-xorg-conf-dir value, 219504d986fSmrg but it no longer is. 220504d986fSmrg 221504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 222504d986fSmrg 223504d986fSmrgcommit aa8a3fa2468094cd37959179e8417ba7ba0a326c 224504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 225504d986fSmrgDate: Fri Sep 16 15:59:16 2016 +0900 226504d986fSmrg 227504d986fSmrg Fix handling of configure option --with-xorg-conf-dir 228504d986fSmrg 229504d986fSmrg There were two problems: 230504d986fSmrg 231504d986fSmrg I accidentally changed the variable name in the AC_ARG_WITH stanza from 232504d986fSmrg configdir to xorgconfigdir, so specifying --with-xorg-conf-dir wouldn't 233504d986fSmrg work correctly. Fix this back to configdir. 234504d986fSmrg 235504d986fSmrg If neither --with-xorg-conf-dir nor --prefix is specified on the command 236504d986fSmrg line, the $prefix variable doesn't contain "/usr/local" (the default 237504d986fSmrg prefix) yet at this point but "NONE". So make install would attempt to 238504d986fSmrg install 10-amdgpu.conf in ${DESTDIR}NONE/share/X11/xorg.conf.d/ . Fix 239504d986fSmrg this by leaving ${prefix} verbatim in the default value, to be resolved 240504d986fSmrg by make. 241504d986fSmrg 242504d986fSmrg Also print the configdir value along with the values of other similar 243504d986fSmrg configuration variables. 244504d986fSmrg 245504d986fSmrg Reported-by: Timo Aaltonen <tjaalton@debian.org> 246504d986fSmrg Reviewed-by: Julien Cristau <jcristau@debian.org> 247504d986fSmrg 248504d986fSmrgcommit cd3acb75718dfd42dd25d58b4e7bd4db27b659d8 249504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 250504d986fSmrgDate: Wed Sep 14 18:33:42 2016 +0900 251504d986fSmrg 252504d986fSmrg Use --with-xorg-conf-dir=$prefix/share/X11/xorg.conf.d by default 253504d986fSmrg 254504d986fSmrg We were using the result of `pkg-config --variable=sysconfigdir 255504d986fSmrg xorg-server` before, which may not be inside $prefix, so make install 256504d986fSmrg might fail for 10-amdgpu.conf . 257504d986fSmrg 258504d986fSmrg Fixes make distcheck in that case, and possibly also 10-amdgpu.conf 259504d986fSmrg seemingly missing from some distribution packages. 260504d986fSmrg 261504d986fSmrg This matches what some (though not all) input drivers are doing for their 262504d986fSmrg xorg.conf.d snippets. 263504d986fSmrg 264504d986fSmrgcommit 0f8df8584ad61a3e47fe303b34cd7b0c4ed08bb0 265504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 266504d986fSmrgDate: Thu Sep 8 18:14:49 2016 +0900 267504d986fSmrg 268504d986fSmrg Make TearFree effective with PRIME slave scanout 269504d986fSmrg 270504d986fSmrg TearFree can now prevent tearing with any possible display 271504d986fSmrg configuration. 272504d986fSmrg 273504d986fSmrg Note that there may still be inter-GPU tearing if the primary GPU uses 274504d986fSmrg a different driver. 275504d986fSmrg 276504d986fSmrg (Ported from radeon commit 38797a33117222dadbc89e5f21ed8cd5deef9bea) 277504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 278504d986fSmrg 279504d986fSmrgcommit d6feed2cd78fe879aba4860a6d9bc2e388b9f135 280504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 281504d986fSmrgDate: Thu Sep 8 17:56:24 2016 +0900 282504d986fSmrg 283504d986fSmrg Synchronize scanout pixmaps for TearFree 284504d986fSmrg 285504d986fSmrg Copy the damaged areas which are still valid in the other scanout pixmap 286504d986fSmrg from there, then only copy the remaining damaged area from the screen 287504d986fSmrg pixmap. 288504d986fSmrg 289504d986fSmrg This is slightly more efficient (only needs one Damage record instead of 290504d986fSmrg two, and only needs to copy each screen update across PCIe once with 291504d986fSmrg ShadowPrimary and a discrete GPU), and will be significantly more 292504d986fSmrg efficient for PRIME with the following change. 293504d986fSmrg 294504d986fSmrg (Ported from radeon commit eda1f3df6aaed683036369fe8820da4dac3c2ae2) 295504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 296504d986fSmrg 297504d986fSmrgcommit 4927b84ec84bc0cb5055686cca6be54390f82803 298504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 299504d986fSmrgDate: Thu Sep 8 17:52:25 2016 +0900 300504d986fSmrg 301504d986fSmrg Move up amdgpu_scanout_extents_intersect 302504d986fSmrg 303504d986fSmrg Will be needed higher up by the following changes. No functional change. 304504d986fSmrg 305504d986fSmrg (Ported from radeon commit 2f6e5fb15f1a9ce523c85550e493f8bda9d0c00f) 306504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 307504d986fSmrg 308504d986fSmrgcommit 1c725f63961746258f6138b47037ec18bf508d78 309504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 310504d986fSmrgDate: Thu Sep 8 17:45:32 2016 +0900 311504d986fSmrg 312504d986fSmrg Factor out transform_region helper 313504d986fSmrg 314504d986fSmrg (Ported from radeon commit 5a57005178fc13b6f7e513458ca6dae72a3e5783) 315504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 316504d986fSmrg 317504d986fSmrgcommit c92842764f95fa09e145d81f80e9fa39ea8c453c 318504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 319504d986fSmrgDate: Thu Sep 8 17:26:18 2016 +0900 320504d986fSmrg 321504d986fSmrg Only copy from screen pixmap to shared pixmap on demand for slave scanout 322504d986fSmrg 323504d986fSmrg Only copy once for each time we update the corresponding scanout pixmap. 324504d986fSmrg This can significantly reduce the bandwidth usage when there are 325504d986fSmrg frequent updates to the screen pixmap. 326504d986fSmrg 327504d986fSmrg This initial implementation only works when both the master and slave 328504d986fSmrg screens use this driver. 329504d986fSmrg 330504d986fSmrg (Ported from radeon commit 99232f64db52812a843cd616d263d3a6b90eef3d) 331504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 332504d986fSmrg 333504d986fSmrgcommit 61ceefe17fe9e6ffbaaad0e216b2bd37fd39f47d 334504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 335504d986fSmrgDate: Thu Sep 8 17:15:03 2016 +0900 336504d986fSmrg 337504d986fSmrg Track damage accurately for RandR 1.4 slave scanout 338504d986fSmrg 339504d986fSmrg This further reduces the PCIe bandwidth usage. 340504d986fSmrg 341504d986fSmrg (Ported from radeon commit b0867063abb197b9134166706d99fcbe5f204bb5, 342504d986fSmrg plus leak fix from 5a57005178fc13b6f7e513458ca6dae72a3e5783) 343504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 344504d986fSmrg 345504d986fSmrgcommit 6d31fb124d4418e64c949bde9ed1facf95967762 346504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 347504d986fSmrgDate: Thu Sep 8 17:04:05 2016 +0900 348504d986fSmrg 349504d986fSmrg Handle RandR 1.4 slave dirty updates via amdgpu_drm_queue 350504d986fSmrg 351504d986fSmrg This reduces PCIe bandwidth usage and tearing. 352504d986fSmrg 353504d986fSmrg (Ported from radeon commit ad0a0656dd0e74683e6d7789decba827aa29c221) 354504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 355504d986fSmrg 356504d986fSmrgcommit b10ecdbd89b0a60a990c78c3e53bab6c4c96fe9f 357504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 358504d986fSmrgDate: Thu Sep 8 16:48:59 2016 +0900 359504d986fSmrg 360504d986fSmrg Use drmmode_crtc_scanout_* helpers for RandR 1.4 scanout pixmaps 361504d986fSmrg 362504d986fSmrg This should allow using multiple CRTCs via RandR 1.4 even with xserver 363504d986fSmrg < 1.17. It also simplifies the code a little, and paves the way for 364504d986fSmrg following changes. 365504d986fSmrg 366504d986fSmrg (Ported from radeon commits 4cfa4615f79f64062e5e771cd45dd7048f48b4f6 367504d986fSmrg and a92c27484703abc7c410b6ae0e4b8d1efbbb8e6f) 368504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 369504d986fSmrg 370504d986fSmrgcommit 9565981f751b0884cbfa885b8f3af3d41a965a2b 371504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 372504d986fSmrgDate: Wed Sep 7 18:49:54 2016 +0900 373504d986fSmrg 374504d986fSmrg Wait for pending flips to complete before turning off an output or CRTC 375504d986fSmrg 376504d986fSmrg At least with older kernels, the flip may never complete otherwise, 377504d986fSmrg which can result in us hanging in drmmode_set_mode_major. 378504d986fSmrg 379504d986fSmrg Fixes: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-ati/+bug/1577170 380504d986fSmrg 381504d986fSmrg (Ported from radeon commits 9090309e057dc703d1a5bffd88e6cae14108cfc3, 382504d986fSmrg e520ce0ec0adf91ddce5c932d4b3f9477fd49304, 383504d986fSmrg a36fdaff40d5b4795a1400c348a80eee94892212 and 384504d986fSmrg 4bd2d01552f18153afa03a8947b22eebf3d67c6b) 385504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 386504d986fSmrg 387504d986fSmrgcommit c7d27c94cb656899746898c2e55407c3e3d7cdc8 388504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 389504d986fSmrgDate: Wed Sep 7 18:28:23 2016 +0900 390504d986fSmrg 391504d986fSmrg Keep track of damage event related flushes per-client 392504d986fSmrg 393504d986fSmrg This further reduces the compositing slowdown due to flushing overhead, 394504d986fSmrg by only flushing when the X server actually sends XDamageNotify events 395504d986fSmrg to a client, and there hasn't been a flush yet in the meantime. 396504d986fSmrg 397504d986fSmrg (Ported from radeon commit 121a6de72da5fcf9a32408eff36b2235f3dfbcfe) 398504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 399504d986fSmrg 400504d986fSmrgcommit 58773d1945cfa8155d8a6c5eb3f95097535604ef 401504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 402504d986fSmrgDate: Wed Sep 7 18:14:10 2016 +0900 403504d986fSmrg 404504d986fSmrg Use EventCallback to avoid flushing every time in the FlushCallback 405504d986fSmrg 406504d986fSmrg We only need to flush for XDamageNotify events. 407504d986fSmrg 408504d986fSmrg Significantly reduces compositing slowdown due to flushing overhead, in 409504d986fSmrg particular with glamor. 410504d986fSmrg 411504d986fSmrg (Ported from radeon commit 9a1afbf61fbb2827c86bd86d295fa0848980d60b) 412504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 413504d986fSmrg 414504d986fSmrgcommit d166d04f6951f6a48d7d5ce5d31bba857fe0cb06 415504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 416504d986fSmrgDate: Wed Sep 7 18:03:05 2016 +0900 417504d986fSmrg 418504d986fSmrg Add explicit AMDGPU_DRM_QUEUE_ERROR define 419504d986fSmrg 420504d986fSmrg Should make the amdgpu_drm_queue_alloc error handling clearer, and gets 421504d986fSmrg rid of a compile warning about it returning NULL. 422504d986fSmrg 423504d986fSmrg (Ported from radeon commit a37af701768b12d86868a831a79f1e02ee4968cf) 424504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 425504d986fSmrg 426504d986fSmrgcommit 6a1ba044c2b71081e6060d0c096917d6238f2145 427504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 428504d986fSmrgDate: Mon Aug 29 16:43:59 2016 +0900 429504d986fSmrg 430504d986fSmrg Only list each unique chipset family once in the log file 431504d986fSmrg 432504d986fSmrg Acked-by: Christian König <christian.koenig@amd.com> 433504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 434504d986fSmrg 435504d986fSmrgcommit 7d050d15d49ef25e86e7abe88dafb52370715640 436504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 437504d986fSmrgDate: Mon Aug 29 16:13:20 2016 +0900 438504d986fSmrg 439504d986fSmrg Add missing Kaveri PCI ID (1318) 440504d986fSmrg 441504d986fSmrg Found by comparing src/pcidb/ati_pciids.csv with xf86-video-ati. 442504d986fSmrg 443504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 444504d986fSmrg 445504d986fSmrgcommit aa5492660958e359bdc2107cba9a211ff988c90e 446504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 447504d986fSmrgDate: Mon Aug 29 15:52:48 2016 +0900 448504d986fSmrg 449504d986fSmrg Add Mullins PCI IDs 450504d986fSmrg 451504d986fSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97472 452504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 453504d986fSmrg 454504d986fSmrgcommit 73c8dc000ad6b2b53ba3aa7155f5e8f6b55623b7 455504d986fSmrgAuthor: Qiang Yu <Qiang.Yu@amd.com> 456504d986fSmrgDate: Mon Aug 22 19:13:26 2016 +0800 457504d986fSmrg 458504d986fSmrg DRI2: Fix amdgpu_dri2_exchange_buffers width/height copy'n'paste error 459504d986fSmrg 460504d986fSmrg Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> 461504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 462504d986fSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 463504d986fSmrg 464504d986fSmrgcommit 5a4d3267ac3823fe58b51b0b9075b82375d7180c 465504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 466504d986fSmrgDate: Wed Aug 17 18:57:01 2016 +0900 467504d986fSmrg 468504d986fSmrg Remove unused lut_r/g/b arrays from drmmode_crtc_private_rec 469504d986fSmrg 470504d986fSmrg Fixes: 1091f28e1fa2 ("Remove drmmode_load_palette") 471504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 472504d986fSmrg 473504d986fSmrgcommit c4364520691d18961f0a6b77071baeeffaa80a11 474504d986fSmrgAuthor: Marek Olšák <marek.olsak@amd.com> 475504d986fSmrgDate: Fri Aug 19 12:42:38 2016 +0200 476504d986fSmrg 477504d986fSmrg Fix cursor size for SI 478504d986fSmrg 479504d986fSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 480504d986fSmrg Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> 481504d986fSmrg 482504d986fSmrgcommit 2eb5d77b841e55e7328df4b95c0d41fec30ce10f 483504d986fSmrgAuthor: Ronie Salgado <roniesalg@gmail.com> 484504d986fSmrgDate: Thu Feb 11 03:00:14 2016 -0300 485504d986fSmrg 486504d986fSmrg Add SI PCI IDs 487504d986fSmrg 488504d986fSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 489504d986fSmrg 490504d986fSmrgcommit abd1a7901c95e4bc78415cf1b7923623b9177152 491504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 492504d986fSmrgDate: Wed Jun 29 17:54:26 2016 +0900 493504d986fSmrg 494504d986fSmrg DRI2: Add interpolated_vblanks in amdgpu_dri2_get_crtc_msc 495504d986fSmrg 496504d986fSmrg We need that in amdgpu_dri2_drawable_crtc as well for priv->vblank_delta 497504d986fSmrg to work as intended. 498504d986fSmrg 499504d986fSmrg amdgpu_dri2_get_msc was already doing this. 500504d986fSmrg 501504d986fSmrg Fixes hangs in some cases when using VDPAU via DRI2 and moving the 502504d986fSmrg window between CRTCs. 503504d986fSmrg 504504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 505504d986fSmrg 506504d986fSmrgcommit 978242977e5dc905e1d5a46b1b0d34b356c7af26 507504d986fSmrgAuthor: Qiang Yu <Qiang.Yu@amd.com> 508504d986fSmrgDate: Wed Jul 13 19:25:12 2016 +0800 509504d986fSmrg 510504d986fSmrg Fix amdgpu_mode_hotplug crash on multi GPU platform. 511504d986fSmrg 512504d986fSmrg On multi GPU platform, some screen is created by other GPU DDX. 513504d986fSmrg 514504d986fSmrg Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> 515504d986fSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 516504d986fSmrg 517504d986fSmrgcommit fdd1209e26128b3e894f2867fac3a1b08fe1f29e 518504d986fSmrgAuthor: Keith Packard <keithp@keithp.com> 519504d986fSmrgDate: Tue Jul 19 09:16:32 2016 -0700 520504d986fSmrg 521504d986fSmrg Use NotifyFd for drm fd 522504d986fSmrg 523504d986fSmrg NotifyFd is available after API 22, and must be used after API 23. 524504d986fSmrg 525504d986fSmrg Signed-off-by: Keith Packard <keithp@keithp.com> 526504d986fSmrg 527504d986fSmrgcommit 17c0cf49746a20fb25610c24a40c441f88c08365 528504d986fSmrgAuthor: Adam Jackson <ajax@redhat.com> 529504d986fSmrgDate: Tue Jul 19 10:03:56 2016 -0400 530504d986fSmrg 531504d986fSmrg Adapt Block/WakeupHandler signature for ABI 23 532504d986fSmrg 533504d986fSmrg Signed-off-by: Adam Jackson <ajax@redhat.com> 534504d986fSmrg 535504d986fSmrgcommit b5e2b964b7884c205a7c0fa578e05e867c176fcc 536504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 537504d986fSmrgDate: Wed Jul 6 17:46:56 2016 +0900 538504d986fSmrg 539504d986fSmrg Only use RandR APIs if RandR is enabled 540504d986fSmrg 541504d986fSmrg Fixes crash with Xinerama enabled, which disables RandR. 542504d986fSmrg 543504d986fSmrg Fixes: https://bugs.debian.org/827984 544504d986fSmrg 545504d986fSmrg (Ported from radeon commit 3be841d0ae7d505cef325993205b12d15e98dba9) 546504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 547504d986fSmrg 548504d986fSmrgcommit 84496ebc89a9973347c774c13ff6f4667fcdbe69 549504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 550504d986fSmrgDate: Wed Jul 6 17:43:36 2016 +0900 551504d986fSmrg 552504d986fSmrg Add .editorconfig file 553504d986fSmrg 554504d986fSmrg Basically a conversion from .dir-locals.el. EditorConfig supports many 555504d986fSmrg more editors and IDEs. 556504d986fSmrg 557504d986fSmrg (Ported from radeon commit aa07b365d7b0610411e118f105e49daff5f5a5cf) 558504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 559504d986fSmrg 560504d986fSmrgcommit a576430526cbc404de64b30e1377a356644e8024 561504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 562504d986fSmrgDate: Fri Jun 24 16:28:25 2016 +0900 563504d986fSmrg 564504d986fSmrg Clear damage in amdgpu_scanout_update if it doesn't intersect the CRTC 565504d986fSmrg 566504d986fSmrg There's no need to test that same damage again. 567504d986fSmrg 568504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 569504d986fSmrg 570504d986fSmrgcommit ede7f2bcae63be65e05e3029bfe7c742e5978932 571504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 572504d986fSmrgDate: Fri Jun 24 16:19:15 2016 +0900 573504d986fSmrg 574504d986fSmrg Remove w/h parameters from amdgpu_scanout_extents_intersect 575504d986fSmrg 576504d986fSmrg We can use the dimensions of the CRTC's mode instead. 577504d986fSmrg 578504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 579504d986fSmrg 580504d986fSmrgcommit bf000ea7ef91f5ecb59fc3c1ab8ed9eddcc0841d 581504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 582504d986fSmrgDate: Thu Jun 23 17:28:16 2016 +0900 583504d986fSmrg 584504d986fSmrg Make the dedicated scanout mechanism work with arbitrary transforms v2 585504d986fSmrg 586504d986fSmrg This makes TearFree work with arbitrary transforms, and makes transforms 587504d986fSmrg work better even without TearFree, with xserver >= 1.12. 588504d986fSmrg 589504d986fSmrg v2: Preserve clamping of transformed damage extents to CRTC boundaries. 590504d986fSmrg 591504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 592504d986fSmrg 593504d986fSmrgcommit d96dabc71b1b32dc4b422a9633cdd4e0e95da052 594504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 595504d986fSmrgDate: Thu Jun 23 16:27:45 2016 +0900 596504d986fSmrg 597504d986fSmrg Destroy all dedicated scanout buffers during CloseScreen 598504d986fSmrg 599504d986fSmrg Fixes leaking active scanout buffers across a server reset, which also 600504d986fSmrg fixes server reset with glamor and active scanout buffers. 601504d986fSmrg 602504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 603504d986fSmrg 604504d986fSmrgcommit 1091f28e1fa239ee1a973d84a8376fa4a95d7247 605504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 606504d986fSmrgDate: Thu Jun 23 12:47:04 2016 +0900 607504d986fSmrg 608504d986fSmrg Remove drmmode_load_palette 609504d986fSmrg 610504d986fSmrg Not used by any supported version of xserver. 611504d986fSmrg 612504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 613504d986fSmrg 614504d986fSmrgcommit 4d506c23c9a628204fa23607931557b07ada3e31 615504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 616504d986fSmrgDate: Wed Jun 22 17:16:24 2016 +0900 617504d986fSmrg 618504d986fSmrg present: Separate checks for flips vs unflips v2 619504d986fSmrg 620504d986fSmrg All unflip checks apply to flips as well, but not vice versa. 621504d986fSmrg 622504d986fSmrg v2: Add comment above amdgpu_present_check_unflip (Alex) 623504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 624504d986fSmrg 625504d986fSmrgcommit decabd574f90d3df397c80ec931b3fde8a4afb49 626504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 627504d986fSmrgDate: Wed Jun 22 17:43:41 2016 +0900 628504d986fSmrg 629504d986fSmrg dri2: Don't allow flipping when using a dedicated scanout buffer 630504d986fSmrg 631504d986fSmrg Fixes issues when mixing rotation and page flipping with current xserver 632504d986fSmrg Git master. 633504d986fSmrg 634504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 635504d986fSmrg 636504d986fSmrgcommit 3ed28ce7cd26f89969617ba901ff253091d0d469 637504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 638504d986fSmrgDate: Wed Jun 22 16:54:01 2016 +0900 639504d986fSmrg 640504d986fSmrg present: Don't allow flipping when using a dedicated scanout buffer 641504d986fSmrg 642504d986fSmrg Fixes issues when mixing rotation and page flipping with current xserver 643504d986fSmrg Git master. 644504d986fSmrg 645504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 646504d986fSmrg 647504d986fSmrgcommit 9c3324715fd395fd486ea341654d78f4f298b97f 648504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 649504d986fSmrgDate: Wed Jun 22 16:12:32 2016 +0900 650504d986fSmrg 651504d986fSmrg Make sure drmmode_crtc->scanout[] are destroyed when not needed 652504d986fSmrg 653504d986fSmrg We failed to do this when going back to scanning out directly from the 654504d986fSmrg screen pixmap. 655504d986fSmrg 656504d986fSmrg As a bonus, since we now destroy drmmode_crtc->scanout[] after setting 657504d986fSmrg the new scanout buffer, we may avoid the CRTC turning off intermittently 658504d986fSmrg in this case. 659504d986fSmrg 660504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 661504d986fSmrg 662504d986fSmrgcommit 3bce0519a4008cf87c0e31a7a579e10f5dcdd2f3 663504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 664504d986fSmrgDate: Wed Jun 22 16:19:07 2016 +0900 665504d986fSmrg 666504d986fSmrg Simplify drmmode_set_mode_major error handling 667504d986fSmrg 668504d986fSmrg Initialize ret = FALSE and only set it to TRUE when we've succeeded. 669504d986fSmrg 670504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 671504d986fSmrg 672504d986fSmrgcommit a3ca1500703837cbb8d49c554199a25dea7d5e1e 673504d986fSmrgAuthor: Hans de Goede <hdegoede@redhat.com> 674504d986fSmrgDate: Wed Jun 1 15:14:32 2016 +0200 675504d986fSmrg 676504d986fSmrg Only add main fb if necessary 677504d986fSmrg 678504d986fSmrg If we're doing reverse-prime; or doing rotation the main fb is not used, 679504d986fSmrg and there is no reason to add it in this case. 680504d986fSmrg 681504d986fSmrg Signed-off-by: Hans de Goede <hdegoede@redhat.com> 682504d986fSmrg (Ported from xserver commit 4313122dea0df9affc280ee698e929489061ccc6) 683504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 684504d986fSmrg 685504d986fSmrgcommit 9ca1c24235ff5ab2e028333fc326e2eff008c574 686504d986fSmrgAuthor: Hans de Goede <hdegoede@redhat.com> 687504d986fSmrgDate: Wed Jun 1 15:11:05 2016 +0200 688504d986fSmrg 689504d986fSmrg Remove unnecessary fb addition from drmmode_xf86crtc_resize 690504d986fSmrg 691504d986fSmrg drmmode_set_mode_major() is the only user of drmmode->fb_id and will 692504d986fSmrg create it if necessary. 693504d986fSmrg 694504d986fSmrg Signed-off-by: Hans de Goede <hdegoede@redhat.com> 695504d986fSmrg (Ported from xserver commit 877453212166fdc912e0d687cdecee11aba563b5) 696504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 697504d986fSmrg 698504d986fSmrgcommit 0d42082108c264568e2aadd15ace70e72388bc65 699504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 700504d986fSmrgDate: Wed Jun 22 19:01:03 2016 +0900 701504d986fSmrg 702504d986fSmrg Call amdgpu_glamor_create_screen_resources after ModifyPixmapHeader 703504d986fSmrg 704504d986fSmrg Otherwise, glamor doesn't pick up the new screen pixmap size and 705504d986fSmrg continues using the old size, leaving garbage in some areas after 706504d986fSmrg enlarging the screen. 707504d986fSmrg 708504d986fSmrg Fixes regression from commit c315c00e44afc91a7c8e2eab5af836d9643ebb88 709504d986fSmrg ("Propagate failure from amdgpu_set_pixmap_bo"). 710504d986fSmrg 711504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 712504d986fSmrg 713504d986fSmrgcommit e7e71eabbbccdeabcae1bc6fffabc27c272090ab 714504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 715504d986fSmrgDate: Mon Mar 28 18:49:15 2016 +0900 716504d986fSmrg 717504d986fSmrg Adapt to XF86_CRTC_VERSION 7 718504d986fSmrg 719504d986fSmrg Now the HW cursor can be used with TearFree rotation. 720504d986fSmrg 721504d986fSmrg This also allows always using the separate scanout pixmap mechanism for 722504d986fSmrg rotation, so that should be much smoother even without TearFree enabled. 723504d986fSmrg 724504d986fSmrg (Ported from radeon commit 7835558acdce318130ba4a09ef936fd675e3197d) 725504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 726504d986fSmrg 727504d986fSmrgcommit 7f7f9825caf3983902491da27c16d14cd8bf9b7d 728504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 729504d986fSmrgDate: Mon Jun 13 18:58:49 2016 +0900 730504d986fSmrg 731504d986fSmrg Free priv in amdgpu_set_pixmap_bo also if priv->bo == NULL 732504d986fSmrg 733504d986fSmrg Fixes memory leak when destroying pixmaps with priv->bo == NULL. 734504d986fSmrg 735504d986fSmrg Reported-by: Qiang Yu <qiang.yu@amd.com> 736504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 737504d986fSmrg 738504d986fSmrgcommit 397aedafee437c125b8ac1feafb1c3b466842aeb 739504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 740504d986fSmrgDate: Mon Jun 13 18:34:11 2016 +0900 741504d986fSmrg 742504d986fSmrg glamor: Fix leak of pixmap private when replacing BO 743504d986fSmrg 744504d986fSmrg Reported-by: Qiang Yu <qiang.yu@amd.com> 745504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 746504d986fSmrg 747504d986fSmrgcommit 5b4a8a7a6ed70a50be252fa9b34d3b3a17cdf91a 748504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 749504d986fSmrgDate: Tue Jun 14 19:00:18 2016 +0900 750504d986fSmrg 751504d986fSmrg Use amdgpu_set_pixmap_bo in amdgpu_set_shared_pixmap_backing 752504d986fSmrg 753504d986fSmrg Fixes leaking any existing pixmap private. 754504d986fSmrg 755504d986fSmrg While we're at it, also fix leaking the GBM BO if 756504d986fSmrg amdgpu_glamor_create_textured_pixmap fails. 757504d986fSmrg 758504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 759504d986fSmrg 760504d986fSmrgcommit c315c00e44afc91a7c8e2eab5af836d9643ebb88 761504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 762504d986fSmrgDate: Wed Jun 15 17:20:36 2016 +0900 763504d986fSmrg 764504d986fSmrg Propagate failure from amdgpu_set_pixmap_bo 765504d986fSmrg 766504d986fSmrg Preparation for the following fixes. 767504d986fSmrg 768504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 769504d986fSmrg 770504d986fSmrgcommit 74602c4221e3c84949fd69f690cbc66dcae384ea 771504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 772504d986fSmrgDate: Tue Jun 14 18:53:34 2016 +0900 773504d986fSmrg 774504d986fSmrg glamor: Make amdgpu_glamor_create_textured_pixmap take amdgpu_buffer* 775504d986fSmrg 776504d986fSmrg Preparation for the following fixes. 777504d986fSmrg 778504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 779504d986fSmrg 780504d986fSmrgcommit 0007c2f018ba663303d91d847e7c085269a23062 781504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 782504d986fSmrgDate: Wed Jun 8 16:27:33 2016 +0900 783504d986fSmrg 784504d986fSmrg glamor: Reallocate linear pixmap BO if necessary for DRI2 PRIME 785504d986fSmrg 786504d986fSmrg Fixes corruption when using DRI2 PRIME render offloading with the master 787504d986fSmrg screen using this driver. 788504d986fSmrg 789504d986fSmrg Reported-by: Qiang Yu <qiang.yu@amd.com> 790504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 791504d986fSmrg Tested-by: Qiang Yu <qiang.yu@amd.com> 792504d986fSmrg 793504d986fSmrgcommit 5518bf5d793439b5bab369e5fc18de9a4a3b9dd6 794504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 795504d986fSmrgDate: Wed Jun 8 16:44:26 2016 +0900 796504d986fSmrg 797504d986fSmrg Move DRI2's local fixup_glamor helper to amdgpu_glamor_set_pixmap_bo v2 798504d986fSmrg 799504d986fSmrg So it can be used outside of the DRI2 code. 800504d986fSmrg 801504d986fSmrg v2: Keep pixmap refcnt increment in amdgpu_dri2_create_buffer2 (Qiang Yu) 802504d986fSmrg 803504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 804504d986fSmrg Tested-by: Qiang Yu <qiang.yu@amd.com> (v1) 805504d986fSmrg 806504d986fSmrgcommit 641f4647b7f51dfd2da330376cd10fa9702b6423 807504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 808504d986fSmrgDate: Wed Jun 8 16:39:10 2016 +0900 809504d986fSmrg 810504d986fSmrg Consolidate get_drawable_pixmap helper 811504d986fSmrg 812504d986fSmrg There were two static helpers for the same purpose. Consolidate them 813504d986fSmrg into a single inline helper which can be used anywhere. 814504d986fSmrg 815504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 816504d986fSmrg Tested-by: Qiang Yu <qiang.yu@amd.com> 817504d986fSmrg 818504d986fSmrgcommit 8e40f190e4704c2802bf0f073f17e742786d0f18 819504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 820504d986fSmrgDate: Wed Jun 8 16:00:21 2016 +0900 821504d986fSmrg 822504d986fSmrg Add amdgpu_pixmap_get_tiling_info 823504d986fSmrg 824504d986fSmrg Retrieves the tiling information about a pixmap BO from the kernel 825504d986fSmrg driver. 826504d986fSmrg 827504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 828504d986fSmrg Tested-by: Qiang Yu <qiang.yu@amd.com> 829504d986fSmrg 830504d986fSmrgcommit e7eeb6ad1133b6023d34b4489959ae330a8e15dd 831504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 832504d986fSmrgDate: Wed Jun 8 15:42:01 2016 +0900 833504d986fSmrg 834504d986fSmrg Remove amdgpu_share_pixmap_backing 835504d986fSmrg 836504d986fSmrg Not used anymore. 837504d986fSmrg 838504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 839504d986fSmrg Tested-by: Qiang Yu <qiang.yu@amd.com> 840504d986fSmrg 841504d986fSmrgcommit b36c77695ba77b59a0ccd868454e3af4fc04d5ff 842504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 843504d986fSmrgDate: Wed Jun 8 15:38:57 2016 +0900 844504d986fSmrg 845504d986fSmrg glamor: Fix amdgpu_glamor_share_pixmap_backing for priv->bo == NULL 846504d986fSmrg 847504d986fSmrg Fixes crash when running a compositor and DRI_PRIME client via DRI2. 848504d986fSmrg 849504d986fSmrg Reported-by: Qiang Yu <qiang.yu@amd.com> 850504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 851504d986fSmrg Tested-by: Qiang Yu <qiang.yu@amd.com> 852504d986fSmrg 853504d986fSmrgcommit 60ced5026ebc34d9f32c7618430b6a7ef7c8eb4b 854504d986fSmrgAuthor: Alex Deucher <alexander.deucher@amd.com> 855504d986fSmrgDate: Tue May 17 16:59:41 2016 -0400 856504d986fSmrg 857504d986fSmrg add missing bonaire pci id 858504d986fSmrg 859504d986fSmrg Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 860504d986fSmrg 861504d986fSmrgcommit 8e89448ee00da16e05e6777f34bb75d2dd6f7025 862504d986fSmrgAuthor: Flora Cui <Flora.Cui@amd.com> 863504d986fSmrgDate: Tue May 17 11:02:09 2016 +0800 864504d986fSmrg 865504d986fSmrg Add more Polaris 11 PCI IDs 866504d986fSmrg 867504d986fSmrg Signed-off-by: Flora Cui <Flora.Cui@amd.com> 868504d986fSmrg Reviewed-by: Christian König <christian.koenig@amd.com> 869504d986fSmrg Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 870504d986fSmrg 871504d986fSmrgcommit a59b23d64285741a7a25e314343f6261046d980f 872504d986fSmrgAuthor: Flora Cui <Flora.Cui@amd.com> 873504d986fSmrgDate: Mon May 16 17:25:34 2016 +0800 874504d986fSmrg 875504d986fSmrg Add more Polaris 10 PCI IDs 876504d986fSmrg 877504d986fSmrg Signed-off-by: Flora Cui <Flora.Cui@amd.com> 878504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 879504d986fSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 880504d986fSmrg Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 881504d986fSmrg 882504d986fSmrgcommit 14606e127f4b6eb0b00fd42cec13d524a67e4c4a 883504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 884504d986fSmrgDate: Thu May 12 16:38:56 2016 +0900 885504d986fSmrg 886504d986fSmrg Handle Zaphod mode correctly in amdgpu_mode_hotplug 887504d986fSmrg 888504d986fSmrg We need to scan both screens of the entity for existing connectors, and 889504d986fSmrg enumerate DVI & HDMI connectors consistently regardless of which screen 890504d986fSmrg they're assigned to. 891504d986fSmrg 892504d986fSmrg Fixes crash when hot-(un)plugging connectors in Zaphod mode. 893504d986fSmrg 894504d986fSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93415 895504d986fSmrg (Ported from radeon commit c801f9f10a5d72d935faf21e72f7e7808fb4f05f) 896504d986fSmrg 897504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 898504d986fSmrg 899504d986fSmrgcommit 861da1d5c243f51d6c1f76e5b13e5184aa608776 900504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 901504d986fSmrgDate: Thu May 12 16:34:30 2016 +0900 902504d986fSmrg 903504d986fSmrg Enable DRI3 by default when building for Xorg >= 1.18.3 904504d986fSmrg 905504d986fSmrg Seems to work well enough in general now. 906504d986fSmrg 907504d986fSmrg (Ported from radeon commit 1181b9c582f10b6c523e4b2988e2ce87ecf3d367) 908504d986fSmrg 909504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 910504d986fSmrg 911504d986fSmrgcommit 86f991838824494e68ac277fa27cbd88c23a5ee8 912504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 913504d986fSmrgDate: Tue May 10 15:57:04 2016 +0900 914504d986fSmrg 915504d986fSmrg present: Support async flips 916504d986fSmrg 917504d986fSmrg The xserver Present code only calls radeon_present_flip with 918504d986fSmrg sync_flip=FALSE if radeon_present_screen_init sets 919504d986fSmrg PresentCapabilityAsync, and the latter only sets it if the kernel driver 920504d986fSmrg advertises support for async flips. 921504d986fSmrg 922504d986fSmrg (Ported from radeon commit 1ca677309720e2f6c953c9e76f5b34c22a4416c6) 923504d986fSmrg 924504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 925504d986fSmrg 926504d986fSmrgcommit 744ac5faff7f58e26fa76974b6bdc345ea4c7c79 927504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 928504d986fSmrgDate: Tue May 10 15:47:55 2016 +0900 929504d986fSmrg 930504d986fSmrg Add support for async flips to radeon_do_pageflip 931504d986fSmrg 932504d986fSmrg Will be used by the next change. No functional change here. 933504d986fSmrg 934504d986fSmrg (Ported from radeon commit 90a915c62d012e99193833aecc93974e68880c60) 935504d986fSmrg 936504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 937504d986fSmrg 938504d986fSmrgcommit 4822ec7a23d2253c88bc403f17abb6d7a053528c 939504d986fSmrgAuthor: Flora Cui <flora.cui@amd.com> 940504d986fSmrgDate: Tue May 10 17:14:00 2016 +0900 941504d986fSmrg 942504d986fSmrg add strato pci id 943504d986fSmrg 944504d986fSmrg Signed-off-by: Flora Cui <flora.cui@amd.com> 945504d986fSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 946504d986fSmrg 947504d986fSmrgcommit b93006714b8de972060492cfa311320921a73773 948504d986fSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 949504d986fSmrgDate: Tue Apr 12 08:48:33 2016 -0400 950504d986fSmrg 951504d986fSmrg dri3: Return NULL from amdgpu_dri3_pixmap_from_fd if calloc fails. 952504d986fSmrg 953504d986fSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 954504d986fSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 955504d986fSmrg 956504d986fSmrgcommit a0bbb373f902e0ffc14570c85faec7e44134f62e 957504d986fSmrgAuthor: Qiang Yu <Qiang.Yu@amd.com> 958504d986fSmrgDate: Fri Apr 8 17:29:17 2016 +0800 959504d986fSmrg 960504d986fSmrg Remove RR_Capability_SinkOutput for GPU without CRTC. 961504d986fSmrg 962504d986fSmrg Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> 963504d986fSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 964504d986fSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 965504d986fSmrg 966504d986fSmrgcommit 1a29c4bcc0a286b14f37ab942eb0cad47bc4f337 967504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 968504d986fSmrgDate: Mon Apr 11 16:27:40 2016 +0900 969504d986fSmrg 970504d986fSmrg Post 1.1.0 release version bump 971504d986fSmrg 972d6c0b56eSmrgcommit a04f4015d6afef20c2b79e2779f6555836ee2b07 973d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 974d6c0b56eSmrgDate: Thu Apr 7 16:47:25 2016 +0900 975d6c0b56eSmrg 976d6c0b56eSmrg Bump version for 1.1.0 release 977d6c0b56eSmrg 978d6c0b56eSmrgcommit aed1c17c43b2c0c983f6fc0973a5224d0faf32d9 979d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 980d6c0b56eSmrgDate: Mon Apr 4 18:28:02 2016 +0900 981d6c0b56eSmrg 982d6c0b56eSmrg glamor: Force GPU rendering to/from pixmaps created via DRI3 983d6c0b56eSmrg 984d6c0b56eSmrg Fixes crash when running DRI3 clients with ShadowPrimary enabled. 985d6c0b56eSmrg 986d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94799 987d6c0b56eSmrg 988d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 989d6c0b56eSmrg 990d6c0b56eSmrgcommit faf9d720b7d650f5f1ea657a874d08eac3972e60 991d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 992d6c0b56eSmrgDate: Fri Apr 1 16:09:51 2016 +0900 993d6c0b56eSmrg 994d6c0b56eSmrg Update manpage entry for Option "TearFree" 995d6c0b56eSmrg 996d6c0b56eSmrg It's now effective for rotation as well. 997d6c0b56eSmrg 998d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 999d6c0b56eSmrg 1000d6c0b56eSmrgcommit 5ba95c3abeb8df82aa8d33a47596eae6403ea7af 1001d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1002d6c0b56eSmrgDate: Fri Apr 1 15:29:26 2016 +0900 1003d6c0b56eSmrg 1004d6c0b56eSmrg Identify DRM event queue entries by sequence number instead of by pointer 1005d6c0b56eSmrg 1006d6c0b56eSmrg If the memory for an entry was allocated at the same address as that for 1007d6c0b56eSmrg a previously cancelled entry, the handler could theoretically be called 1008d6c0b56eSmrg prematurely, triggered by the DRM event which was submitted for the 1009d6c0b56eSmrg cancelled entry. 1010d6c0b56eSmrg 1011d6c0b56eSmrg (Ported from radeon commit 4693b1bd5b5c381e8b7b68a6f7f0c6696d6a68df) 1012d6c0b56eSmrg 1013d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1014d6c0b56eSmrg 1015d6c0b56eSmrgcommit 8ecfa69b5a833bd4c39e773a6acfd7eef9144d13 1016d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1017d6c0b56eSmrgDate: Wed Mar 30 18:33:00 2016 +0900 1018d6c0b56eSmrg 1019d6c0b56eSmrg DRI3: Refuse to open DRM file descriptor for ssh clients 1020d6c0b56eSmrg 1021d6c0b56eSmrg Fixes hangs when attempting to use DRI3 on display connections forwarded 1022d6c0b56eSmrg via SSH. 1023d6c0b56eSmrg 1024d6c0b56eSmrg Don't do this for Xorg > 1.18.99.1 since the corresponding xserver 1025d6c0b56eSmrg change has landed in Git master. 1026d6c0b56eSmrg 1027d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93261 1028d6c0b56eSmrg 1029d6c0b56eSmrg (Ported from radeon commit 0b3aac1de9db42bfca545fa331e4985836682ec7) 1030d6c0b56eSmrg 1031d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1032d6c0b56eSmrg 1033d6c0b56eSmrgcommit b2a2e114eec0967f7b67f030fbab8983cf980489 1034d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1035d6c0b56eSmrgDate: Fri Mar 25 11:55:34 2016 +0900 1036d6c0b56eSmrg 1037d6c0b56eSmrg Revert "Use render node for DRI3 if available" 1038d6c0b56eSmrg 1039d6c0b56eSmrg This reverts commit ea558e645786b08d75307716036045170e97b43e. 1040d6c0b56eSmrg 1041d6c0b56eSmrg It broke VDPAU<->GL interop with DRI3 enabled, because the Gallium VDPAU 1042d6c0b56eSmrg code doesn't support DRI3 yet. We can consider re-enabling this once 1043d6c0b56eSmrg there is a Mesa release where the Gallium VDPAU code supports DRI3. 1044d6c0b56eSmrg 1045d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94675 1046d6c0b56eSmrg 1047d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1048d6c0b56eSmrg 1049d6c0b56eSmrgcommit e31a2d668a1b5ebaf75d423c8123cbc8e0dcbae9 1050d6c0b56eSmrgAuthor: Flora Cui <Flora.Cui@amd.com> 1051d6c0b56eSmrgDate: Wed Nov 18 16:44:13 2015 +0800 1052d6c0b56eSmrg 1053d6c0b56eSmrg add polaris10 pci id 1054d6c0b56eSmrg 1055d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1056d6c0b56eSmrg Signed-off-by: Flora Cui <Flora.Cui@amd.com> 1057d6c0b56eSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 1058d6c0b56eSmrg 1059d6c0b56eSmrgcommit 6e09b8deb77f76b9bb7d393cc1ad924ebba62eff 1060d6c0b56eSmrgAuthor: Flora Cui <Flora.Cui@amd.com> 1061d6c0b56eSmrgDate: Thu Nov 5 14:16:39 2015 +0800 1062d6c0b56eSmrg 1063d6c0b56eSmrg add polaris11 pci id 1064d6c0b56eSmrg 1065d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1066d6c0b56eSmrg Signed-off-by: Flora Cui <Flora.Cui@amd.com> 1067d6c0b56eSmrg Reviewed-By: Jammy Zhou <Jammy.Zhou@amd.com> 1068d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1069d6c0b56eSmrg 1070d6c0b56eSmrgcommit 7d32c43fff4c8df32cce150223094f793e036cf3 1071d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com> 1072d6c0b56eSmrgDate: Wed Oct 28 17:28:23 2015 -0400 1073d6c0b56eSmrg 1074d6c0b56eSmrg add Polaris chip families 1075d6c0b56eSmrg 1076d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1077d6c0b56eSmrg Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 1078d6c0b56eSmrg 1079d6c0b56eSmrgcommit fbf9ae18cd241b8b78936aa30441e5fbfd9ba1c5 1080d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1081d6c0b56eSmrgDate: Thu Mar 24 19:05:15 2016 +0900 1082d6c0b56eSmrg 1083d6c0b56eSmrg Require xserver 1.9 or newer 1084d6c0b56eSmrg 1085d6c0b56eSmrg 1.9.0 was released in August 2010. 1086d6c0b56eSmrg 1087d6c0b56eSmrg We were already unintentionally relying on things not available in 1.8 1088d6c0b56eSmrg for at least a year, and nobody has complained. 1089d6c0b56eSmrg 1090d6c0b56eSmrg (Ported from radeon commit e592f32f8b5f5873fcc18b10a69dd5e4ccf11073) 1091d6c0b56eSmrg 1092d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1093d6c0b56eSmrg 1094d6c0b56eSmrgcommit 912db5fbbc6b9b1121c8a03168cb4bd870474376 1095d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1096d6c0b56eSmrgDate: Thu Mar 24 18:59:05 2016 +0900 1097d6c0b56eSmrg 1098d6c0b56eSmrg Fix build against older versions of xserver 1099d6c0b56eSmrg 1100d6c0b56eSmrg Also slightly clean up the error handling in amdgpu_scanout_do_update. 1101d6c0b56eSmrg 1102d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94614 1103d6c0b56eSmrg 1104d6c0b56eSmrg (Ported from radeon commit bde466e5d44cad64b4e4eceaa5de80fdbf86356e) 1105d6c0b56eSmrg 1106d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1107d6c0b56eSmrg 1108d6c0b56eSmrgcommit 3fb6280ab3b104b02841c7cab8ed68c1d463c834 1109d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1110d6c0b56eSmrgDate: Thu Mar 24 18:56:44 2016 +0900 1111d6c0b56eSmrg 1112d6c0b56eSmrg DRI3 only works with acceleration 1113d6c0b56eSmrg 1114d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94214 1115d6c0b56eSmrg 1116d6c0b56eSmrg (Ported from radeon commit d21ac4669a8b2cdd4eec5e5a94d1950b7423b8b5) 1117d6c0b56eSmrg 1118d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1119d6c0b56eSmrg 1120d6c0b56eSmrgcommit 3177fe817a5f2de4ed10860866a0dd6d6c6ba816 1121d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1122d6c0b56eSmrgDate: Thu Mar 24 18:51:59 2016 +0900 1123d6c0b56eSmrg 1124d6c0b56eSmrg Check for xf86CursorResetCursor 1125d6c0b56eSmrg 1126d6c0b56eSmrg If it's available, Xorg calls it on each mode configuration change. It 1127d6c0b56eSmrg does what xf86_reload_cursors does (and more), so we don't need to call 1128d6c0b56eSmrg the latter anymore. 1129d6c0b56eSmrg 1130d6c0b56eSmrg (Ported from radeon commit d670c5c9851b4eff21c845d26c7d7e4eb5ee0fa9) 1131d6c0b56eSmrg 1132d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1133d6c0b56eSmrg 1134d6c0b56eSmrgcommit a3dfce7b24e1ea01c1aa62926025a545312cbe13 1135d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1136d6c0b56eSmrgDate: Thu Mar 24 18:45:46 2016 +0900 1137d6c0b56eSmrg 1138d6c0b56eSmrg Don't try DRI2/Present flipping while the HW cursor can't be used 1139d6c0b56eSmrg 1140d6c0b56eSmrg Flipping doesn't interact correctly with SW cursor: A flip makes the SW 1141d6c0b56eSmrg cursor disappear. It will only appear again when the cursor is moved, 1142d6c0b56eSmrg but it will be surrounded by corruption, because the SW cursor code 1143d6c0b56eSmrg will restore stale screen contents at the old cursor location before 1144d6c0b56eSmrg drawing the cursor at the new location. 1145d6c0b56eSmrg 1146d6c0b56eSmrg (Ported from radeon commit 7f3d0780ca65a90117c2a61362dbc0899bd9c0b0) 1147d6c0b56eSmrg 1148d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1149d6c0b56eSmrg 1150d6c0b56eSmrgcommit ba9be8f32f0321689133e17c1681809dec8c6cf1 1151d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1152d6c0b56eSmrgDate: Thu Mar 24 18:44:30 2016 +0900 1153d6c0b56eSmrg 1154d6c0b56eSmrg Factor out HW cursor checking code into drmmode_can_use_hw_cursor 1155d6c0b56eSmrg 1156d6c0b56eSmrg And add a check for RandR 1.4 multihead. 1157d6c0b56eSmrg 1158d6c0b56eSmrg (Ported from radeon commit 3de480e83c0a1824838d662d6d67c9fe85277298) 1159d6c0b56eSmrg 1160d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1161d6c0b56eSmrg 1162d6c0b56eSmrgcommit 4a60b4b1851a3cbc2d8ad9048d68eeb6947cf132 1163d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1164d6c0b56eSmrgDate: Thu Mar 24 12:03:38 2016 +0900 1165d6c0b56eSmrg 1166d6c0b56eSmrg Call AMDGPUBlockHandler_KMS before setting initial modes 1167d6c0b56eSmrg 1168d6c0b56eSmrg Doing it the other way around meant that there was still a possibility 1169d6c0b56eSmrg for the front buffer contents to be uninitialized when they start being 1170d6c0b56eSmrg scanned out. 1171d6c0b56eSmrg 1172d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1173d6c0b56eSmrg 1174d6c0b56eSmrgcommit 37bd79652a8ec612b94a1863e8c580b1cfaf3960 1175d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1176d6c0b56eSmrgDate: Fri Mar 18 18:51:00 2016 +0900 1177d6c0b56eSmrg 1178d6c0b56eSmrg present: Return rotated CRTCs from amdgpu_present_get_crtc 1179d6c0b56eSmrg 1180d6c0b56eSmrg Sync-to-vblank works fine with rotation. We're still checking for 1181d6c0b56eSmrg rotation in amdgpu_present_check_flip. 1182d6c0b56eSmrg 1183d6c0b56eSmrg Returning NULL from here resulted in the xserver present code falling 1184d6c0b56eSmrg back to the fake CRTC running at 1 fps. 1185d6c0b56eSmrg 1186d6c0b56eSmrg (Ported from radeon commit a03271de5ecdaa7790d1316e993c4450b91fe936) 1187d6c0b56eSmrg 1188d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1189d6c0b56eSmrg 1190d6c0b56eSmrgcommit 6b930fb3285dea4a6440e31099c96f08da508d49 1191d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1192d6c0b56eSmrgDate: Fri Mar 18 18:47:10 2016 +0900 1193d6c0b56eSmrg 1194d6c0b56eSmrg present: Clear drmmode->fb_id before calling set_mode_major for unflip 1195d6c0b56eSmrg 1196d6c0b56eSmrg Without this, drmmode_set_mode_major may just re-set the FB for the 1197d6c0b56eSmrg last flipped BO, in which case the display will probably freeze. 1198d6c0b56eSmrg 1199d6c0b56eSmrg Reproduction recipe: Enable rotation while a fullscreen client is 1200d6c0b56eSmrg flipping. 1201d6c0b56eSmrg 1202d6c0b56eSmrg (Ported from radeon commit 40191d82370eb7e58bd34c44966cbf44c3703229) 1203d6c0b56eSmrg 1204d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1205d6c0b56eSmrg 1206d6c0b56eSmrgcommit 6889e091442b6ba1b9351e72bd067425e87d96e9 1207d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1208d6c0b56eSmrgDate: Fri Mar 18 18:18:04 2016 +0900 1209d6c0b56eSmrg 1210d6c0b56eSmrg Make Option "TearFree" effective for rotated/reflected outputs as well 1211d6c0b56eSmrg 1212d6c0b56eSmrg Support varies by xserver version: 1213d6c0b56eSmrg 1214d6c0b56eSmrg < 1.12: No support for the driver handling rotation/reflection 1215d6c0b56eSmrg 1.12-1.15: Support for driver handling rotation/reflection, but there's 1216d6c0b56eSmrg a bug preventing the HW cursor from being visible everywhere 1217d6c0b56eSmrg it should be on rotated outputs, so we can only support 1218d6c0b56eSmrg TearFree for reflection. 1219d6c0b56eSmrg >= 1.16: While the bug above is still there (fixes pending review), 1220d6c0b56eSmrg the driver can force SW cursor for rotated outputs, so we 1221d6c0b56eSmrg can support TearFree for rotation as well. 1222d6c0b56eSmrg 1223d6c0b56eSmrg (Ported from radeon commit 798c4fd16d339b1ad5fd729cc884be084c60e38b) 1224d6c0b56eSmrg 1225d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1226d6c0b56eSmrg 1227d6c0b56eSmrgcommit da4e0c66fcbcf63143372720e3d606a462332e3a 1228d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1229d6c0b56eSmrgDate: Fri Mar 18 18:15:34 2016 +0900 1230d6c0b56eSmrg 1231d6c0b56eSmrg Consolidate pScreen usage in drmmode_set_mode_major 1232d6c0b56eSmrg 1233d6c0b56eSmrg We were already relying on pScrn->pScreen being non-NULL in some cases, 1234d6c0b56eSmrg which is supposedly always true ever since this function is no longer 1235d6c0b56eSmrg getting called from ScreenInit. 1236d6c0b56eSmrg 1237d6c0b56eSmrg (Ported from radeon commit eb611a2e4ecce7a1ab85fd72b9b78e3269311dd5) 1238d6c0b56eSmrg 1239d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1240d6c0b56eSmrg 1241d6c0b56eSmrgcommit 0bbf09dd7ef54133b3e534becb3ba15c0cf3eed2 1242d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1243d6c0b56eSmrgDate: Fri Mar 18 18:14:28 2016 +0900 1244d6c0b56eSmrg 1245d6c0b56eSmrg Remove check for XF86_CRTC_VERSION 3 1246d6c0b56eSmrg 1247d6c0b56eSmrg We require xserver >= 1.8, which was already at version 3. 1248d6c0b56eSmrg 1249d6c0b56eSmrg (Ported from radeon commit 06602171386e538081c298645fb7ca1a70fe80cc) 1250d6c0b56eSmrg 1251d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1252d6c0b56eSmrg 1253d6c0b56eSmrgcommit 3485ca0051a224d00135d4024a97a6c4e85a9644 1254d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1255d6c0b56eSmrgDate: Fri Mar 18 18:07:07 2016 +0900 1256d6c0b56eSmrg 1257d6c0b56eSmrg Deal with modesets and page flips crossing on a CRTC 1258d6c0b56eSmrg 1259d6c0b56eSmrg If we set a mode while a flip is pending, the kernel driver may program 1260d6c0b56eSmrg the flip to the hardware after the modeset. If that happens, the hardware 1261d6c0b56eSmrg will display the BO from the flip, whereas we will assume it displays the 1262d6c0b56eSmrg BO from the modeset. In other words, the display will most likely freeze, 1263d6c0b56eSmrg at least until another modeset. 1264d6c0b56eSmrg 1265d6c0b56eSmrg Prevent this condition by waiting for a pending flip to finish before 1266d6c0b56eSmrg setting a mode. 1267d6c0b56eSmrg 1268d6c0b56eSmrg Fixes display freezing when setting rotation or a transform with 1269d6c0b56eSmrg TearFree enabled. 1270d6c0b56eSmrg 1271d6c0b56eSmrg (Ported from radeon commit a88985f5d1e39caca49ceb65678aaa9cb622a0d2) 1272d6c0b56eSmrg 1273d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1274d6c0b56eSmrg 1275d6c0b56eSmrgcommit b9d00fa7aaf946d985897380bfa42faafbf1b3fb 1276d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1277d6c0b56eSmrgDate: Fri Mar 18 17:18:00 2016 +0900 1278d6c0b56eSmrg 1279d6c0b56eSmrg Make DRM event queue xf86CrtcPtr based instead of ScrnInfoPtr based 1280d6c0b56eSmrg 1281d6c0b56eSmrg This allows for a minor simplification of the code. 1282d6c0b56eSmrg 1283d6c0b56eSmrg (Ported from radeon commit f5d968cbba3c9b7ec202161f2157d8d64778c817) 1284d6c0b56eSmrg 1285d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1286d6c0b56eSmrg 1287d6c0b56eSmrgcommit e0ed26151bfeadf309da53d001751c0a014dbd24 1288d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1289d6c0b56eSmrgDate: Fri Mar 18 17:11:47 2016 +0900 1290d6c0b56eSmrg 1291d6c0b56eSmrg Remove amdgpu_scanout_flip_handler 1292d6c0b56eSmrg 1293d6c0b56eSmrg No longer necessary now that amdgpu_drm_queue_handler can handle 1294d6c0b56eSmrg e->handler == NULL. 1295d6c0b56eSmrg 1296d6c0b56eSmrg (Ported from radeon commit d5dbb07db22d5420c81dfebc060f0dd86e7b8a20) 1297d6c0b56eSmrg 1298d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1299d6c0b56eSmrg 1300d6c0b56eSmrgcommit acd5da56f502d6ad115501e77bce06fe72b1895c 1301d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1302d6c0b56eSmrgDate: Fri Mar 18 17:14:49 2016 +0900 1303d6c0b56eSmrg 1304d6c0b56eSmrg DRI2: Also clear dri2_flipping when client disconnects before event 1305d6c0b56eSmrg 1306d6c0b56eSmrg Fixes the following problem: 1307d6c0b56eSmrg 1308d6c0b56eSmrg With DRI3 enabled, run glxgears with LIBGL_DRI3_DISABLE=1, make it 1309d6c0b56eSmrg fullscreen and press Escape while it's still fullscreen. This could 1310d6c0b56eSmrg result in dri2_flipping not getting cleared, spuriously preventing apps 1311d6c0b56eSmrg using DRI3 from flipping. 1312d6c0b56eSmrg 1313d6c0b56eSmrg (Ported from radeon commit e87365117acbd80b7d80fbb5eb30890ef7153291) 1314d6c0b56eSmrg 1315d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1316d6c0b56eSmrg 1317d6c0b56eSmrgcommit a58bfa98208cc092014d3f36a08714eb1e0d8814 1318d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1319d6c0b56eSmrgDate: Fri Mar 18 17:07:47 2016 +0900 1320d6c0b56eSmrg 1321d6c0b56eSmrg drm_queue: Don't abort events immediately from amdgpu_drm_abort_client 1322d6c0b56eSmrg 1323d6c0b56eSmrg Keep them around until the DRM event arrives, but then call the abort 1324d6c0b56eSmrg functions instead of the handler functions. 1325d6c0b56eSmrg 1326d6c0b56eSmrg This is a prerequisite for the following fix. 1327d6c0b56eSmrg 1328d6c0b56eSmrg (Ported from radeon commit 3989766edde85d1abe7024577b98fc9b007bc02a) 1329d6c0b56eSmrg 1330d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1331d6c0b56eSmrg 1332d6c0b56eSmrgcommit e4888df6e32bb817bf0d6166a22b19c14e189a84 1333d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1334d6c0b56eSmrgDate: Fri Mar 18 17:04:10 2016 +0900 1335d6c0b56eSmrg 1336d6c0b56eSmrg Fix RandR CRTC transforms 1337d6c0b56eSmrg 1338d6c0b56eSmrg Currently, Xorg will only transform the cursor as of the first time the 1339d6c0b56eSmrg cursor image changes after a transform is set. 1340d6c0b56eSmrg 1341d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80678 1342d6c0b56eSmrg 1343d6c0b56eSmrg (Ported from radeon commit 9483a3d777919b224f70c3b4d01e4b320a57db31) 1344d6c0b56eSmrg 1345d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1346d6c0b56eSmrg 1347d6c0b56eSmrgcommit 43af92ede0968f2108f9562aa4c2c861ac703617 1348d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1349d6c0b56eSmrgDate: Fri Mar 18 16:58:07 2016 +0900 1350d6c0b56eSmrg 1351d6c0b56eSmrg Build RandR 1.4 provider name from chipset name and bus ID 1352d6c0b56eSmrg 1353d6c0b56eSmrg Instead of just "amdgpu", it's now e.g. "TONGA @ pci:0000:01:00.0". 1354d6c0b56eSmrg 1355d6c0b56eSmrg (Ported from radeon commit c7cf00487cd6d4a5d0f39d5b92ff04f6420d6a32) 1356d6c0b56eSmrg 1357d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1358d6c0b56eSmrg 1359d6c0b56eSmrgcommit 5ec1797a2858d693d18d21326e2307d71555e1db 1360d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1361d6c0b56eSmrgDate: Wed Feb 24 17:33:49 2016 +0900 1362d6c0b56eSmrg 1363d6c0b56eSmrg DRI2: Use amdgpu_pixmap_get_handle 1364d6c0b56eSmrg 1365d6c0b56eSmrg Now we can share pixmaps with no struct amdgpu_buffer via DRI2. 1366d6c0b56eSmrg 1367d6c0b56eSmrg Fixes VDPAU video playback freezing when using an OpenGL compositor with 1368d6c0b56eSmrg DRI3 enabled and mpv VAAPI hardware decoding with OpenGL output. 1369d6c0b56eSmrg 1370d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89755 1371d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93804 1372d6c0b56eSmrg 1373d6c0b56eSmrg (ported from radeon commit f8b0f23e9f4af9f9097ee5e72d53b45173163c41) 1374d6c0b56eSmrg 1375d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1376d6c0b56eSmrg 1377d6c0b56eSmrgcommit df60c635e1e632233de9dd4b01d63c2b963003f8 1378d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1379d6c0b56eSmrgDate: Wed Feb 24 17:06:43 2016 +0900 1380d6c0b56eSmrg 1381d6c0b56eSmrg glamor: Avoid generating GEM flink names for BOs shared via DRI3 (v2) 1382d6c0b56eSmrg 1383d6c0b56eSmrg We can't create our own struct amdgpu_buffer representation in this case 1384d6c0b56eSmrg because destroying that would make the GEM handle inaccessible to glamor 1385d6c0b56eSmrg as well. So just get the handle directly via dma-buf. 1386d6c0b56eSmrg 1387d6c0b56eSmrg (ported from radeon commit 391900a670addec39515f924265bfa9f8bfa9ec0, 1388d6c0b56eSmrg extended to cache BO handles in the private for non-DRI3 pixmaps as 1389d6c0b56eSmrg well) 1390d6c0b56eSmrg 1391d6c0b56eSmrg v2: Swap whole pixmap privates instead of just BOs in 1392d6c0b56eSmrg amdgpu_dri2_exchange_buffers to avoid invalidating cached BO handles 1393d6c0b56eSmrg 1394d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1395d6c0b56eSmrg 1396d6c0b56eSmrgcommit e463b849f3e9d7b69e64a65619a22e00e78d297b 1397d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1398d6c0b56eSmrgDate: Tue Feb 23 18:10:29 2016 +0900 1399d6c0b56eSmrg 1400d6c0b56eSmrg Make amdgpu_do_pageflip take a pixmap instead of a BO 1401d6c0b56eSmrg 1402d6c0b56eSmrg (inspired by radeon commit 7b4fc4a677d252d01c2bf80d162bc35814059eaa) 1403d6c0b56eSmrg 1404d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1405d6c0b56eSmrg 1406d6c0b56eSmrgcommit 1ee341f9d909f3b7ba2984fc912dabdb98c34b19 1407d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1408d6c0b56eSmrgDate: Tue Feb 23 18:42:19 2016 +0900 1409d6c0b56eSmrg 1410d6c0b56eSmrg Add amdgpu_pixmap_get_handle helper 1411d6c0b56eSmrg 1412d6c0b56eSmrg (inspired by radeon commits dfad91fffb5bd013785223b42d78886df839eacf 1413d6c0b56eSmrg and ccbda955ebae1d457d35293833f12791e0f9fb0b) 1414d6c0b56eSmrg 1415d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1416d6c0b56eSmrg 1417d6c0b56eSmrgcommit a36bbfd98b96426bbe0be3923c64da7ec0e565d0 1418d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1419d6c0b56eSmrgDate: Mon Feb 15 18:41:51 2016 +0900 1420d6c0b56eSmrg 1421d6c0b56eSmrg HAS_DIRTYTRACKING_ROTATION also supports multiple CRTCs 1422d6c0b56eSmrg 1423d6c0b56eSmrg (ported from radeon commit ff9a6b6f079a8419f4e6fadfee778060618bf735) 1424d6c0b56eSmrg 1425d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1426d6c0b56eSmrg 1427d6c0b56eSmrgcommit a37746ffceaed83e48e48fb05439be7e020dd2ea 1428d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1429d6c0b56eSmrgDate: Mon Feb 15 18:35:54 2016 +0900 1430d6c0b56eSmrg 1431d6c0b56eSmrg Load fb module before glamoregl/shadow modules 1432d6c0b56eSmrg 1433d6c0b56eSmrg Fixes unresolved symbols on some systems. 1434d6c0b56eSmrg 1435d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93105 1436d6c0b56eSmrg (ported from radeon commit 78fbca095ae9887a2d3de48bb07975e2d1126e68) 1437d6c0b56eSmrg 1438d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1439d6c0b56eSmrg 1440d6c0b56eSmrgcommit 59c0a6807110eca829c6708e16585a38f39a5c17 1441d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1442d6c0b56eSmrgDate: Mon Feb 15 18:28:13 2016 +0900 1443d6c0b56eSmrg 1444d6c0b56eSmrg Don't advertise any PRIME offloading capabilities without acceleration 1445d6c0b56eSmrg 1446d6c0b56eSmrg Acceleration is required even for display offloading. Trying to enable 1447d6c0b56eSmrg display offloading without acceleration resulted in a crash. 1448d6c0b56eSmrg 1449d6c0b56eSmrg (ported from radeon commit b19417e2fddf4df725951aea5ad5e9558338f59e) 1450d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1451d6c0b56eSmrg 1452d6c0b56eSmrgcommit a3eac85d812ecc605436e6bd5b9ee7ebf307e3d3 1453d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1454d6c0b56eSmrgDate: Tue Jan 26 16:12:28 2016 +0900 1455d6c0b56eSmrg 1456d6c0b56eSmrg Only map front buffer if glamor acceleration is disabled (v2) 1457d6c0b56eSmrg 1458d6c0b56eSmrg Otherwise the front buffer may not be accessible by the CPU, because Mesa 1459d6c0b56eSmrg sets the AMDGPU_GEM_CREATE_NO_CPU_ACCESS flag for tiled buffers, because 1460d6c0b56eSmrg accessing tiled buffers with the CPU makes little sense. 1461d6c0b56eSmrg 1462d6c0b56eSmrg v2: Also handle Option "AccelMethod" "none" 1463d6c0b56eSmrg 1464d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1465d6c0b56eSmrg 1466d6c0b56eSmrgcommit 2fcb7dadd3c71cd405cbbaafc777697538ca9c29 1467d6c0b56eSmrgAuthor: jimqu <Jim.Qu@amd.com> 1468d6c0b56eSmrgDate: Mon Jan 25 09:47:00 2016 +0800 1469d6c0b56eSmrg 1470d6c0b56eSmrg glamor: Return NullPixmap on failure to create shareable pixmap 1471d6c0b56eSmrg 1472d6c0b56eSmrg If we were asked to create a shareable pixmap, it doesn't make sense 1473d6c0b56eSmrg to return a pixmap which isn't shareable. Doing so caused trouble down 1474d6c0b56eSmrg the line such as a crash with older versions of glamor when trying to 1475d6c0b56eSmrg use GLX pixmaps of bpp < 32 via DRI2. 1476d6c0b56eSmrg 1477d6c0b56eSmrg Signed-off-by: JimQu <jim.qu@amd.com> 1478d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1479d6c0b56eSmrg 1480d6c0b56eSmrgcommit 5269a2228bff6023c1a7f3e8534027e1d7addc25 1481d6c0b56eSmrgAuthor: jimqu <Jim.Qu@amd.com> 1482d6c0b56eSmrgDate: Mon Jan 25 10:12:02 2016 +0800 1483d6c0b56eSmrg 1484d6c0b56eSmrg Move amdgpu_glamor_destroy_pixmap before amdgpu_glamor_create_pixmap 1485d6c0b56eSmrg 1486d6c0b56eSmrg The next commit will call the former from the latter. No functional 1487d6c0b56eSmrg change. 1488d6c0b56eSmrg 1489d6c0b56eSmrg Signed-off-by: JimQu <jim.qu@amd.com> 1490d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1491d6c0b56eSmrg 1492d6c0b56eSmrgcommit 54c959c163288caa87f612911b70df73f87d29d6 1493d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 1494d6c0b56eSmrgDate: Wed Jan 20 09:37:36 2016 -0500 1495d6c0b56eSmrg 1496d6c0b56eSmrg Move memset() after variable declarations 1497d6c0b56eSmrg 1498d6c0b56eSmrg To make the code more "C" like move the function calls 1499d6c0b56eSmrg after the variable declarations. 1500d6c0b56eSmrg 1501d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 1502d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1503d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1504d6c0b56eSmrg 1505d6c0b56eSmrgcommit 8853b07ae8169c409740c40d45cd335bd608f2a7 1506d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1507d6c0b56eSmrgDate: Tue Jan 19 17:35:11 2016 +0900 1508d6c0b56eSmrg 1509d6c0b56eSmrg Set the RandR primary output on startup if Xorg hasn't 1510d6c0b56eSmrg 1511d6c0b56eSmrg Fixes xrandr (XRRGetOutputPrimary) not reporting any output as primary 1512d6c0b56eSmrg after startup. 1513d6c0b56eSmrg 1514d6c0b56eSmrg (Ported from radeon commit b16856b25086ffb27365ac2249b8da921066ce62) 1515d6c0b56eSmrg 1516d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1517d6c0b56eSmrg 1518d6c0b56eSmrgcommit bd5c65daceaf633c36fcec86ff061df10c364bc0 1519d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1520d6c0b56eSmrgDate: Thu Jan 7 15:53:41 2016 +0900 1521d6c0b56eSmrg 1522d6c0b56eSmrg Only call amdgpu_bus_id once in each probe path (v2) 1523d6c0b56eSmrg 1524d6c0b56eSmrg Instead of up to twice as before. 1525d6c0b56eSmrg 1526d6c0b56eSmrg v2: Remove free(busIdString) call from amdgpu_kernel_mode_enabled, the 1527d6c0b56eSmrg bus ID string is now managed by its callers. 1528d6c0b56eSmrg 1529d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) 1530d6c0b56eSmrg 1531d6c0b56eSmrgcommit 6e42c58375a4c3229da93c27bbd104af145c6163 1532d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1533d6c0b56eSmrgDate: Thu Jan 7 15:57:38 2016 +0900 1534d6c0b56eSmrg 1535d6c0b56eSmrg Remove pci_dev test from amdgpu_get_scrninfo 1536d6c0b56eSmrg 1537d6c0b56eSmrg The pci_dev parameter can never be NULL since we only support KMS. 1538d6c0b56eSmrg 1539d6c0b56eSmrg Reported-by: Tom St Denis <tom.stdenis@amd.com> 1540d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1541d6c0b56eSmrg 1542d6c0b56eSmrgcommit 8e09180798a06af5afa030d754938e4ca06e272f 1543d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1544d6c0b56eSmrgDate: Thu Jan 7 15:35:35 2016 +0900 1545d6c0b56eSmrg 1546d6c0b56eSmrg Re-use PCI bus ID code from kernel_open_fd in kernel_mode_enabled 1547d6c0b56eSmrg 1548d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1549d6c0b56eSmrg 1550d6c0b56eSmrgcommit 4eb9cedca080b30c57ded349a397620ee7d0cd46 1551d6c0b56eSmrgAuthor: Mykola Lysenko <Mykola.Lysenko@amd.com> 1552d6c0b56eSmrgDate: Wed Jan 13 14:03:55 2016 +0800 1553d6c0b56eSmrg 1554d6c0b56eSmrg Initialize drmmode_crtc dpms_mode to DPMSModeOff 1555d6c0b56eSmrg 1556d6c0b56eSmrg This disables query of disabled pipes for drmWaitVBlank on X start 1557d6c0b56eSmrg 1558d6c0b56eSmrg Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com> 1559d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1560d6c0b56eSmrg 1561d6c0b56eSmrgcommit 1d0b0c1794e65e581a48aa9fb19679d928d82a5d 1562d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1563d6c0b56eSmrgDate: Thu Dec 10 18:08:12 2015 +0900 1564d6c0b56eSmrg 1565d6c0b56eSmrg sync: Check if miSyncShmScreenInit symbol is resolved at runtime 1566d6c0b56eSmrg 1567d6c0b56eSmrg It may be disabled in the Xorg build, either explicitly or because the 1568d6c0b56eSmrg xshmfence library isn't available. 1569d6c0b56eSmrg 1570d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1571d6c0b56eSmrg 1572d6c0b56eSmrgcommit f4107f67f147e2500582fc36cf0f0f76bc1ef098 1573d6c0b56eSmrgAuthor: Mykola Lysenko <Mykola.Lysenko@amd.com> 1574d6c0b56eSmrgDate: Wed Dec 23 11:58:47 2015 -0500 1575d6c0b56eSmrg 1576d6c0b56eSmrg Check for NULL koutput in drmmode_output_dpms 1577d6c0b56eSmrg 1578d6c0b56eSmrg This situation happens whit start of usage of DRM DP MST framework, 1579d6c0b56eSmrg when connectors created and destroyed dynamically. 1580d6c0b56eSmrg 1581d6c0b56eSmrg Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com> 1582d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1583d6c0b56eSmrg 1584d6c0b56eSmrgcommit ea558e645786b08d75307716036045170e97b43e 1585d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com> 1586d6c0b56eSmrgDate: Fri Nov 20 17:03:05 2015 +0800 1587d6c0b56eSmrg 1588d6c0b56eSmrg Use render node for DRI3 if available 1589d6c0b56eSmrg 1590d6c0b56eSmrg Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> 1591d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1592d6c0b56eSmrg 1593d6c0b56eSmrgcommit 43c2dc1aab682d5b6ad49d24983d6382c4f305bb 1594d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1595d6c0b56eSmrgDate: Thu Nov 19 17:05:05 2015 +0900 1596d6c0b56eSmrg 1597d6c0b56eSmrg glamor: Deal with glamor_egl_destroy_textured_pixmap being removed 1598d6c0b56eSmrg 1599d6c0b56eSmrg When it's not available, it's safe to call down to the glamor 1600d6c0b56eSmrg DestroyPixmap hook instead. 1601d6c0b56eSmrg 1602d6c0b56eSmrg (ported from radeon commit 10b7c3def58bb34acc38f076bc230e25b454ab79) 1603d6c0b56eSmrg 1604d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1605d6c0b56eSmrg 1606d6c0b56eSmrgcommit 84cab5738a315e9825bd0864c4f0fc5b03eb81a1 1607d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1608d6c0b56eSmrgDate: Thu Nov 19 16:44:22 2015 +0900 1609d6c0b56eSmrg 1610d6c0b56eSmrg glamor: Restore all ScreenRec hooks during CloseScreen 1611d6c0b56eSmrg 1612d6c0b56eSmrg (ported from radeon commit 535e5438b2c32f774b9c8c27ee0289b4749548ef) 1613d6c0b56eSmrg 1614d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1615d6c0b56eSmrg 1616d6c0b56eSmrgcommit a00c050c2e5667ed815c51979a3cadb5146136ff 1617d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1618d6c0b56eSmrgDate: Thu Nov 19 17:55:53 2015 +0900 1619d6c0b56eSmrg 1620d6c0b56eSmrg Post 1.0.0 release version bump 1621d6c0b56eSmrg 1622d6c0b56eSmrgcommit 755e6ff2337cf615e3ba0854ccd533baec7144db 1623d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1624d6c0b56eSmrgDate: Thu Nov 19 17:28:19 2015 +0900 1625d6c0b56eSmrg 1626d6c0b56eSmrg Bump version for 1.0.0 release 1627d6c0b56eSmrg 1628d6c0b56eSmrgcommit 49c7d2be99aaf6d040e553065bdc461ce8d4769a 1629d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1630d6c0b56eSmrgDate: Thu Nov 19 17:14:54 2015 +0900 1631d6c0b56eSmrg 1632d6c0b56eSmrg Add amdgpu_pixmap.h to src/Makefile.am's EXTRA_DIST 1633d6c0b56eSmrg 1634d6c0b56eSmrg Fixes make distcheck. 1635d6c0b56eSmrg 1636d6c0b56eSmrgcommit d069ec5d27f5c8d2ab17b759b85293ef4113acf3 1637d6c0b56eSmrgAuthor: Stephen Chandler Paul <cpaul@redhat.com> 1638d6c0b56eSmrgDate: Wed Nov 11 18:10:55 2015 +0900 1639d6c0b56eSmrg 1640d6c0b56eSmrg Handle failures in setting a CRTC to a DRM mode properly 1641d6c0b56eSmrg 1642d6c0b56eSmrg This fixes a bug where running the card out of PPLL's when hotplugging 1643d6c0b56eSmrg another monitor would result in all of the displays going blank and 1644d6c0b56eSmrg failing to work properly until X was restarted or the user switched to 1645d6c0b56eSmrg another VT. 1646d6c0b56eSmrg 1647d6c0b56eSmrg [Michel Dänzer: Pass errno instead of -ret to strerror()] 1648d6c0b56eSmrg 1649d6c0b56eSmrg Signed-off-by: Stephen Chandler Paul <cpaul@redhat.com> 1650d6c0b56eSmrg (ported from radeon commit 7186a8713ba004de4991f21c1a9fc4abc62aeff4) 1651d6c0b56eSmrg 1652d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1653d6c0b56eSmrg 1654d6c0b56eSmrgcommit c8bddcf6c97b1338be3715f1fc5e0b17ce71c195 1655d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1656d6c0b56eSmrgDate: Wed Nov 11 18:09:59 2015 +0900 1657d6c0b56eSmrg 1658d6c0b56eSmrg Call xf86CrtcRotate from initial drmmode_set_desired_modes call 1659d6c0b56eSmrg 1660d6c0b56eSmrg Fixes various problems when rotation is specified in xorg.conf. 1661d6c0b56eSmrg 1662d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92475 1663d6c0b56eSmrg 1664d6c0b56eSmrg (ported from radeon commit 548e97b3b7d1e94075a54ca2bb4eb683025098a7) 1665d6c0b56eSmrg 1666d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1667d6c0b56eSmrg 1668d6c0b56eSmrgcommit 12815156f38ce3357f03901a78402db834577d11 1669d6c0b56eSmrgAuthor: Emil Velikov <emil.l.velikov@gmail.com> 1670d6c0b56eSmrgDate: Wed Nov 11 18:04:01 2015 +0900 1671d6c0b56eSmrg 1672d6c0b56eSmrg Do not link amdgpu_drv.so against libpciaccess 1673d6c0b56eSmrg 1674d6c0b56eSmrg Not used directly. 1675d6c0b56eSmrg 1676d6c0b56eSmrg Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> 1677d6c0b56eSmrg (ported from radeon commit fcb32231a38f9461d12720cbf72f63502197a711) 1678d6c0b56eSmrg 1679d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1680d6c0b56eSmrg 1681d6c0b56eSmrgcommit a02982b0ae0b79d2f183a1628edc05cafed8703a 1682d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1683d6c0b56eSmrgDate: Wed Nov 11 17:59:14 2015 +0900 1684d6c0b56eSmrg 1685d6c0b56eSmrg Skip disabled CRTCs in amdgpu_scanout_(do_)update 1686d6c0b56eSmrg 1687d6c0b56eSmrg The vblank / page flip ioctls don't work as expected for a disabled CRTC. 1688d6c0b56eSmrg 1689d6c0b56eSmrg (ported from radeon commit acc11877423ecd81a6e0a7f38466f80e43efee20) 1690d6c0b56eSmrg 1691d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1692d6c0b56eSmrg 1693d6c0b56eSmrgcommit 0ddd20600d0046afd17aa47ffebe86dfd91a2215 1694d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1695d6c0b56eSmrgDate: Wed Nov 11 17:44:16 2015 +0900 1696d6c0b56eSmrg 1697d6c0b56eSmrg Prefer drmModeSetCursor2 over drmModeSetCursor 1698d6c0b56eSmrg 1699d6c0b56eSmrg The former includes information about the position of the hotspot within 1700d6c0b56eSmrg the cursor image. 1701d6c0b56eSmrg 1702d6c0b56eSmrg Copied from xf86-video-modesetting. 1703d6c0b56eSmrg 1704d6c0b56eSmrg (ported from radeon commit c9f8f642fd495937400618a4fc25ecae3f8888fc) 1705d6c0b56eSmrg 1706d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1707d6c0b56eSmrg 1708d6c0b56eSmrgcommit 83a47c0ebe17caa79d12a8b2f94b59cc945452f5 1709d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1710d6c0b56eSmrgDate: Wed Nov 11 17:37:54 2015 +0900 1711d6c0b56eSmrg 1712d6c0b56eSmrg PRIME: Don't advertise offload capabilities when acceleration is disabled 1713d6c0b56eSmrg 1714d6c0b56eSmrg Xorg tends to crash if the user tries to actually use the offload 1715d6c0b56eSmrg capabilities with acceleration disabled. 1716d6c0b56eSmrg 1717d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57200 1718d6c0b56eSmrg (ported from radeon commit c74de9fec13fac2c836bb2a07ae6f90e1d61e667) 1719d6c0b56eSmrg 1720d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1721d6c0b56eSmrg 1722d6c0b56eSmrgcommit 560b7fe6dc66405762020f00e9a05918a36f3a17 1723d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1724d6c0b56eSmrgDate: Wed Nov 11 17:31:34 2015 +0900 1725d6c0b56eSmrg 1726d6c0b56eSmrg Rename Option "NoAccel" to "Accel" 1727d6c0b56eSmrg 1728d6c0b56eSmrg Removes the need for a double negation when forcing acceleration on. 1729d6c0b56eSmrg 1730d6c0b56eSmrg Note that this change is backwards compatible, as the option parser 1731d6c0b56eSmrg automagically handles the 'No' prefix. 1732d6c0b56eSmrg 1733d6c0b56eSmrg (ported from radeon commit cc615d06db0332fc6e673b55632bcc7bf957b44b) 1734d6c0b56eSmrg 1735d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1736d6c0b56eSmrg 1737d6c0b56eSmrgcommit ad77ad32c4a723447d3191d527cfa6de9f54d7ce 1738d6c0b56eSmrgAuthor: Adam Jackson <ajax@redhat.com> 1739d6c0b56eSmrgDate: Wed Nov 11 17:20:21 2015 +0900 1740d6c0b56eSmrg 1741d6c0b56eSmrg Use own thunk function instead of shadowUpdatePackedWeak 1742d6c0b56eSmrg 1743d6c0b56eSmrg I plan to delete the Weak functions from a future server. 1744d6c0b56eSmrg 1745d6c0b56eSmrg Signed-off-by: Adam Jackson <ajax@redhat.com> 1746d6c0b56eSmrg (ported from radeon commit 851b2cf8714618843725f6d067915375485ade9d) 1747d6c0b56eSmrg 1748d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1749d6c0b56eSmrg 1750d6c0b56eSmrgcommit f5ccea99c03b62acf3a25984aba617c665d80b7c 1751d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1752d6c0b56eSmrgDate: Wed Nov 11 17:16:58 2015 +0900 1753d6c0b56eSmrg 1754d6c0b56eSmrg dri2: Handle PRIME for source buffer as well in amdgpu_dri2_copy_region2 1755d6c0b56eSmrg 1756d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77810 1757d6c0b56eSmrg 1758d6c0b56eSmrg (ported from radeon commit c84230d686c078aac1dc98d82153f8b02521b2e1) 1759d6c0b56eSmrg 1760d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1761d6c0b56eSmrg 1762d6c0b56eSmrgcommit 92e7c93d2f9c3036da1a17d7fccccb6f9e9eaa3d 1763d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1764d6c0b56eSmrgDate: Mon Nov 2 18:29:24 2015 +0900 1765d6c0b56eSmrg 1766d6c0b56eSmrg Move scrn/info declaration inside USE_GLAMOR in amdgpu_dri3_fd_from_pixmap 1767d6c0b56eSmrg 1768d6c0b56eSmrg Fixes warning when building with --disable-glamor: 1769d6c0b56eSmrg 1770d6c0b56eSmrg ../../src/amdgpu_dri3.c: In function 'amdgpu_dri3_fd_from_pixmap': 1771d6c0b56eSmrg ../../src/amdgpu_dri3.c:135:16: warning: unused variable 'info' [-Wunused-variable] 1772d6c0b56eSmrg AMDGPUInfoPtr info = AMDGPUPTR(scrn); 1773d6c0b56eSmrg ^ 1774d6c0b56eSmrg 1775d6c0b56eSmrg Reported-by: Jammy Zhou <Jammy.Zhou@amd.com> 1776d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1777d6c0b56eSmrg 1778d6c0b56eSmrgcommit c9bd1399a13cea2e1331af2c826ca054b88db071 1779d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1780d6c0b56eSmrgDate: Mon Nov 2 18:21:50 2015 +0900 1781d6c0b56eSmrg 1782d6c0b56eSmrg Call AMDGPUFreeRec from AMDGPUFreeScreen_KMS even if info == NULL 1783d6c0b56eSmrg 1784d6c0b56eSmrg It's safe now. 1785d6c0b56eSmrg 1786d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1787d6c0b56eSmrg 1788d6c0b56eSmrgcommit fb8444e731765588c0ff1e9053c1c7b73f5f0907 1789d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1790d6c0b56eSmrgDate: Mon Nov 2 18:20:41 2015 +0900 1791d6c0b56eSmrg 1792d6c0b56eSmrg Don't use AMDGPUEntPriv in AMDGPUFreeRec 1793d6c0b56eSmrg 1794d6c0b56eSmrg It crashes if info == NULL. 1795d6c0b56eSmrg 1796d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1797d6c0b56eSmrg 1798d6c0b56eSmrgcommit 8e7ee03f55c2f3874f6e84daeb5700f8b8037a51 1799d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1800d6c0b56eSmrgDate: Wed Oct 28 17:53:27 2015 +0900 1801d6c0b56eSmrg 1802d6c0b56eSmrg Remove amdgpu_reference_drm_fd 1803d6c0b56eSmrg 1804d6c0b56eSmrg Increase pAMDGPUEnt->fd_ref in the probe code instead when we're reusing 1805d6c0b56eSmrg the existing fd. 1806d6c0b56eSmrg 1807d6c0b56eSmrg The previous reference counting was imbalanced, so pAMDGPUEnt->fd_ref 1808d6c0b56eSmrg could never go to 0. 1809d6c0b56eSmrg 1810d6c0b56eSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 1811d6c0b56eSmrg 1812d6c0b56eSmrgcommit 6bab8fabb37eb131e131ce59446c214ded28f779 1813d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1814d6c0b56eSmrgDate: Wed Oct 28 17:44:09 2015 +0900 1815d6c0b56eSmrg 1816d6c0b56eSmrg Remove info->dri2.drm_fd and info->drmmode->fd 1817d6c0b56eSmrg 1818d6c0b56eSmrg Use pAMDGPUEnt->fd everywhere instead. 1819d6c0b56eSmrg 1820d6c0b56eSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 1821d6c0b56eSmrg 1822d6c0b56eSmrgcommit 0530e39cc6b7340163e7f6bb6d82719d102ee6e9 1823d6c0b56eSmrgAuthor: Jammy Zhou <jammy.zhou@amd.com> 1824d6c0b56eSmrgDate: Thu Oct 29 17:08:01 2015 +0900 1825d6c0b56eSmrg 1826d6c0b56eSmrg Pass struct pci_device *pci_dev directly to amdgpu_get_scrninfo 1827d6c0b56eSmrg 1828d6c0b56eSmrg Instead of throwing away the type information by passing it as a void*. 1829d6c0b56eSmrg 1830d6c0b56eSmrg Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> 1831d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1832d6c0b56eSmrg 1833d6c0b56eSmrgcommit edf72afee3a25eae9827b4de3a013b541b78e213 1834d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com> 1835d6c0b56eSmrgDate: Wed Oct 28 21:24:29 2015 +0800 1836d6c0b56eSmrg 1837d6c0b56eSmrg Fix crash in PCI probe path (v4) 1838d6c0b56eSmrg 1839d6c0b56eSmrg The crash is caused by the NULL value returned by AMDGPUPTR(pScrn), 1840d6c0b56eSmrg because the driverPrivate is not allocated yet in PciProbe phase, 1841d6c0b56eSmrg and it is usually done in the PreInit phase. 1842d6c0b56eSmrg 1843d6c0b56eSmrg Use pAMDGPUEnt->fd instead of info->dri2.drm_fd to avoid AMDGPUInfoPtr 1844d6c0b56eSmrg related code in amdgpu_open_drm_master, so that the crash can be fixed. 1845d6c0b56eSmrg 1846d6c0b56eSmrg v4: (md) Remove unused parameter entity_num, split out logically 1847d6c0b56eSmrg separate changes 1848d6c0b56eSmrg v3: some more cleanup 1849d6c0b56eSmrg v2: switch to pAMDGPUEnt->fd, and update the commit message 1850d6c0b56eSmrg 1851d6c0b56eSmrg Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> 1852d6c0b56eSmrg Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> 1853d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v3) 1854d6c0b56eSmrg 1855d6c0b56eSmrgcommit cef725121eb0e56aa54d9c4665e36047373f4db7 1856d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1857d6c0b56eSmrgDate: Wed Oct 28 17:56:13 2015 +0900 1858d6c0b56eSmrg 1859d6c0b56eSmrg Remove dead code from probe paths 1860d6c0b56eSmrg 1861d6c0b56eSmrg amdgpu_get_scrninfo allocates the memory pointed to by pAMDGPUEnt just 1862d6c0b56eSmrg before it calls amdgpu_open_drm_master, so pAMDGPUEnt->fd is always 0 1863d6c0b56eSmrg in the latter. 1864d6c0b56eSmrg 1865d6c0b56eSmrg Also, no need to clear pAMDGPUEnt->fd just before freeing the memory 1866d6c0b56eSmrg it's stored in. 1867d6c0b56eSmrg 1868d6c0b56eSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 1869d6c0b56eSmrg 1870d6c0b56eSmrgcommit 3b0a3c89b53b3ebe21a9d703a4dbff6e57c65a57 1871d6c0b56eSmrgAuthor: Samuel Li <samuel.li@amd.com> 1872d6c0b56eSmrgDate: Thu Oct 22 12:50:21 2015 -0400 1873d6c0b56eSmrg 1874d6c0b56eSmrg Add Stoney support 1875d6c0b56eSmrg 1876d6c0b56eSmrg (agd): rebase 1877d6c0b56eSmrg 1878d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1879d6c0b56eSmrg Signed-off-by: Samuel Li <samuel.li@amd.com> 1880d6c0b56eSmrg 1881d6c0b56eSmrgcommit 9c8b7ebe15eec7abd5dc10ad6ccecbc57225494a 1882d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1883d6c0b56eSmrgDate: Wed Oct 21 17:18:44 2015 +0900 1884d6c0b56eSmrg 1885d6c0b56eSmrg Revert "Handle RandR CRTC transforms properly" 1886d6c0b56eSmrg 1887d6c0b56eSmrg This reverts commit 175251645fec1a3d19f498e1cd1e655374c67801. 1888d6c0b56eSmrg 1889d6c0b56eSmrg I accidentally pushed this patch. 1890d6c0b56eSmrg 1891d6c0b56eSmrgcommit 0a6ba4bf50128464a30951721b0c72e748fb89bc 1892d6c0b56eSmrgAuthor: Darren Powell <darren.powell@amd.com> 1893d6c0b56eSmrgDate: Tue Oct 20 16:56:54 2015 -0400 1894d6c0b56eSmrg 1895d6c0b56eSmrg Add Option "TearFree" to manpage 1896d6c0b56eSmrg 1897d6c0b56eSmrg This was missed in commit c57da33308a81fa575179238a0415abcb8b34908. 1898d6c0b56eSmrg 1899d6c0b56eSmrg Signed-off-by: Darren Powell <darren.powell@amd.com> 1900d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1901d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1902d6c0b56eSmrg 1903d6c0b56eSmrgcommit 175251645fec1a3d19f498e1cd1e655374c67801 1904d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1905d6c0b56eSmrgDate: Thu Oct 15 16:35:51 2015 +0900 1906d6c0b56eSmrg 1907d6c0b56eSmrg Handle RandR CRTC transforms properly 1908d6c0b56eSmrg 1909d6c0b56eSmrgcommit 6000aef4e2f0a121b94023484406fb6f04688f74 1910d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 1911d6c0b56eSmrgDate: Wed Oct 14 13:25:59 2015 -0400 1912d6c0b56eSmrg 1913d6c0b56eSmrg Clean up amdgpu_dri2_create_buffer2() 1914d6c0b56eSmrg 1915d6c0b56eSmrg Remove the depth_pixmap variable from the function and clear 1916d6c0b56eSmrg out any dead/odd behaviour that results. 1917d6c0b56eSmrg 1918d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 1919d6c0b56eSmrg 1920d6c0b56eSmrgcommit 21e72fb2418b5cc7fc849a9cf951186e209036b0 1921d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1922d6c0b56eSmrgDate: Fri Oct 9 18:38:47 2015 +0900 1923d6c0b56eSmrg 1924d6c0b56eSmrg Properly handle drmModeAddFB failure in drmmode_crtc_scanout_allocate 1925d6c0b56eSmrg 1926d6c0b56eSmrg We were printing an error message, but not propagating the failure. That 1927d6c0b56eSmrg would probably lead to trouble down the road. 1928d6c0b56eSmrg 1929d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1930d6c0b56eSmrg 1931d6c0b56eSmrgcommit 8da1d0c870e1081d77925807d6e3bbc61a23f54f 1932d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1933d6c0b56eSmrgDate: Fri Oct 9 18:59:16 2015 +0900 1934d6c0b56eSmrg 1935d6c0b56eSmrg Eliminate redundant data parameter from drmmode_crtc_scanout_create 1936d6c0b56eSmrg 1937d6c0b56eSmrg drmmode_crtc_scanout_create just needs to call 1938d6c0b56eSmrg drmmode_crtc_scanout_allocate when scanout->bo is NULL. 1939d6c0b56eSmrg 1940d6c0b56eSmrg This makes it clearer to the reader / compiler that 1941d6c0b56eSmrg drmmode_crtc_scanout_create doesn't dereference scanout->bo when it's 1942d6c0b56eSmrg NULL. 1943d6c0b56eSmrg 1944d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1945d6c0b56eSmrg 1946d6c0b56eSmrgcommit dc40582d5ff94d812cbc08f95cf14b80cd0f410d 1947d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 1948d6c0b56eSmrgDate: Wed Oct 7 16:19:22 2015 +0900 1949d6c0b56eSmrg 1950d6c0b56eSmrg Don't advertise rotation support without hardware acceleration v2 1951d6c0b56eSmrg 1952d6c0b56eSmrg Rotation currently doesn't work without acceleration (doesn't actually 1953d6c0b56eSmrg rotate with Option "NoAccel", crashes with Option "AccelMethod" "none" 1954d6c0b56eSmrg or when glamor fails to initialize) and would probably be too slow 1955d6c0b56eSmrg anyway. 1956d6c0b56eSmrg 1957d6c0b56eSmrg v2: Also remove now dead code checking for ShadowFB from 1958d6c0b56eSmrg drmmode_crtc_scanout_allocate(). 1959d6c0b56eSmrg 1960d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 1961d6c0b56eSmrg 1962d6c0b56eSmrgcommit 460560502a1bdf26d06f3c30df46fa9f28ffb9e5 1963d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 1964d6c0b56eSmrgDate: Tue Oct 6 08:49:54 2015 -0400 1965d6c0b56eSmrg 1966d6c0b56eSmrg Simplify drmmode_set_mode_major() and avoid leaking memory. 1967d6c0b56eSmrg 1968d6c0b56eSmrg The function would leak the memory allocated for output_ids. This 1969d6c0b56eSmrg patch addresses that as well as simplifies the logic somewhat. 1970d6c0b56eSmrg 1971d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 1972d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1973d6c0b56eSmrg 1974d6c0b56eSmrgcommit 56398d6651dfc4935cbd117ad861e1800077c73c 1975d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 1976d6c0b56eSmrgDate: Tue Oct 6 08:43:12 2015 -0400 1977d6c0b56eSmrg 1978d6c0b56eSmrg Avoid NULL dereference if drmmode_crtc_scanout_allocate fails 1979d6c0b56eSmrg 1980d6c0b56eSmrg This avoids a NULL dereference if the memory allocation fails. 1981d6c0b56eSmrg 1982d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 1983d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1984d6c0b56eSmrg 1985d6c0b56eSmrgcommit 4b92b960c7705be8b3a5dee17b2341864d7ca9bb 1986d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 1987d6c0b56eSmrgDate: Mon Oct 5 10:00:09 2015 -0400 1988d6c0b56eSmrg 1989d6c0b56eSmrg cleanup the entity rec 1990d6c0b56eSmrg 1991d6c0b56eSmrg Based on radeon commit: b32a0a3de84a44b9af4f1ca8be19f10d7fa31b12 1992d6c0b56eSmrg 1993d6c0b56eSmrg Some of these were set, some of them were 1994d6c0b56eSmrg always opposites, so clean things up. 1995d6c0b56eSmrg 1996d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 1997d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 1998d6c0b56eSmrg 1999d6c0b56eSmrgcommit fe100fd6bf483228eaf64b959c56a68e8dac4447 2000d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2001d6c0b56eSmrgDate: Mon Oct 5 10:45:33 2015 -0400 2002d6c0b56eSmrg 2003d6c0b56eSmrg present: Handle DPMS off in radeon_present_get_ust_msc 2004d6c0b56eSmrg 2005d6c0b56eSmrg Based on radeon commit: 95f5d09e3667ded027ae648c97eb4737d8bf67c5 2006d6c0b56eSmrg 2007d6c0b56eSmrg The DRM_IOCTL_WAIT_VBLANK ioctl may return an error during DPMS off, 2008d6c0b56eSmrg which would trigger an error message in drmmode_crtc_get_ust_msc. 2009d6c0b56eSmrg 2010d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2011d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2012d6c0b56eSmrg 2013d6c0b56eSmrgcommit bfa925a04815cee5fd57b99447cb2ee0e158036c 2014d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2015d6c0b56eSmrgDate: Mon Oct 5 10:10:51 2015 -0400 2016d6c0b56eSmrg 2017d6c0b56eSmrg present: Look at all CRTCs to determine if we can flip 2018d6c0b56eSmrg 2019d6c0b56eSmrg Based on radeon commit 211862b777d0be251a4662f5dd24f2d400544c09 2020d6c0b56eSmrg 2021d6c0b56eSmrg Inspired by modesetting driver change by Kenneth Graunke. 2022d6c0b56eSmrg 2023d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2024d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2025d6c0b56eSmrg 2026d6c0b56eSmrgcommit a1e47e76322619ed037ebce27974a4e3792940c2 2027d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2028d6c0b56eSmrgDate: Mon Oct 5 10:41:22 2015 -0400 2029d6c0b56eSmrg 2030d6c0b56eSmrg present: Fall back to modeset for unflip operation 2031d6c0b56eSmrg 2032d6c0b56eSmrg Based on radeon commit: 802d33e474a82262d9cdf11b03568b0c4929cd0d 2033d6c0b56eSmrg 2034d6c0b56eSmrg It's not always possible to use the page flip ioctl for this, e.g. 2035d6c0b56eSmrg during DPMS off. We were previously just skipping the unflip in that 2036d6c0b56eSmrg case, which could result in hangs when setting DPMS off while a 2037d6c0b56eSmrg fullscreen Present app is running, e.g. at the GNOME3 lock screen. 2038d6c0b56eSmrg 2039d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2040d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2041d6c0b56eSmrg 2042d6c0b56eSmrgcommit bac21dfc8e60a07f08158b13fab1f3a9b9d27d1b 2043d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2044d6c0b56eSmrgDate: Mon Oct 5 10:37:50 2015 -0400 2045d6c0b56eSmrg 2046d6c0b56eSmrg Don't attempt a DRI2/Present page flip while the other one is flipping 2047d6c0b56eSmrg 2048d6c0b56eSmrg Based on radeon commit 49f5b0bc301414df049e00d226034e3d6e56421b 2049d6c0b56eSmrg 2050d6c0b56eSmrg Fixes corrupted display and hangs when switching between DRI2 and DRI3 2051d6c0b56eSmrg fullscreen apps, e.g. a compositor using DRI3 and a fullscreen app using 2052d6c0b56eSmrg DRI2 or vice versa. 2053d6c0b56eSmrg 2054d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2055d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2056d6c0b56eSmrg 2057d6c0b56eSmrgcommit a5f7f2e68bad1935f5ad52286033237467f77302 2058d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2059d6c0b56eSmrgDate: Mon Oct 5 13:12:23 2015 -0400 2060d6c0b56eSmrg 2061d6c0b56eSmrg Move amdgpu_drm_handler/abort_proc fields to drmmode_flipdata_re 2062d6c0b56eSmrg 2063d6c0b56eSmrg Based on radeon commit de5ddd09db82141b263338dcf0c28e01f58268ee 2064d6c0b56eSmrg 2065d6c0b56eSmrg Their values are the same for all DRM flip ioctl calls within a single 2066d6c0b56eSmrg radeon_do_pageflip() call. 2067d6c0b56eSmrg 2068d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2069d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2070d6c0b56eSmrg 2071d6c0b56eSmrgcommit e14e3560bff2537d3ad4c93d2b31442a122cde66 2072d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2073d6c0b56eSmrgDate: Mon Oct 5 13:08:43 2015 -0400 2074d6c0b56eSmrg 2075d6c0b56eSmrg Simplify amdgpu_do_pageflip() error handling slightly more 2076d6c0b56eSmrg 2077d6c0b56eSmrg Based on radeon commit e8c0f6319fbf4c3ea11e22ab1a68837031bdec8c 2078d6c0b56eSmrg 2079d6c0b56eSmrg We don't need the local variable old_fb_id. 2080d6c0b56eSmrg 2081d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2082d6c0b56eSmrg 2083d6c0b56eSmrg [ Michel Dänzer: fix up slightly to better match radeon formatting ] 2084d6c0b56eSmrg 2085d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2086d6c0b56eSmrg 2087d6c0b56eSmrgcommit e9621ec0e2400f62db320c560a739b29258edb87 2088d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2089d6c0b56eSmrgDate: Mon Oct 5 09:34:47 2015 -0400 2090d6c0b56eSmrg 2091d6c0b56eSmrg Increase robustness against DRM page flip ioctl failures 2092d6c0b56eSmrg 2093d6c0b56eSmrg Based on radeon commit 8fc22360d5520469c82092ccb0fcf2af330c573f 2094d6c0b56eSmrg 2095d6c0b56eSmrg Centralize cleanup, only clean up things that have been allocated for 2096d6c0b56eSmrg the failed ioctl call. 2097d6c0b56eSmrg 2098d6c0b56eSmrg Fixes double-free after a flip ioctl failure. 2099d6c0b56eSmrg 2100d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89681 2101d6c0b56eSmrg 2102d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2103d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2104d6c0b56eSmrg 2105d6c0b56eSmrgcommit db3bb2061b9ac16b0922d9afae99874820356a04 2106d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2107d6c0b56eSmrgDate: Tue Sep 29 13:07:04 2015 -0400 2108d6c0b56eSmrg 2109d6c0b56eSmrg Clean up allocation in AMDGPUInitVideo() 2110d6c0b56eSmrg 2111d6c0b56eSmrg The allocation of the adapters should use the correct sizeof (even if 2112d6c0b56eSmrg allocating an array of pointers). 2113d6c0b56eSmrg 2114d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2115d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2116d6c0b56eSmrg 2117d6c0b56eSmrgcommit 94caf7ac777134b8396aa762a506053179bbb4c6 2118d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2119d6c0b56eSmrgDate: Thu Oct 1 13:08:41 2015 -0400 2120d6c0b56eSmrg 2121d6c0b56eSmrg Avoid leaking memory on output. 2122d6c0b56eSmrg 2123d6c0b56eSmrg Based on radeon commit 63dc36dc49f93cb00111b497ab6805194bc9d240 2124d6c0b56eSmrg 2125d6c0b56eSmrg and 2nd patch: 2126d6c0b56eSmrg 2127d6c0b56eSmrg Proper leak fix, previous leak fix was bogus. 2128d6c0b56eSmrg 2129d6c0b56eSmrg Based on radeon commit b8ec9ed4fe86952763b963c86f0af0dcae69aa6c 2130d6c0b56eSmrg 2131d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2132d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2133d6c0b56eSmrg 2134d6c0b56eSmrgcommit f035faec041cb5df65c78effa58eb50197cedf88 2135d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2136d6c0b56eSmrgDate: Thu Oct 1 12:56:05 2015 -0400 2137d6c0b56eSmrg 2138d6c0b56eSmrg add support for DP 1.2 display hotplug 2139d6c0b56eSmrg 2140d6c0b56eSmrg Based on radeon commit 2f11dcd43966cf2ee26e61960fd72e6644f5e037 2141d6c0b56eSmrg 2142d6c0b56eSmrg > This allows for dynamic creation of conneectors when the 2143d6c0b56eSmrg > kernel tells us. 2144d6c0b56eSmrg > 2145d6c0b56eSmrg > v2: fix dpms off crash 2146d6c0b56eSmrg 2147d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2148d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2149d6c0b56eSmrg 2150d6c0b56eSmrgcommit aee72b29210d79dbf41bde6eef16d7fe817e6cf4 2151d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2152d6c0b56eSmrgDate: Thu Oct 1 12:29:36 2015 -0400 2153d6c0b56eSmrg 2154d6c0b56eSmrg move output name creation to its own function 2155d6c0b56eSmrg 2156d6c0b56eSmrg Based on radeon commit c88424d1f4aaa78b569e5d44f0b4a47de2f422f4 2157d6c0b56eSmrg 2158d6c0b56eSmrg > The secondary indent is deliberate to make the next patch more 2159d6c0b56eSmrg > parseable for mst support. 2160d6c0b56eSmrg 2161d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2162d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2163d6c0b56eSmrg 2164d6c0b56eSmrgcommit 0846abeace649d27a5f2c17373e717f92d246797 2165d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2166d6c0b56eSmrgDate: Thu Oct 1 12:13:21 2015 -0400 2167d6c0b56eSmrg 2168d6c0b56eSmrg stop caching mode resources 2169d6c0b56eSmrg 2170d6c0b56eSmrg Based on radeon commit 32b003cb7657e07d5af6338ad44d768eda87fd33 2171d6c0b56eSmrg 2172d6c0b56eSmrg > This is step one towards MST connector hotplug support, 2173d6c0b56eSmrg > it stop caching the mode resources structure, and 2174d6c0b56eSmrg > just passes a pointer to it around. 2175d6c0b56eSmrg 2176d6c0b56eSmrg With a few tweaks to match the state of the AMDGPU tree. 2177d6c0b56eSmrg 2178d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2179d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2180d6c0b56eSmrg 2181d6c0b56eSmrgcommit 4ca8f957e0b417b099f625470db98a54531a731d 2182d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2183d6c0b56eSmrgDate: Thu Oct 1 13:16:15 2015 -0400 2184d6c0b56eSmrg 2185d6c0b56eSmrg Silence type mismatch warning. 2186d6c0b56eSmrg 2187d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2188d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2189d6c0b56eSmrg 2190d6c0b56eSmrgcommit a79735ab1499c1f7814036d1b19ff465705c5f45 2191d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2192d6c0b56eSmrgDate: Thu Oct 1 10:51:07 2015 -0400 2193d6c0b56eSmrg 2194d6c0b56eSmrg Add support for server managed fds 2195d6c0b56eSmrg 2196d6c0b56eSmrg Based on radeon commit ed0cfbb4fe77146b0b38f777bc28f3a4ea6da07f 2197d6c0b56eSmrg 2198d6c0b56eSmrg and 2nd patch: 2199d6c0b56eSmrg 2200d6c0b56eSmrg Fix building on older servers without xf86platformBus.h 2201d6c0b56eSmrg 2202d6c0b56eSmrg Based on radeon commit b50da3b96c212086cb58501dbe988d64f1f35b6d 2203d6c0b56eSmrg 2204d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2205d6c0b56eSmrg 2206d6c0b56eSmrg [ Michel Dänzer: Fixed up amdgpu_kernel_open_fd() not to need 2207d6c0b56eSmrg AMDGPUEntPriv(), which doesn't work yet at that point ] 2208d6c0b56eSmrg 2209d6c0b56eSmrg Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> 2210d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2211d6c0b56eSmrg 2212d6c0b56eSmrgcommit b93934a9ed5e92f3a6eac6554c5c4fa2967a6dd0 2213d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2214d6c0b56eSmrgDate: Thu Oct 1 10:05:36 2015 -0400 2215d6c0b56eSmrg 2216d6c0b56eSmrg Add amdgpu_open_drm_master helper function 2217d6c0b56eSmrg 2218d6c0b56eSmrg Based on radeon commit 3d7861fe112f25874319d4cdc12b745fbcd359cf 2219d6c0b56eSmrg 2220d6c0b56eSmrg > This is a preparation patch for adding server-managed-fd support without it 2221d6c0b56eSmrg > turning into a goto fest. 2222d6c0b56eSmrg 2223d6c0b56eSmrg With appropriate modifications because the open call stack is different 2224d6c0b56eSmrg in the amdgpu tree. 2225d6c0b56eSmrg 2226d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2227d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2228d6c0b56eSmrg 2229d6c0b56eSmrgcommit f5c3fd0b57cf9e392bf591110568637937a1d338 2230d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2231d6c0b56eSmrgDate: Thu Oct 1 09:13:57 2015 -0400 2232d6c0b56eSmrg 2233d6c0b56eSmrg Cleaning up for server-fd support 2234d6c0b56eSmrg 2235d6c0b56eSmrg Based on radeon commit a63342ad15408071437c80b411d14196f3288aed 2236d6c0b56eSmrg 2237d6c0b56eSmrg > radeon_open_drm_master get rid of unnecessary goto 2238d6c0b56eSmrg 2239d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2240d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2241d6c0b56eSmrg 2242d6c0b56eSmrgcommit 3055724aef76a624718f26d5f0f9e9d567ffbcfb 2243d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2244d6c0b56eSmrgDate: Thu Sep 24 13:08:31 2015 -0400 2245d6c0b56eSmrg 2246d6c0b56eSmrg Simplify pick best crtc to fold two loops into one 2247d6c0b56eSmrg 2248d6c0b56eSmrg This patch folds the two for loops from amdgpu_pick_best_crtc() into 2249d6c0b56eSmrg one to reduce the LOC and make the routine easier to read. 2250d6c0b56eSmrg 2251d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2252d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2253d6c0b56eSmrg 2254d6c0b56eSmrgcommit 9945b4ae1664ab815b39ff07e7b66cfa7f942dfa 2255d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2256d6c0b56eSmrgDate: Wed Sep 9 09:38:02 2015 -0400 2257d6c0b56eSmrg 2258d6c0b56eSmrg Avoid use-after-free in drmmode_output_destroy() 2259d6c0b56eSmrg 2260d6c0b56eSmrg The encoders array is freed before potentially all of the elements of 2261d6c0b56eSmrg the array are individually freed. 2262d6c0b56eSmrg 2263d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2264d6c0b56eSmrg Reviewed-by: Christian König <christian.koenig@amd.com> 2265d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2266d6c0b56eSmrg Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> (cosmetic fixups) 2267d6c0b56eSmrg 2268d6c0b56eSmrgcommit 36b3faebdd1d2090a286616eeeb131d15e9a1386 2269d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2270d6c0b56eSmrgDate: Wed Sep 9 09:36:59 2015 -0400 2271d6c0b56eSmrg 2272d6c0b56eSmrg Avoid use-after-free in amdgpu_kernel_open_fd() 2273d6c0b56eSmrg 2274d6c0b56eSmrg If the device cannot be opened avoid re-using busid after it has been 2275d6c0b56eSmrg freed. 2276d6c0b56eSmrg 2277d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2278d6c0b56eSmrg Reviewed-by: Christian König <christian.koenig@amd.com> 2279d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2280d6c0b56eSmrg Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> (cosmetic fixups) 2281d6c0b56eSmrg 2282d6c0b56eSmrgcommit 8823c3d4c6db70cff7699b31088f2d92db8faaf4 2283d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com> 2284d6c0b56eSmrgDate: Wed Sep 9 09:34:38 2015 -0400 2285d6c0b56eSmrg 2286d6c0b56eSmrg dri2: Avoid calculation with undefined msc value 2287d6c0b56eSmrg 2288d6c0b56eSmrg If the get_msc() call fails for any reason we should avoid updating the 2289d6c0b56eSmrg vblank counter delta with undefined data. 2290d6c0b56eSmrg 2291d6c0b56eSmrg Signed-off-by: Tom St Denis <tom.stdenis@amd.com> 2292d6c0b56eSmrg Reviewed-by: Christian König <christian.koenig@amd.com> 2293d6c0b56eSmrg Acked-by: Alex Deucher <alexander.deucher@amd.com> 2294d6c0b56eSmrg Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> (minor fixups) 2295d6c0b56eSmrg 2296d6c0b56eSmrgcommit 63948ea091a9b324327ade7ec4fc5d67ca7e6f6f 2297d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2298d6c0b56eSmrgDate: Fri Aug 14 18:41:57 2015 +0900 2299d6c0b56eSmrg 2300d6c0b56eSmrg DRI2: Keep MSC monotonic when moving window between CRTCs 2301d6c0b56eSmrg 2302d6c0b56eSmrg This mirrors the DRI3 implementation in xserver. Fixes VDPAU video 2303d6c0b56eSmrg playback hanging when moving the window between CRTCs. 2304d6c0b56eSmrg 2305d6c0b56eSmrg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66384 2306d6c0b56eSmrg 2307d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2308d6c0b56eSmrg 2309d6c0b56eSmrgcommit 55a4461bd95698cb8d52f9f6c28583f8f81afb4e 2310d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2311d6c0b56eSmrgDate: Fri Aug 7 11:46:31 2015 +0900 2312d6c0b56eSmrg 2313d6c0b56eSmrg Wait for scanout BO initialization to finish before setting mode 2314d6c0b56eSmrg 2315d6c0b56eSmrg This should avoid intermittent artifacts which could sometimes be visible 2316d6c0b56eSmrg when setting a new scanout pixmap, e.g. on server startup or when 2317d6c0b56eSmrg changing resolutions. 2318d6c0b56eSmrg 2319d6c0b56eSmrg (Ported from radeon commit 3791fceabf2cb037467dc41c15364e9f9ec1e47e) 2320d6c0b56eSmrg 2321d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2322d6c0b56eSmrg 2323d6c0b56eSmrgcommit 4c425e9c5c038504a0f0498dd800ab1fb40bf0c5 2324d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2325d6c0b56eSmrgDate: Fri Aug 7 12:39:24 2015 +0900 2326d6c0b56eSmrg 2327d6c0b56eSmrg glamor: Add amdgpu_glamor_finish to wait for glamor rendering to finish 2328d6c0b56eSmrg 2329d6c0b56eSmrg This is a bit sneaky, because it calls glFinish directly from the driver, 2330d6c0b56eSmrg but it seems to work fine. 2331d6c0b56eSmrg 2332d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2333d6c0b56eSmrg 2334d6c0b56eSmrgcommit bb989e173dc364a7d68e50d7e819d0e0ee133d2f 2335d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2336d6c0b56eSmrgDate: Fri Aug 7 11:43:48 2015 +0900 2337d6c0b56eSmrg 2338d6c0b56eSmrg Only call drmmode_copy_fb (at most) once on server startup 2339d6c0b56eSmrg 2340d6c0b56eSmrg It doesn't make sense to copy the screen contents from console when VT 2341d6c0b56eSmrg switching back to Xorg or when Xorg resets. 2342d6c0b56eSmrg 2343d6c0b56eSmrg Fixes intermittent artifacts when VT switching back from console to the 2344d6c0b56eSmrg gdm login screen. 2345d6c0b56eSmrg 2346d6c0b56eSmrg (Ported from radeon commit 4e3dfa69e4630df2e0ec0f5b81d61159757c4664) 2347d6c0b56eSmrg 2348d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2349d6c0b56eSmrg 2350d6c0b56eSmrgcommit ebe2c020fbf2ef8de01fc50b201ab23ddb9fb13b 2351d6c0b56eSmrgAuthor: Mario Kleiner <mario.kleiner.de@gmail.com> 2352d6c0b56eSmrgDate: Mon Aug 10 23:34:40 2015 +0200 2353d6c0b56eSmrg 2354d6c0b56eSmrg Make selection between DRI2 and DRI3 consistent with other drivers. (v2) 2355d6c0b56eSmrg 2356d6c0b56eSmrg Add Option "DRI" to allow selection of maximum DRI level. 2357d6c0b56eSmrg 2358d6c0b56eSmrg This allows the user to select the maximum level of DRI 2359d6c0b56eSmrg implementation to use, DRI2 or DRI3. It replaces the old 2360d6c0b56eSmrg option "DRI3" which had exactly the same purpose, but 2361d6c0b56eSmrg differs from the method used in both intel ddx and nouveau ddx. 2362d6c0b56eSmrg Make this consistent before a new stable driver is released. 2363d6c0b56eSmrg 2364d6c0b56eSmrg v2: Retain handling of old Option "DRI3" for backwards 2365d6c0b56eSmrg compatibility, but Option "DRI" will take precedence 2366d6c0b56eSmrg over "DRI3" if both are provided. 2367d6c0b56eSmrg 2368d6c0b56eSmrg Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> 2369d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2370d6c0b56eSmrg 2371d6c0b56eSmrgcommit c9611a2aa0f8d3bb55c552353740d60f6e4f63a0 2372d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com> 2373d6c0b56eSmrgDate: Tue Jul 7 22:46:34 2015 -0400 2374d6c0b56eSmrg 2375d6c0b56eSmrg add fiji pci id 2376d6c0b56eSmrg 2377d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2378d6c0b56eSmrg Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2379d6c0b56eSmrg 2380d6c0b56eSmrgcommit 2622ac1554761b8824bfbbb2e3051a632ee38ce7 2381d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com> 2382d6c0b56eSmrgDate: Tue Jul 7 22:46:08 2015 -0400 2383d6c0b56eSmrg 2384d6c0b56eSmrg Add fiji support 2385d6c0b56eSmrg 2386d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2387d6c0b56eSmrg Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2388d6c0b56eSmrg 2389d6c0b56eSmrgcommit 7a49d8728d17875206a84fd1023f62b37c4a9f51 2390d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2391d6c0b56eSmrgDate: Thu Aug 6 18:21:30 2015 +0900 2392d6c0b56eSmrg 2393d6c0b56eSmrg On screen resize, clear the new buffer before displaying it 2394d6c0b56eSmrg 2395d6c0b56eSmrg Fixes garbage being intermittently visible during a screen resize. 2396d6c0b56eSmrg 2397d6c0b56eSmrg (Ported from radeon commit 80f3d727f93cb6efedd2b39338d2301035965fe2) 2398d6c0b56eSmrg 2399d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2400d6c0b56eSmrg 2401d6c0b56eSmrgcommit 9f988bf1dc9d4cb92926c051ed8f15e9ba58a016 2402d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2403d6c0b56eSmrgDate: Thu Aug 6 17:50:11 2015 +0900 2404d6c0b56eSmrg 2405d6c0b56eSmrg Make drmmode_copy_fb() work with glamor 2406d6c0b56eSmrg 2407d6c0b56eSmrg Needed for Xorg -background none. 2408d6c0b56eSmrg 2409d6c0b56eSmrg (Ported from radeon commit 3999bf88cdb192fe2f30b03bd2ed6f6a3f9f9057) 2410d6c0b56eSmrg 2411d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2412d6c0b56eSmrg 2413d6c0b56eSmrgcommit 13cf61bd8d46b0059f26120a8902da6f86e6bd11 2414d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2415d6c0b56eSmrgDate: Thu Aug 6 17:46:38 2015 +0900 2416d6c0b56eSmrg 2417d6c0b56eSmrg Update scanout pixmap contents before setting a mode with it 2418d6c0b56eSmrg 2419d6c0b56eSmrg This ensures the scanout pixmaps used for Option "TearFree" and Option 2420d6c0b56eSmrg "ShadowPrimary" have been initialized when their initial mode is set. 2421d6c0b56eSmrg 2422d6c0b56eSmrg (Ported from radeon commit a4a8cdbcc10c1c5f07485a2af9e9e81e490c3e1d) 2423d6c0b56eSmrg 2424d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2425d6c0b56eSmrg 2426d6c0b56eSmrgcommit 15050aabf256c17250d1fca0bfac97fc6707b195 2427d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2428d6c0b56eSmrgDate: Thu Aug 6 17:37:11 2015 +0900 2429d6c0b56eSmrg 2430d6c0b56eSmrg Defer initial modeset until the first BlockHandler invocation 2431d6c0b56eSmrg 2432d6c0b56eSmrg This ensures that the screen pixmap contents have been initialized when 2433d6c0b56eSmrg the initial modes are set. 2434d6c0b56eSmrg 2435d6c0b56eSmrg (Ported from radeon commits 673e1c7637687c74fc9bdeeeffb7ace0d04b734f and 2436d6c0b56eSmrg 1584dc545c78e0bce8d4b4b9f26b568e2c211453) 2437d6c0b56eSmrg 2438d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2439d6c0b56eSmrg 2440d6c0b56eSmrgcommit 96b5364496222f1b3afb9caad458f16f156b6c47 2441d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2442d6c0b56eSmrgDate: Thu Aug 6 17:32:45 2015 +0900 2443d6c0b56eSmrg 2444d6c0b56eSmrg Defer initial drmmode_copy_fb call until root window creation 2445d6c0b56eSmrg 2446d6c0b56eSmrg That's late enough for acceleration to be fully initialized, but still 2447d6c0b56eSmrg early enough to set pScreen->canDoBGNoneRoot. 2448d6c0b56eSmrg 2449d6c0b56eSmrg (Ported from radeon commit 37874a4eeace5df04b02c8fc28f67b824e3f0f5f) 2450d6c0b56eSmrg 2451d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2452d6c0b56eSmrg 2453d6c0b56eSmrgcommit 0fb45f2bba89379ba25d4c863091937b6384bda9 2454d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2455d6c0b56eSmrgDate: Thu Aug 6 17:25:53 2015 +0900 2456d6c0b56eSmrg 2457d6c0b56eSmrg Only copy fbcon BO contents if bgNoneRoot is TRUE 2458d6c0b56eSmrg 2459d6c0b56eSmrg Otherwise, the X server will initialize the screen pixmap contents 2460d6c0b56eSmrg anyway. 2461d6c0b56eSmrg 2462d6c0b56eSmrg (Ported from radeon commit 39c497f3efca5ca08343b884f44c93215dcdef31) 2463d6c0b56eSmrg 2464d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2465d6c0b56eSmrg 2466d6c0b56eSmrgcommit cac553d3b691d26eaad24fbdcba06097b6728a6d 2467d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2468d6c0b56eSmrgDate: Thu Aug 6 17:20:22 2015 +0900 2469d6c0b56eSmrg 2470d6c0b56eSmrg Add .dir-locals.el file with Emacs indentation settings 2471d6c0b56eSmrg 2472d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2473d6c0b56eSmrg 2474d6c0b56eSmrgcommit ea32253541959cc36a40fb0118200a8f493dc98a 2475d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com> 2476d6c0b56eSmrgDate: Wed Jul 15 11:26:28 2015 +0800 2477d6c0b56eSmrg 2478d6c0b56eSmrg Adapt to the interface change of amdgpu_bo_alloc v3 2479d6c0b56eSmrg 2480d6c0b56eSmrg The amdgpu_bo_alloc_result structure is removed from libdrm_amdgpu, 2481d6c0b56eSmrg and the amdgpu_bo_handle is returned directly 2482d6c0b56eSmrg 2483d6c0b56eSmrg v2: remove the va_map/unmap 2484d6c0b56eSmrg v3: simply the code a bit 2485d6c0b56eSmrg 2486d6c0b56eSmrg Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> 2487d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2488d6c0b56eSmrg 2489d6c0b56eSmrgcommit 3010d3259d3bc74263d526e54e02bc169c8d4b4d 2490d6c0b56eSmrgAuthor: Mario Kleiner <mario.kleiner.de@gmail.com> 2491d6c0b56eSmrgDate: Wed Jul 15 09:54:59 2015 +0200 2492d6c0b56eSmrg 2493d6c0b56eSmrg Allow/Fix use of multiple ZaphodHead outputs per x-screen. 2494d6c0b56eSmrg 2495d6c0b56eSmrg Defining multiple ZaphodHead outputs per x-screen in a 2496d6c0b56eSmrg multiple x-screen's per gpu configuration caused all 2497d6c0b56eSmrg outputs except one per x-screen to go dark, because 2498d6c0b56eSmrg there was a fixed mapping x-screen number -> crtc number, 2499d6c0b56eSmrg limiting the number of crtc's per x-screen to one. 2500d6c0b56eSmrg 2501d6c0b56eSmrg On a ZaphodHead's setup, be more clever and assign 2502d6c0b56eSmrg as many crtc's to a given x-screen as there are 2503d6c0b56eSmrg ZaphodHeads defined for that screen, assuming 2504d6c0b56eSmrg there are enough unused crtc's available. 2505d6c0b56eSmrg 2506d6c0b56eSmrg (Ported from radeon commit afab7839fc15722dbaa7203d00fe7f6ce5336b9d) 2507d6c0b56eSmrg 2508d6c0b56eSmrg Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> 2509d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2510d6c0b56eSmrg 2511d6c0b56eSmrgcommit 159c5d460a330cf0a24678f3c6c3e2fbaf23c571 2512d6c0b56eSmrgAuthor: Dave Airlie <airlied@gmail.com> 2513d6c0b56eSmrgDate: Tue Jul 14 17:04:14 2015 +0900 2514d6c0b56eSmrg 2515d6c0b56eSmrg Adopt for new X server dirty tracking APIs. 2516d6c0b56eSmrg 2517d6c0b56eSmrg Signed-off-by: Dave Airlie <airlied@redhat.com> 2518d6c0b56eSmrg 2519d6c0b56eSmrg (Ported from radeon commit b6d871bf299c7d0f106c07ee4d8bd3b2337f53cc) 2520d6c0b56eSmrg 2521d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2522d6c0b56eSmrg 2523d6c0b56eSmrgcommit 7b3212e33cd36fb6f122774df27b56ec4e1a22b8 2524d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2525d6c0b56eSmrgDate: Thu Jul 9 17:57:29 2015 +0900 2526d6c0b56eSmrg 2527d6c0b56eSmrg DRI2: Don't ignore rotated CRTCs in amdgpu_dri2_drawable_crtc 2528d6c0b56eSmrg 2529d6c0b56eSmrg Waiting for vblank interrupts works fine with rotated CRTCs. The only 2530d6c0b56eSmrg case we can't handle with rotation is page flipping, which is handled 2531d6c0b56eSmrg in can_exchange(). 2532d6c0b56eSmrg 2533d6c0b56eSmrg This fixes gnome-shell hanging on rotation, probably because 2534d6c0b56eSmrg amdgpu_dri2_get_msc returned MSC/UST 0 for rotated CRTCs. 2535d6c0b56eSmrg 2536d6c0b56eSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 2537d6c0b56eSmrg 2538d6c0b56eSmrgcommit 5587a7b43d02d6371ed4675a6260427492ebad94 2539d6c0b56eSmrgAuthor: Piotr Redlewski <predlewski@gmail.com> 2540d6c0b56eSmrgDate: Wed Jul 8 20:59:14 2015 +0200 2541d6c0b56eSmrg 2542d6c0b56eSmrg Do not try to enable already enabled CRTCs in DPMS hook 2543d6c0b56eSmrg 2544d6c0b56eSmrg (Ported from radeon commit a8ed62010d5012dfb27773595c446b217f3c00c5) 2545d6c0b56eSmrg 2546d6c0b56eSmrg Signed-off-by: Piotr Redlewski <predlewski@gmail.com> 2547d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2548d6c0b56eSmrg 2549d6c0b56eSmrgcommit b176e63df20b345cb378fe962afd14eed43421d3 2550d6c0b56eSmrgAuthor: Piotr Redlewski <predlewski@gmail.com> 2551d6c0b56eSmrgDate: Sun Jun 28 23:20:22 2015 +0200 2552d6c0b56eSmrg 2553d6c0b56eSmrg Enable/disable CRTCs in DPMS hook 2554d6c0b56eSmrg 2555d6c0b56eSmrg The CRTC DPMS hook hasn't enabled or disabled hardware CRTCs. 2556d6c0b56eSmrg 2557d6c0b56eSmrg (Based on radeon commit 48e5be1d5a82c1e0ccf6b7d52924c92a630e52a8) 2558d6c0b56eSmrg 2559d6c0b56eSmrg Signed-off-by: Piotr Redlewski <predlewski@gmail.com> 2560d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2561d6c0b56eSmrg 2562d6c0b56eSmrgcommit d94d4a609c593b46ab718544ee24c25530732f22 2563d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2564d6c0b56eSmrgDate: Thu Jun 11 17:49:33 2015 +0900 2565d6c0b56eSmrg 2566d6c0b56eSmrg Handle CRTC DPMS from output DPMS hooks 2567d6c0b56eSmrg 2568d6c0b56eSmrg This fixes at least two issues: 2569d6c0b56eSmrg 2570d6c0b56eSmrg The CRTC DPMS hook isn't called after a modeset, so the vertical blank 2571d6c0b56eSmrg interrupt emulation code considered the CRTC disabled after a modeset. As 2572d6c0b56eSmrg a side effect, page flipping was no longer used after a modeset. 2573d6c0b56eSmrg 2574d6c0b56eSmrg This change also makes sure the vertical blank interrupt emulation code 2575d6c0b56eSmrg runs before the hardware CRTC is disabled and after it's enabled from the 2576d6c0b56eSmrg output DPMS hook. The wrong order could cause gnome-shell to hang after 2577d6c0b56eSmrg a suspend/resume and/or DPMS off/on cycle. 2578d6c0b56eSmrg 2579d6c0b56eSmrg (Ported from radeon commit c4ae0e2cbcc0e2ebf9f13ee92d59b5120254a1dc) 2580d6c0b56eSmrg 2581d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2582d6c0b56eSmrg 2583d6c0b56eSmrgcommit c57da33308a81fa575179238a0415abcb8b34908 2584d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2585d6c0b56eSmrgDate: Tue Jun 9 12:39:21 2015 +0900 2586d6c0b56eSmrg 2587d6c0b56eSmrg Add Option "TearFree" 2588d6c0b56eSmrg 2589d6c0b56eSmrg Avoids tearing by flipping between two scanout BOs per (non-rotated) CRTC 2590d6c0b56eSmrg 2591d6c0b56eSmrg (Cherry picked from radeon commit 43159ef400c3b18b9f4d3e6fa1c4aef2d60d38fe) 2592d6c0b56eSmrg 2593d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2594d6c0b56eSmrg 2595d6c0b56eSmrgcommit bd0aca09770543fa77b934e1728a832c9c2dc90c 2596d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2597d6c0b56eSmrgDate: Tue Jun 9 11:57:59 2015 +0900 2598d6c0b56eSmrg 2599d6c0b56eSmrg glamor: Remove the stride member of struct radeon_pixmap 2600d6c0b56eSmrg 2601d6c0b56eSmrg Its value was always the same as that of the PixmapRec devKind member. 2602d6c0b56eSmrg 2603d6c0b56eSmrg (Cherry picked from radeon commit ed401f5b4f07375db17ff05e294907ec95fc946d) 2604d6c0b56eSmrg 2605d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2606d6c0b56eSmrg 2607d6c0b56eSmrgcommit e5dfb6c2667994701ee451bf82c4142cbf343405 2608d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2609d6c0b56eSmrgDate: Wed Mar 18 16:23:24 2015 +0900 2610d6c0b56eSmrg 2611d6c0b56eSmrg glamor: Add Option "ShadowPrimary" 2612d6c0b56eSmrg 2613d6c0b56eSmrg When this option is enabled, most pixmaps (including the screen pixmap) 2614d6c0b56eSmrg are allocated in system RAM and mostly accessed by the CPU. Changed areas 2615d6c0b56eSmrg of the screen pixmap are copied to dedicated per-CRTC scanout pixmaps 2616d6c0b56eSmrg regularly, triggered by the vblank interrupt. 2617d6c0b56eSmrg 2618d6c0b56eSmrg (Cherry picked from radeon commits ae92d1765fa370a8d94c2856ad6c45d273ec3c69 2619d6c0b56eSmrg and 1af044d7eee211fd4b248c236280274a68334da5) 2620d6c0b56eSmrg 2621d6c0b56eSmrg [ Michel Dänzer: Additional adjustements for the amdgpu driver ] 2622d6c0b56eSmrg 2623d6c0b56eSmrg Signed-off-by: Darren Powell <darren.powell@amd.com> 2624d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2625d6c0b56eSmrg 2626d6c0b56eSmrgcommit 08da7b691d556735dcc22b1351c886a5079dfd3f 2627d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2628d6c0b56eSmrgDate: Wed Jun 10 16:21:21 2015 +0900 2629d6c0b56eSmrg 2630d6c0b56eSmrg Add AMDGPU_CREATE_PIXMAP_GTT flag 2631d6c0b56eSmrg 2632d6c0b56eSmrg When set, the pixmap memory is allocated in GTT instead of in VRAM. 2633d6c0b56eSmrg 2634d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2635d6c0b56eSmrg 2636d6c0b56eSmrgcommit 59bdb578266a2637fda8d11168b9332f6845157c 2637d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2638d6c0b56eSmrgDate: Wed Jun 10 12:04:29 2015 +0900 2639d6c0b56eSmrg 2640d6c0b56eSmrg Factor out amdgpu_bo_get_handle helper 2641d6c0b56eSmrg 2642d6c0b56eSmrg The helper transparently handles BOs allocated from GBM and 2643d6c0b56eSmrg libdrm_amdgpu. 2644d6c0b56eSmrg 2645d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2646d6c0b56eSmrg 2647d6c0b56eSmrgcommit 9a6eff506b6804481a6e8139d362355fc5ffdbfb 2648d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2649d6c0b56eSmrgDate: Wed Jun 10 12:10:24 2015 +0900 2650d6c0b56eSmrg 2651d6c0b56eSmrg Set AMDGPU_BO_FLAGS_GBM for cursor buffers allocated from GBM 2652d6c0b56eSmrg 2653d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2654d6c0b56eSmrg 2655d6c0b56eSmrgcommit d3ea8a69b02b308f8f23662be6e0c7bd81c1a2c9 2656d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2657d6c0b56eSmrgDate: Fri May 29 18:53:50 2015 +0900 2658d6c0b56eSmrg 2659d6c0b56eSmrg glamor: Add wrappers for the X server rendering hooks 2660d6c0b56eSmrg 2661d6c0b56eSmrg They can choose between using the GPU or CPU for the operation. 2662d6c0b56eSmrg 2663d6c0b56eSmrg (cherry picked from radeon commits eea79472a84672ee4dc7adc4487cec6a4037048a 2664d6c0b56eSmrg and e58fc380ccf2a581d28f041fd74b963626ca5404) 2665d6c0b56eSmrg 2666d6c0b56eSmrg Signed-off-by: Darren Powell <darren.powell@amd.com> 2667d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2668d6c0b56eSmrg 2669d6c0b56eSmrgcommit 895e4d73d5f042afa13065b64a78f5625ecb5612 2670d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2671d6c0b56eSmrgDate: Fri May 29 18:53:40 2015 +0900 2672d6c0b56eSmrg 2673d6c0b56eSmrg glamor: Remove unused function radeon_glamor_pixmap_is_offscreen 2674d6c0b56eSmrg 2675d6c0b56eSmrg (cherry picked from radeon commit 2fa021f77372ca93375a3d13a0c43a9089674899) 2676d6c0b56eSmrg 2677d6c0b56eSmrg Signed-off-by: Darren Powell <darren.powell@amd.com> 2678d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2679d6c0b56eSmrg 2680d6c0b56eSmrgcommit cc5671c587d575b2a7d2802d17e8af0384a2cea5 2681d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2682d6c0b56eSmrgDate: Fri May 29 18:53:36 2015 +0900 2683d6c0b56eSmrg 2684d6c0b56eSmrg Add RADEON_CREATE_PIXMAP_SCANOUT flag 2685d6c0b56eSmrg 2686d6c0b56eSmrg It means that the pixmap is used for scanout exclusively. 2687d6c0b56eSmrg 2688d6c0b56eSmrg (cherry picked from radeon commit e96349ba6281fd18b8bf9c76629128276b065e6c) 2689d6c0b56eSmrg 2690d6c0b56eSmrg Signed-off-by: Darren Powell <darren.powell@amd.com> 2691d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2692d6c0b56eSmrg 2693d6c0b56eSmrgcommit 21834953ee64920438dee1c94f3a1e53dc58b82d 2694d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2695d6c0b56eSmrgDate: Fri May 29 18:53:32 2015 +0900 2696d6c0b56eSmrg 2697d6c0b56eSmrg Split out struct drmmode_scanout for rotation shadow buffer information 2698d6c0b56eSmrg 2699d6c0b56eSmrg Will be used for other kinds of dedicated scanout buffers as well. 2700d6c0b56eSmrg 2701d6c0b56eSmrg (cherry picked from radeon commit 9be7dd382e86d2b804de81d4e2af7431b2e16843) 2702d6c0b56eSmrg 2703d6c0b56eSmrg Signed-off-by: Darren Powell <darren.powell@amd.com> 2704d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2705d6c0b56eSmrg 2706d6c0b56eSmrgcommit e4e4f7b83e7d7e43993fa0793d666d6dec2980f8 2707d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2708d6c0b56eSmrgDate: Fri May 29 18:53:21 2015 +0900 2709d6c0b56eSmrg 2710d6c0b56eSmrg Rename scanout_pixmap_x field to prime_pixmap_x 2711d6c0b56eSmrg 2712d6c0b56eSmrg To avoid confusion with upcoming changes. 2713d6c0b56eSmrg 2714d6c0b56eSmrg (cherry picked from radeon commit c32b0530302739f6512755bccf281c2300617376) 2715d6c0b56eSmrg 2716d6c0b56eSmrg Signed-off-by: Darren Powell <darren.powell@amd.com> 2717d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2718d6c0b56eSmrg 2719d6c0b56eSmrgcommit edfff6b1a3a19953644b8052b30076f76f7dc337 2720d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2721d6c0b56eSmrgDate: Tue Jun 2 17:04:21 2015 +0900 2722d6c0b56eSmrg 2723d6c0b56eSmrg Add DRI3 support 2724d6c0b56eSmrg 2725d6c0b56eSmrg Must be enabled with 2726d6c0b56eSmrg 2727504d986fSmrg Option "DRI3" 2728d6c0b56eSmrg 2729d6c0b56eSmrg in xorg.conf. 2730d6c0b56eSmrg 2731d6c0b56eSmrg (Cherry picked from radeon commits 64e1e4dbdd3caee6f5d8f6b6c094b4533fa94953, 2732d6c0b56eSmrg 694e04720b886060fe3eefdce59741f218c8269f, 2733d6c0b56eSmrg f940fd741b15f03393037c5bb904cd74f012de9d, 2734d6c0b56eSmrg fcd37f65f485291084c174666bd605e215bf1398, 2735d6c0b56eSmrg 4b0997e56dec0053cb2cb793e0f4ae35055ff7e6, 2736d6c0b56eSmrg f68d9b5ba0c91a725b5eec9386c61bea8824c299 and 2737d6c0b56eSmrg 98fb4199e63fedd4607cddee64bf602d6398df81) 2738d6c0b56eSmrg 2739d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2740d6c0b56eSmrg 2741d6c0b56eSmrgcommit d295b5b3310bc5c23d232c4be4170165a057c090 2742d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2743d6c0b56eSmrgDate: Tue Jun 2 17:01:06 2015 +0900 2744d6c0b56eSmrg 2745d6c0b56eSmrg amdgpu_set_shared_pixmap_backing: Add support for GBM / glamor v2 2746d6c0b56eSmrg 2747d6c0b56eSmrg v2: Initialize reference count of imported GBM BOs to 1, fixes leaking 2748d6c0b56eSmrg them. 2749d6c0b56eSmrg 2750d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> [v1] 2751d6c0b56eSmrg 2752d6c0b56eSmrgcommit 03ad0fa0185d215f7d4234006e04406af1ab63ca 2753d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2754d6c0b56eSmrgDate: Fri May 29 18:53:45 2015 +0900 2755d6c0b56eSmrg 2756d6c0b56eSmrg glamor: Add radeon_pixmap parameter to radeon_glamor_create_textured_pixmap 2757d6c0b56eSmrg 2758d6c0b56eSmrg (cherry picked from radeon commit 051d46382656ffc3e6cac1aab3aee7efdf5b623a) 2759d6c0b56eSmrg 2760d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2761d6c0b56eSmrg Signed-off-by: Darren Powell <darren.powell@amd.com> 2762d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2763d6c0b56eSmrg 2764d6c0b56eSmrgcommit fafb8c6ac925ad16073e5a60dbf60d5add11bb25 2765d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2766d6c0b56eSmrgDate: Tue Jun 2 17:00:46 2015 +0900 2767d6c0b56eSmrg 2768d6c0b56eSmrg Add support for the Present extension 2769d6c0b56eSmrg 2770d6c0b56eSmrg (Cherry picked from radeon commits 3c65fb849e1ba9fb6454bcaa55b696548902f3fc, 2771d6c0b56eSmrg 694e04720b886060fe3eefdce59741f218c8269f, 2772d6c0b56eSmrg e3be8b0a8cf484ff16597413a6172788178e80c8, 2773d6c0b56eSmrg 80eede245d1eda27eaba108b0761a24bfd69aff6 and 2774d6c0b56eSmrg 5f82a720374c9c1caebb42bfbeea1f0cf8847d28) 2775d6c0b56eSmrg 2776d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2777d6c0b56eSmrg 2778d6c0b56eSmrgcommit 5b51f0e7e396ea946ef85429a8e9be5c1d5c39c3 2779d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2780d6c0b56eSmrgDate: Tue Jun 2 16:58:27 2015 +0900 2781d6c0b56eSmrg 2782d6c0b56eSmrg Add support for SYNC extension fences 2783d6c0b56eSmrg 2784d6c0b56eSmrg (Cherry picked from radeon commits 8fc9a241ab59ffbcdc178d6415332c88a54e85fe, 2785d6c0b56eSmrg af1862a37570fa512a525ab47d72b30400d2e2d6, 2786d6c0b56eSmrg aa7825eb29cdf6ac9d7b28ad18186807ff384687, 2787d6c0b56eSmrg af6076241c0d322b295a4e898407ae2472bd8eb4 and 2788d6c0b56eSmrg d64a13ebe0ecd241ee3260dbffd8f4a01e254183) 2789d6c0b56eSmrg 2790d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2791d6c0b56eSmrg 2792d6c0b56eSmrgcommit a30060d22a42688371166a861e5050fdd5ce8f7b 2793d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2794d6c0b56eSmrgDate: Mon Jun 1 18:33:33 2015 +0900 2795d6c0b56eSmrg 2796d6c0b56eSmrg DRI2: Split out helper for getting UST and MSC of a specific CRTC 2797d6c0b56eSmrg 2798d6c0b56eSmrg (Cherry picked from radeon commits 76c2923ac5c7230a8b2f9f8329c308d28b44d9c0 2799d6c0b56eSmrg and d7c82731a8bf3d381bc571b94d80d9bb2dd6e40d) 2800d6c0b56eSmrg 2801d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2802d6c0b56eSmrg 2803d6c0b56eSmrgcommit 9a554a683b970660b467566cf05b921393705a20 2804d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2805d6c0b56eSmrgDate: Mon Jun 1 17:32:56 2015 +0900 2806d6c0b56eSmrg 2807d6c0b56eSmrg DRI2: Use helper functions for DRM event queue management 2808d6c0b56eSmrg 2809d6c0b56eSmrg This is mostly in preparation for Present support, but it also simplifies 2810d6c0b56eSmrg the DRI2 specific code a little. 2811d6c0b56eSmrg 2812d6c0b56eSmrg (Cherry picked from radeon commit 6c3a721cde9317233072b573f9502348dcd21b16) 2813d6c0b56eSmrg 2814d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2815d6c0b56eSmrg 2816d6c0b56eSmrgcommit e6164ad340f65ff8ee6f6a6934302591af875a43 2817d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2818d6c0b56eSmrgDate: Mon Jun 1 17:29:30 2015 +0900 2819d6c0b56eSmrg 2820d6c0b56eSmrg DRI2: Move amdgpu_dri2_flip_event_handler 2821d6c0b56eSmrg 2822d6c0b56eSmrg In preparation for the next change, which will modify it to a static 2823d6c0b56eSmrg function which needs to be in the new place. No functional change. 2824d6c0b56eSmrg 2825d6c0b56eSmrg (Cherry picked from radeon commit c3fa22a479e61d1899fa9d327d9c4e2a7f64b0c1) 2826d6c0b56eSmrg 2827d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2828d6c0b56eSmrg 2829d6c0b56eSmrgcommit 5419e13da7ec3cffd43510ac88106076ea81124c 2830d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2831d6c0b56eSmrgDate: Mon Jun 1 17:25:23 2015 +0900 2832d6c0b56eSmrg 2833d6c0b56eSmrg DRI2: Remove superfluous assignments to *_info->frame 2834d6c0b56eSmrg 2835d6c0b56eSmrg That field is only used for page flipping. 2836d6c0b56eSmrg 2837d6c0b56eSmrg (Cherry picked from radeon commit 65045112fdc8a9fa36e0e00f46739a6152b775ff) 2838d6c0b56eSmrg 2839d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2840d6c0b56eSmrg 2841d6c0b56eSmrgcommit f4c2b640be17ab1f8694b35d4cb74ccfce3d1385 2842d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2843d6c0b56eSmrgDate: Mon Jun 1 17:11:30 2015 +0900 2844d6c0b56eSmrg 2845d6c0b56eSmrg DRI2: Simplify blit fallback handling for scheduled swaps 2846d6c0b56eSmrg 2847d6c0b56eSmrg Also use amdgpu_dri2_schedule_event when possible. 2848d6c0b56eSmrg 2849d6c0b56eSmrg (Cherry picked from radeon commit ad27f16f308079d06a2b1c788b3cb0947531253a) 2850d6c0b56eSmrg 2851d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2852d6c0b56eSmrg 2853d6c0b56eSmrgcommit 13a7284e061081a12180b375d66f9b8394cf8753 2854d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2855d6c0b56eSmrgDate: Mon Jun 1 16:58:00 2015 +0900 2856d6c0b56eSmrg 2857d6c0b56eSmrg Add DRM event queue helpers 2858d6c0b56eSmrg 2859d6c0b56eSmrg (Cherry picked from radeon commit b4af8a327ed8420f0ff4ea0f113f4a59406ed4d3) 2860d6c0b56eSmrg 2861d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2862d6c0b56eSmrg 2863d6c0b56eSmrgcommit eb7c6958dff5cb8b0aad02d1d5673483dae4e3d4 2864d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2865d6c0b56eSmrgDate: Mon Jun 1 16:52:40 2015 +0900 2866d6c0b56eSmrg 2867d6c0b56eSmrg Move xorg_list backwards compatibility to new amdgpu_list.h header 2868d6c0b56eSmrg 2869d6c0b56eSmrg (Cherry picked from radeon commits 7c3470f4b659206ed23f761948936ede3a2dba3d 2870d6c0b56eSmrg and 4a98f60117c387a228d5cbaadb6e298fb4e865df) 2871d6c0b56eSmrg 2872d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2873d6c0b56eSmrg 2874d6c0b56eSmrgcommit 69d161a54b4ea0d8033a0873210f2857c91ceae8 2875d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2876d6c0b56eSmrgDate: Mon Jun 1 16:46:30 2015 +0900 2877d6c0b56eSmrg 2878d6c0b56eSmrg Require at least xserver 1.8 2879d6c0b56eSmrg 2880d6c0b56eSmrg So we can rely on the list.h header. 2881d6c0b56eSmrg 2882d6c0b56eSmrg xserver 1.8 was released in April 2010. 2883d6c0b56eSmrg 2884d6c0b56eSmrg (Cherry picked from radeon commit 7388d0b6c54b9d536fdb161e3aa61b326627b939) 2885d6c0b56eSmrg 2886d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2887d6c0b56eSmrg 2888d6c0b56eSmrgcommit 7363156b7c077def2aaf9a4573410817f5e92610 2889d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com> 2890d6c0b56eSmrgDate: Sat May 30 00:31:44 2015 +0800 2891d6c0b56eSmrg 2892d6c0b56eSmrg Check GBM_BO_USE_LINEAR correctly v2 2893d6c0b56eSmrg 2894d6c0b56eSmrg v2: remove the check for gbm.h 2895d6c0b56eSmrg 2896d6c0b56eSmrg Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> 2897d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2898d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> [v1] 2899d6c0b56eSmrg 2900d6c0b56eSmrgcommit e75e9f39c95b8b563885882bf29d776861cd6ca3 2901d6c0b56eSmrgAuthor: Brian Paterni <bpaterni@gmail.com> 2902d6c0b56eSmrgDate: Sat May 16 15:00:14 2015 -0500 2903d6c0b56eSmrg 2904d6c0b56eSmrg extend conditional group GBM_BO_USE_LINEAR 2905d6c0b56eSmrg over both usages 2906d6c0b56eSmrg 2907d6c0b56eSmrg Fixes 'GBM_BO_USE_LINEAR' undeclared error when compiling against older 2908d6c0b56eSmrg libgbm 2909d6c0b56eSmrg 2910d6c0b56eSmrg Signed-off-by: Brian Paterni <bpaterni@gmail.com> 2911d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2912d6c0b56eSmrg 2913d6c0b56eSmrgcommit 37b389ee9e13f065fb080d1269f9a6aed616c210 2914d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2915d6c0b56eSmrgDate: Fri May 15 10:24:24 2015 +0900 2916d6c0b56eSmrg 2917d6c0b56eSmrg glamor: Deal with glamor_glyphs_init being removed from xserver 2918d6c0b56eSmrg 2919d6c0b56eSmrg Port of radeon commit 818c180c8932233b214a35ba0647af82f7bcec3d. 2920d6c0b56eSmrg 2921d6c0b56eSmrgcommit 22917044e419023d487f816e0d4f094695b55fa6 2922d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com> 2923d6c0b56eSmrgDate: Tue May 12 13:29:00 2015 -0400 2924d6c0b56eSmrg 2925d6c0b56eSmrg add some new tonga pci ids 2926d6c0b56eSmrg 2927d6c0b56eSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 2928d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2929d6c0b56eSmrg Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2930d6c0b56eSmrg 2931d6c0b56eSmrgcommit e71be4a22799ec4c02051b75c5fed16a3a953c7b 2932d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com> 2933d6c0b56eSmrgDate: Tue May 12 13:25:02 2015 -0400 2934d6c0b56eSmrg 2935d6c0b56eSmrg add new bonaire pci id 2936d6c0b56eSmrg 2937d6c0b56eSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 2938d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2939d6c0b56eSmrg Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2940d6c0b56eSmrg 2941d6c0b56eSmrgcommit b795d1e137b34a314b4b41d025d96ca9251d6bbe 2942d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 2943d6c0b56eSmrgDate: Thu May 7 18:05:32 2015 +0900 2944d6c0b56eSmrg 2945d6c0b56eSmrg Link against libgbm 2946d6c0b56eSmrg 2947d6c0b56eSmrg Fixes unresolved symbol "gbm_create_device". 2948d6c0b56eSmrg 2949d6c0b56eSmrg Reported-and-Tested-by: Brian Paterni <bpaterni@gmail.com> 2950d6c0b56eSmrg 2951d6c0b56eSmrgcommit 7e3b27390a03e423772717fca3c757cf5cc4d7b4 2952d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com> 2953d6c0b56eSmrgDate: Tue May 12 05:34:49 2015 +0800 2954d6c0b56eSmrg 2955d6c0b56eSmrg Disable tiling for PRIME shared pixmap 2956d6c0b56eSmrg 2957d6c0b56eSmrg Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> 2958d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2959d6c0b56eSmrg 2960d6c0b56eSmrgcommit 4840f918ab7d61b4f55bcdff3afdac7b34e45d88 2961d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com> 2962d6c0b56eSmrgDate: Tue May 12 00:09:42 2015 +0800 2963d6c0b56eSmrg 2964d6c0b56eSmrg Use gbm_bo_get_fd to get DMA_BUF fd 2965d6c0b56eSmrg 2966d6c0b56eSmrg When GBM is used for buffer allocation, gbm_bo_get_fd should be 2967d6c0b56eSmrg used to get the DMA_BUF fd. 2968d6c0b56eSmrg 2969d6c0b56eSmrg Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> 2970d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 2971d6c0b56eSmrg 2972d6c0b56eSmrgcommit b69c5b3cc2d7da3bb85acd687db9b5a021258914 2973d6c0b56eSmrgAuthor: Marek Olšák <marek.olsak@amd.com> 2974d6c0b56eSmrgDate: Fri Mar 27 22:56:37 2015 +0100 2975d6c0b56eSmrg 2976d6c0b56eSmrg ddx: use amdgpu_query_crtc_from_id 2977d6c0b56eSmrg 2978d6c0b56eSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 2979d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2980d6c0b56eSmrg 2981d6c0b56eSmrgcommit 91aa694a7da7b690a3e5d59a1a8fa42cbb3ebda4 2982d6c0b56eSmrgAuthor: Marek Olšák <marek.olsak@amd.com> 2983d6c0b56eSmrgDate: Fri Mar 27 22:22:35 2015 +0100 2984d6c0b56eSmrg 2985d6c0b56eSmrg ddx: remove AMDGPUIsAccelWorking 2986d6c0b56eSmrg 2987d6c0b56eSmrg libdrm fails to initialize without acceleration, so this always returns true. 2988d6c0b56eSmrg 2989d6c0b56eSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 2990d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 2991d6c0b56eSmrg 2992d6c0b56eSmrgcommit afc33040f862e2e13ba7f132bb363cf16fb6a1d7 2993d6c0b56eSmrgAuthor: Marek Olšák <marek.olsak@amd.com> 2994d6c0b56eSmrgDate: Fri Mar 27 22:14:37 2015 +0100 2995d6c0b56eSmrg 2996d6c0b56eSmrg ddx: enable acceleration by default on Hawaii 2997d6c0b56eSmrg 2998d6c0b56eSmrg Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> 2999d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 3000d6c0b56eSmrg 3001d6c0b56eSmrgcommit 8a34a8149860ac15e83ccdbd8d9a527d8d3e5997 3002d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com> 3003d6c0b56eSmrgDate: Mon Apr 27 14:27:34 2015 +0800 3004d6c0b56eSmrg 3005d6c0b56eSmrg Remove throttling from amdgpu_dri2_copy_region2 3006d6c0b56eSmrg 3007d6c0b56eSmrg Throttling should be handled by the client-side drivers. 3008d6c0b56eSmrg 3009d6c0b56eSmrg Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> 3010d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 3011d6c0b56eSmrg 3012d6c0b56eSmrgcommit 9f61a5506b1028d30c99cb5866abcec35d5c9cb8 3013d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com> 3014d6c0b56eSmrgDate: Fri Apr 24 11:47:32 2015 -0400 3015d6c0b56eSmrg 3016d6c0b56eSmrg fixup README 3017d6c0b56eSmrg 3018d6c0b56eSmrg Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> 3019d6c0b56eSmrg Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 3020d6c0b56eSmrg 3021d6c0b56eSmrgcommit a49ad11af18dad74506c2f69d7bbda07b67529d2 3022d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 3023d6c0b56eSmrgDate: Fri Apr 24 09:57:27 2015 +0900 3024d6c0b56eSmrg 3025d6c0b56eSmrg Add 10-amdgpu.conf xorg.conf.d snippet 3026d6c0b56eSmrg 3027d6c0b56eSmrg This instructs Xorg >= 1.16 to try loading the amdgpu driver for devices 3028d6c0b56eSmrg managed by the amdgpu kernel driver. 3029d6c0b56eSmrg 3030d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 3031d6c0b56eSmrg 3032d6c0b56eSmrgcommit fa4aed6cf56048a6520eac57514e38db3685cd15 3033d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 3034d6c0b56eSmrgDate: Fri Apr 24 09:53:33 2015 +0900 3035d6c0b56eSmrg 3036d6c0b56eSmrg Document Option "AccelMethod" in the manpage 3037d6c0b56eSmrg 3038d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 3039d6c0b56eSmrg 3040d6c0b56eSmrgcommit fe4a4b6836252cc8caa642a32fb3910c8590076b 3041d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 3042d6c0b56eSmrgDate: Fri Apr 24 09:52:04 2015 +0900 3043d6c0b56eSmrg 3044d6c0b56eSmrg Fix build when gbm.h doesn't define GBM_BO_USE_LINEAR 3045d6c0b56eSmrg 3046d6c0b56eSmrg Option "AccelMethod" "none" is ignored in that case. 3047d6c0b56eSmrg 3048d6c0b56eSmrg Reviewed-by: Alex Deucher <alexander.deucher@amd.com> 3049d6c0b56eSmrg 3050d6c0b56eSmrgcommit 84df3e7114fb71b5e10c1a6f7869ab1505fef5b0 3051d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 3052d6c0b56eSmrgDate: Fri Apr 24 09:51:22 2015 +0900 3053d6c0b56eSmrg 3054d6c0b56eSmrg glamor: Handle GLAMOR_* flags removed from xserver 3055d6c0b56eSmrg 3056d6c0b56eSmrg The behaviour is the same as when the removed flags were passed in. 3057d6c0b56eSmrg 3058d6c0b56eSmrg (cherry picked from radeon commit b16609b453bb1a181198cf27778f205dc23fb642) 3059d6c0b56eSmrg 3060d6c0b56eSmrg Reviewed-by: Christian König <christian.koenig@amd.com> 3061d6c0b56eSmrg 3062d6c0b56eSmrgcommit b947f4bf4efa8841bea4d306d0b0d21c7511c724 3063d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com> 3064d6c0b56eSmrgDate: Fri Apr 24 09:50:51 2015 +0900 3065d6c0b56eSmrg 3066d6c0b56eSmrg Move #include "radeon_glamor.h" from amdgpu_drv.h to where it's needed 3067d6c0b56eSmrg 3068d6c0b56eSmrg (cherry picked from radeon commit 4b8adebb80158bcf81ada83bb88517febe931b12) 3069d6c0b56eSmrg 3070d6c0b56eSmrg Reviewed-by: Christian König <christian.koenig@amd.com> 3071d6c0b56eSmrg 3072d6c0b56eSmrgcommit ff62bf6e9dce55dbde92baf4fa30193c7344ee8a 3073d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com> 3074d6c0b56eSmrgDate: Mon Apr 20 11:57:52 2015 -0400 3075d6c0b56eSmrg 3076d6c0b56eSmrg amdgpu: add the xf86-video-amdgpu driver 3077d6c0b56eSmrg 3078d6c0b56eSmrg This adds the new xf86-video-amdgpu driver for 3079d6c0b56eSmrg newer AMD GPUs. 3080d6c0b56eSmrg 3081 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 3082