ChangeLog revision 77d6d1ec
177d6d1ecSmrgcommit b467d2569a003da05ad222b0dc095bee5eec450a
277d6d1ecSmrgAuthor: Michel Dänzer <mdaenzer@redhat.com>
377d6d1ecSmrgDate:   Fri Oct 11 17:10:10 2019 +0200
477d6d1ecSmrg
577d6d1ecSmrg    Bump version for the 19.1.0 release
677d6d1ecSmrg
777d6d1ecSmrgcommit a1b7263277c033e109629829c370c0e95978e061
877d6d1ecSmrgAuthor: Michel Dänzer <mdaenzer@redhat.com>
977d6d1ecSmrgDate:   Thu Sep 26 15:56:59 2019 +0200
1077d6d1ecSmrg
1177d6d1ecSmrg    Don't unreference FBs of pixmaps from different screens in LeaveVT
1277d6d1ecSmrg    
1377d6d1ecSmrg    FindClientResourcesByType finds pixmaps from all screens, but trying to
1477d6d1ecSmrg    process ones from other screens here makes no sense and likely results
1577d6d1ecSmrg    in a crash or memory corruption.
1677d6d1ecSmrg    
1777d6d1ecSmrg    Fixes: c16ff42f927d ("Make all active CRTCs scan out an all-black
1877d6d1ecSmrg                          framebuffer in LeaveVT")
1977d6d1ecSmrg    (Ported from radeon commit 2faaecc69b127248718e759c6c98c84d56dd1b6b)
2077d6d1ecSmrg
2177d6d1ecSmrgcommit 5b8bc9fc505c551dcd9b0ed5ab835a49fa4f9fda
2277d6d1ecSmrgAuthor: Michel Dänzer <mdaenzer@redhat.com>
2377d6d1ecSmrgDate:   Wed Sep 18 12:55:45 2019 +0200
2477d6d1ecSmrg
2577d6d1ecSmrg    Don't set up black scanout buffer if LeaveVT is called from CloseScreen
2677d6d1ecSmrg    
2777d6d1ecSmrg    Avoids a crash described in
2877d6d1ecSmrg    https://gitlab.freedesktop.org/xorg/driver/xf86-video-amdgpu/merge_requests/43#note_223718
2977d6d1ecSmrg    
3077d6d1ecSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3177d6d1ecSmrg
3277d6d1ecSmrgcommit e6fce59a071220967fcd4e2c9e4a262c72870761
3377d6d1ecSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3477d6d1ecSmrgDate:   Wed Jul 24 16:05:05 2019 +0200
3577d6d1ecSmrg
3677d6d1ecSmrg    present: Don't check pixmap pitch in check_flip with non-DC >= 3.34
3777d6d1ecSmrg    
3877d6d1ecSmrg    The current non-DC kernel driver also handles flipping between different
3977d6d1ecSmrg    pitches correctly.
4077d6d1ecSmrg    
4177d6d1ecSmrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
4277d6d1ecSmrg
4377d6d1ecSmrgcommit 5bb2580b266468f87843b5585ae64e056b63bb88
4477d6d1ecSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4577d6d1ecSmrgDate:   Wed Jul 24 15:55:19 2019 +0200
4677d6d1ecSmrg
4777d6d1ecSmrg    present: Don't check pixmap pitch in check_flip with current DC
4877d6d1ecSmrg    
4977d6d1ecSmrg    Current DC handles flipping between different pitches correctly.
5077d6d1ecSmrg    
5177d6d1ecSmrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
5277d6d1ecSmrg
5377d6d1ecSmrgcommit ac66086613cbd0974b421cd5eda872adc15242ed
5477d6d1ecSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5577d6d1ecSmrgDate:   Wed Jul 24 15:45:21 2019 +0200
5677d6d1ecSmrg
5777d6d1ecSmrg    present: Also check pixmap pitch in check_flip with current xserver
5877d6d1ecSmrg    
5977d6d1ecSmrg    The corresponding check in the xserver Present code was removed again,
6077d6d1ecSmrg    because flipping between different pitches can work in some cases.
6177d6d1ecSmrg    
6277d6d1ecSmrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
6377d6d1ecSmrg
6477d6d1ecSmrgcommit 98f172eb2d2353e19edd8167f22215ce596811f8
6577d6d1ecSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6677d6d1ecSmrgDate:   Mon Jul 29 18:54:24 2019 +0200
6777d6d1ecSmrg
6877d6d1ecSmrg    gitlab-ci: Use templates from wayland/ci-templates
6977d6d1ecSmrg    
7077d6d1ecSmrg    These are already used by xserver, Mesa and some other projects.
7177d6d1ecSmrg    
7277d6d1ecSmrg    Current Debian testing brings e.g. GCC 8.3.0 and clang 7.0.1.
7377d6d1ecSmrg
7477d6d1ecSmrgcommit 87f41ace4920fd2069794211683659eb25b025a6
7577d6d1ecSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
7677d6d1ecSmrgDate:   Fri Jul 5 12:43:53 2019 +0200
7777d6d1ecSmrg
7877d6d1ecSmrg    Don't disable page flipping completely with SW cursor
7977d6d1ecSmrg    
8077d6d1ecSmrg    Even with SW cursor, page flipping can be used while no X cursor is
8177d6d1ecSmrg    visible.
8277d6d1ecSmrg    
8377d6d1ecSmrg    Occurred to me in the context of xorg/xserver#828.
8477d6d1ecSmrg
8577d6d1ecSmrgcommit 7d3fef72e0c871e1677e9e544f4cae5e238b5c52
8677d6d1ecSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
8777d6d1ecSmrgDate:   Thu May 9 17:39:49 2019 +0200
8877d6d1ecSmrg
8977d6d1ecSmrg    present: Check that we can get a KMS FB for flipping
9077d6d1ecSmrg    
9177d6d1ecSmrg    This can legitimately fail if the pixmap's storage is shared from
9277d6d1ecSmrg    another device, e.g. when using PRIME render offloading.
9377d6d1ecSmrg
9477d6d1ecSmrgcommit ea19a5207054bb159fc7fb6d88e0ceb10c3da010
9577d6d1ecSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
9677d6d1ecSmrgDate:   Thu Jun 6 11:02:15 2019 +0200
9777d6d1ecSmrg
9877d6d1ecSmrg    Remove dri2_drawable_crtc parameter consider_disabled
9977d6d1ecSmrg    
10077d6d1ecSmrg    All callers were passing TRUE.
10177d6d1ecSmrg    
10277d6d1ecSmrg    Reviewed-and-tested-by: Flora Cui <flora.cui@amd.com>
10377d6d1ecSmrg
10477d6d1ecSmrgcommit 3109f088fdbd89c2ee8078625d4f073852492656
10577d6d1ecSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
10677d6d1ecSmrgDate:   Thu Jun 6 11:22:09 2019 +0200
10777d6d1ecSmrg
10877d6d1ecSmrg    dri2: Re-use previous CRTC when possible if pick_best_crtc returns NULL
10977d6d1ecSmrg    
11077d6d1ecSmrg    This way, the MSC will continue ticking at the rate of (the last mode
11177d6d1ecSmrg    which was enabled for) that CRTC, instead of the client running
11277d6d1ecSmrg    unthrottled.
11377d6d1ecSmrg    
11477d6d1ecSmrg    Reviewed-and-tested-by: Flora Cui <flora.cui@amd.com>
11577d6d1ecSmrg
11677d6d1ecSmrgcommit fb06fb814700a47464abd756e1111dcc76d0d776
11777d6d1ecSmrgAuthor: Flora Cui <flora.cui@amd.com>
11877d6d1ecSmrgDate:   Wed May 29 14:18:50 2019 +0800
11977d6d1ecSmrg
12077d6d1ecSmrg    dri2: reply to client for WaitMSC request in any case
12177d6d1ecSmrg    
12277d6d1ecSmrg    otherwise client would wait for reply forever and desktop appears hang.
12377d6d1ecSmrg    
12477d6d1ecSmrg    Signed-off-by: Flora Cui <flora.cui@amd.com>
12577d6d1ecSmrg    Acked-by: Feifei Xu <Feifei.Xu@amd.com>
12677d6d1ecSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
12777d6d1ecSmrg
12877d6d1ecSmrgcommit 4b17533fcb30842caf0035ba593b7d986520cc85
12977d6d1ecSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
13077d6d1ecSmrgDate:   Tue Apr 30 17:50:15 2019 +0200
13177d6d1ecSmrg
13277d6d1ecSmrg    dri3: Always flush glamor before sharing pixmap storage with clients
13377d6d1ecSmrg    
13477d6d1ecSmrg    Even if glamor_gbm_bo_from_pixmap / glamor_fd_from_pixmap themselves
13577d6d1ecSmrg    don't trigger any drawing, there could already be unflushed drawing to
13677d6d1ecSmrg    the pixmap whose storage we share with a client.
13777d6d1ecSmrg
13877d6d1ecSmrgcommit bf61e6d7ac1a5754b1026d7f80acf25ef622c491
13977d6d1ecSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
14077d6d1ecSmrgDate:   Thu Apr 18 19:21:40 2019 +0200
14177d6d1ecSmrg
14277d6d1ecSmrg    Retry get_fb_ptr in get_fb
14377d6d1ecSmrg    
14477d6d1ecSmrg    If get_fb_ptr returns NULL, try again after pixmap_get_handle, it should
14577d6d1ecSmrg    work then.
14677d6d1ecSmrg    
14777d6d1ecSmrg    Fixes spurious Present page flipping failures using "normal" pixmaps
14877d6d1ecSmrg    which aren't shared with direct rendering clients, e.g. with a
14977d6d1ecSmrg    compositor using the RENDER extension.
15077d6d1ecSmrg    
15177d6d1ecSmrg    Bugzilla: https://bugs.freedesktop.org/110417
15277d6d1ecSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
15377d6d1ecSmrg
154852bcc3bSmrgcommit bd4ffd4ebbdf1c43ab9e1ef9ba8b812fd2dde4a4
155852bcc3bSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
156852bcc3bSmrgDate:   Tue Mar 19 18:44:31 2019 +0100
157852bcc3bSmrg
158852bcc3bSmrg    Bump version for the 19.0.1 release
159852bcc3bSmrg
160852bcc3bSmrgcommit 6ee857726166f495abcd68e4ff60e3a09593d079
161852bcc3bSmrgAuthor: Dave Airlie <airlied@redhat.com>
162852bcc3bSmrgDate:   Mon Mar 23 11:33:23 2015 +1000
163852bcc3bSmrg
164852bcc3bSmrg    modesetting: add tile property support
165852bcc3bSmrg    
166852bcc3bSmrg    This adds tiling support to the driver, it retrieves the tile info from
167852bcc3bSmrg    the kernel and translates it into the server format and exposes the
168852bcc3bSmrg    property.
169852bcc3bSmrg    
170852bcc3bSmrg    (Ported from xserver commits 8fb8bbb3062f1a06621ab7030a9e89d5e8367b35
171852bcc3bSmrg     and 6abdb54a11dac4e8854ff94ecdcb90a14321ab31)
172852bcc3bSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
173852bcc3bSmrg
17490f2b693Smrgcommit 9534bf3bb33d14cd3a5af08e36ef42b309647fc7
17590f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
17690f2b693SmrgDate:   Wed Mar 6 12:05:14 2019 +0100
17790f2b693Smrg
17890f2b693Smrg    Bump version for the 19.0.0 release
17990f2b693Smrg
18090f2b693Smrgcommit a2b32e72fdaff3007a79b84929997d8176c2d512
18190f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
18290f2b693SmrgDate:   Fri Mar 1 17:42:08 2019 +0100
18390f2b693Smrg
18490f2b693Smrg    present: Don't check tiling parameters with DC & DRM minor version >= 31
18590f2b693Smrg    
18690f2b693Smrg    Current DC handles any changes of tiling parameters for flips.
18790f2b693Smrg    
18890f2b693Smrg    v2:
18990f2b693Smrg    * Just check all tiling bits if DRM minor < 31 or DC is disabled.
19090f2b693Smrg    
19190f2b693Smrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
19290f2b693Smrg
19390f2b693Smrgcommit 2798244be78df3ef3a7841597577506bfbe50156
19490f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
19590f2b693SmrgDate:   Fri Mar 1 17:47:24 2019 +0100
19690f2b693Smrg
19790f2b693Smrg    Make drmmode_cm_enabled an inline function
19890f2b693Smrg    
19990f2b693Smrg    So that it can be used outside of drmmode_display.c as well.
20090f2b693Smrg    
20190f2b693Smrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
20290f2b693Smrg
20390f2b693Smrgcommit 72653455e4f652ca6c7c290c7f1e8a889b77f5ce
20490f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
20590f2b693SmrgDate:   Fri Mar 1 17:35:48 2019 +0100
20690f2b693Smrg
20790f2b693Smrg    Revert "Remove set but unused amdgpu_dri2::pKernelDRMVersion"
20890f2b693Smrg    
20990f2b693Smrg    This reverts commit 720a61000aeb139005bd8125908cec66a6e69554.
21090f2b693Smrg    
21190f2b693Smrg    We're going to make use of it now.
21290f2b693Smrg    
21390f2b693Smrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
21490f2b693Smrg
21590f2b693Smrgcommit 28cd209ebf20561e65d14fa2e8bbfaedf6965948
21690f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
21790f2b693SmrgDate:   Wed Feb 27 17:35:26 2019 +0100
21890f2b693Smrg
21990f2b693Smrg    Revert "gitlab-ci: Only run docker-image stage if relevant source files change"
22090f2b693Smrg    
22190f2b693Smrg    This reverts commit 9c23076b9e81c36ac2408c491f9b2d546829ee8e.
22290f2b693Smrg    
22390f2b693Smrg    Some scenarios have come to light where this failed to ensure the docker
22490f2b693Smrg    image exists:
22590f2b693Smrg    
22690f2b693Smrg    * If the master branch of a forked repository is used for an MR which
22790f2b693Smrg      doesn't modify .gitlab-ci.yml, the docker-image job may not run.
22890f2b693Smrg    * If the docker-image job of the first pipeline in a forked repository
22990f2b693Smrg      is cancelled or fails for any reason, and .gitlab-ci.yml isn't
23090f2b693Smrg      modified for the next pipeline run.
23190f2b693Smrg
23290f2b693Smrgcommit 09be74a3d1dd9604336d9a27f98d132b262dcbaf
23390f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
23490f2b693SmrgDate:   Thu Feb 28 17:31:55 2019 +0100
23590f2b693Smrg
23690f2b693Smrg    dri2: Call drm_queue_handle_deferred in dri2_deferred_event
23790f2b693Smrg    
23890f2b693Smrg    drm_queue_handler just puts the event on the signalled list; without
23990f2b693Smrg    calling drm_queue_handle_deferred, actual processing of the event may be
24090f2b693Smrg    delayed indefinitely, e.g. until another event arrives from the kernel.
24190f2b693Smrg    
24290f2b693Smrg    This could result in DRI2 clients hanging during DPMS off.
24390f2b693Smrg    
24490f2b693Smrg    Fixes: 739181c8d3334 "Add amdgpu_drm_handle_event wrapper for
24590f2b693Smrg                          drmHandleEvent"
24690f2b693Smrg    Reviewed-by: Aaron Liu <aaron.liu@amd.com>
24790f2b693Smrg    Tested-by: Aaron Liu <aaron.liu@amd.com>
24890f2b693Smrg
24990f2b693Smrgcommit a636f42b496b0604ca00a144690ece61d1a88a27
25090f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
25190f2b693SmrgDate:   Wed Feb 27 18:43:27 2019 +0100
25290f2b693Smrg
25390f2b693Smrg    present: Check that flip and screen pixmap pitches match
25490f2b693Smrg    
25590f2b693Smrg    If they don't, flipping will result in corrupted display.
25690f2b693Smrg    
25790f2b693Smrg    Test case:
25890f2b693Smrg    
25990f2b693Smrg    * Run Xorg at 1920x1080 with no window manager
26090f2b693Smrg    * glxgears -geometry 2048x1080
26190f2b693Smrg    
26290f2b693Smrg    The Present extension code in xserver 1.21 will check for this.
26390f2b693Smrg    
26490f2b693Smrg    Tested-by: Jax Lin <jax.lin@amd.com>
26590f2b693Smrg
26690f2b693Smrgcommit bd090f389f19f1f4a3f662ffdd891345a3899539
26790f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
26890f2b693SmrgDate:   Tue Feb 12 17:57:17 2019 +0100
26990f2b693Smrg
27090f2b693Smrg    Call amdgpu_present_set_screen_vrr from amdgpu_vrr_property_update
27190f2b693Smrg    
27290f2b693Smrg    If the window is currently flipping.
27390f2b693Smrg    
27490f2b693Smrg    This might make a difference when the property gets disabled: Variable
27590f2b693Smrg    refresh will now be disabled immediately in that case, instead of only
27690f2b693Smrg    when the window can no longer use page flipping at all.
27790f2b693Smrg    
27890f2b693Smrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
27990f2b693Smrg
28090f2b693Smrgcommit d9be5d712d469595e1e610f7294bc670ca3b1985
28190f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
28290f2b693SmrgDate:   Tue Feb 12 12:26:25 2019 +0100
28390f2b693Smrg
28490f2b693Smrg    Make use of property request wrappers for VRR property
28590f2b693Smrg    
28690f2b693Smrg    Instead of scanning for PropertyNotify events. Reasons:
28790f2b693Smrg    
28890f2b693Smrg    * Works even if no client listens to PropertyNotify events for the
28990f2b693Smrg      window.
29090f2b693Smrg    * No overhead on delivery of unrelated events, and no overhead at all
29190f2b693Smrg      if Option "VariableRefresh" is disabled.
29290f2b693Smrg    
29390f2b693Smrg    v2:
29490f2b693Smrg    * Use shorter variable name amdgpu_vrr_atom.
29590f2b693Smrg    * Call MakeAtom regardless of info->instance_id, for robustness vs VRR
29690f2b693Smrg      being enabled in some but not all AMDGPU screens.
29790f2b693Smrg    
29890f2b693Smrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
29990f2b693Smrg
30090f2b693Smrgcommit ef8fbe33b7d97f7fb5518db9c0e4d2dcbf2fab6f
30190f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
30290f2b693SmrgDate:   Thu Jan 17 18:41:11 2019 +0100
30390f2b693Smrg
30490f2b693Smrg    Wrap change/delete window property request handlers
30590f2b693Smrg    
30690f2b693Smrg    Preparation for the following change.
30790f2b693Smrg    
30890f2b693Smrg    v2:
30990f2b693Smrg    * Add comments explaining what the wrappers are wrapping.
31090f2b693Smrg    * Use global amdgpu_property_vectors_wrapped to keep track of whether
31190f2b693Smrg      the vectors need to be (un)wrapped, for robustness against VRR being
31290f2b693Smrg      enabled in some but not all AMDGPU screens.
31390f2b693Smrg    
31490f2b693Smrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
31590f2b693Smrg
31690f2b693Smrgcommit 09a45ff8fe3ac07bafa3a0822b1598c41f9ca200
31790f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
31890f2b693SmrgDate:   Tue Feb 12 13:01:04 2019 +0100
31990f2b693Smrg
32090f2b693Smrg    Don't enable the VRR support code for GPU screens
32190f2b693Smrg    
32290f2b693Smrg    Windows aren't associated with GPU screens, and amdgpu_present_flip is
32390f2b693Smrg    never called for them, so VRR can never actually be enabled for them.
32490f2b693Smrg    
32590f2b693Smrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
32690f2b693Smrg
32790f2b693Smrgcommit 2a3d00dc7ed2b4fca698e2d699e1b94da6d0ddb8
32890f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
32990f2b693SmrgDate:   Tue Feb 12 18:12:23 2019 +0100
33090f2b693Smrg
33190f2b693Smrg    Don't register a window private if VRR is disabled
33290f2b693Smrg    
33390f2b693Smrg    It's not used in that case.
33490f2b693Smrg    
33590f2b693Smrg    Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
33690f2b693Smrg
33790f2b693Smrgcommit 5f91be77e059d0c4a4268ec10cbd9aa1052f53eb
33890f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
33990f2b693SmrgDate:   Mon Feb 11 18:32:07 2019 +0100
34090f2b693Smrg
34190f2b693Smrg    gitlab-ci: Don't rely on $CI_PROJECT_NAME
34290f2b693Smrg    
34390f2b693Smrg    The name of a forked repository can be changed later, in which case this
34490f2b693Smrg    would fail to refer to the main repository.
34590f2b693Smrg    
34690f2b693Smrg    Pointed out by Eric Engestrom in
34790f2b693Smrg    https://gitlab.freedesktop.org/mesa/mesa/merge_requests/224 .
34890f2b693Smrg
34990f2b693Smrgcommit 9c23076b9e81c36ac2408c491f9b2d546829ee8e
35090f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
35190f2b693SmrgDate:   Thu Feb 7 17:35:13 2019 +0100
35290f2b693Smrg
35390f2b693Smrg    gitlab-ci: Only run docker-image stage if relevant source files change
35490f2b693Smrg    
35590f2b693Smrg    Otherwise there's normally no need to run it. It will also run when a
35690f2b693Smrg    new branch is created, which ensures that the docker image always exists
35790f2b693Smrg    (e.g. in a newly forked repository).
35890f2b693Smrg    
35990f2b693Smrg    Inspired by https://gitlab.freedesktop.org/mesa/mesa/merge_requests/143
36090f2b693Smrg
36190f2b693Smrgcommit 9045fb310f88780e250e60b80431ca153330e61b
36290f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
36390f2b693SmrgDate:   Thu Jan 24 18:31:40 2019 +0100
36490f2b693Smrg
36590f2b693Smrg    Keep waiting for a pending flip if drm_handle_event returns 0
36690f2b693Smrg    
36790f2b693Smrg    drm_wait_pending_flip stopped waiting if drm_handle_event returned 0,
36890f2b693Smrg    but that might have processed only some unrelated DRM events. As long as
36990f2b693Smrg    the flip is pending, we have to keep waiting for its completion event.
37090f2b693Smrg    
37190f2b693Smrg    Noticed while working on the previous fix.
37290f2b693Smrg    
37390f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
37490f2b693Smrg
37590f2b693Smrgcommit 3ff2cc225f6bc08364ee007fa54e9d0150adaf11
37690f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
37790f2b693SmrgDate:   Tue Jan 22 18:36:56 2019 +0100
37890f2b693Smrg
37990f2b693Smrg    Call drmHandleEvent again if it was interrupted by a signal
38090f2b693Smrg    
38190f2b693Smrg    drmHandleEvent can be interrupted by a signal in read(), in which case
38290f2b693Smrg    it doesn't process any events but returns -1, which
38390f2b693Smrg    drm_handle_event propagated to its callers. This could cause the
38490f2b693Smrg    following failure cascade:
38590f2b693Smrg    
38690f2b693Smrg    1. drm_wait_pending_flip stopped waiting for a pending flip.
38790f2b693Smrg    2. Its caller cleared drmmode_crtc->flip_pending before the flip
38890f2b693Smrg       completed.
38990f2b693Smrg    3. Another flip was attempted but got an unexpected EBUSY error because
39090f2b693Smrg       the previous flip was still pending.
39190f2b693Smrg    4. TearFree was disabled due to the error.
39290f2b693Smrg    
39390f2b693Smrg    The solution is to call drmHandleEvent if it was interrupted by a
39490f2b693Smrg    signal. We can do that in drm_handle_event, because when that is called,
39590f2b693Smrg    either it is known that there are events ready to be processed, or the
39690f2b693Smrg    caller has to wait for events to arrive anyway.
39790f2b693Smrg    
39890f2b693Smrg    v2:
39990f2b693Smrg    * Use ErrorF instead of xf86DrvMsg with hard-coded screen 0.
40090f2b693Smrg    
40190f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/109364
40290f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com> # v1
40390f2b693Smrg
40490f2b693Smrgcommit e72a02ba1d35743fefd939458b9d8cddce86e7f5
40590f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
40690f2b693SmrgDate:   Wed Jan 16 10:26:59 2019 +0100
40790f2b693Smrg
40890f2b693Smrg    Only update drmmode_crtc->flip_pending after actually submitting a flip
40990f2b693Smrg    
41090f2b693Smrg    And only clear it if it matches the framebuffer of the completed flip
41190f2b693Smrg    being processed.
41290f2b693Smrg    
41390f2b693Smrg    Fixes
41490f2b693Smrg    
41590f2b693Smrg     (WW) AMDGPU(0): flip queue failed: Device or resource busy
41690f2b693Smrg     (WW) AMDGPU(0): Page flip failed: Device or resource busy
41790f2b693Smrg     (EE) AMDGPU(0): present flip failed
41890f2b693Smrg    
41990f2b693Smrg    due to clobbering drmmode_crtc->flip_pending.
42090f2b693Smrg    
42190f2b693Smrg    Reproducer: Enable TearFree, run warzone2100 fullscreen, toggle
42290f2b693Smrg    Vertical sync on/off under Video Options. Discovered while investigating
42390f2b693Smrg    https://bugs.freedesktop.org/109364 .
42490f2b693Smrg    
42590f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
42690f2b693Smrg
42790f2b693Smrgcommit a1b479c7d0066c481af920f297d6af9009dda11e
42890f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
42990f2b693SmrgDate:   Tue Jan 15 17:55:27 2019 +0100
43090f2b693Smrg
43190f2b693Smrg    Don't allow TearFree scanout flips to complete in the same vblank period
43290f2b693Smrg    
43390f2b693Smrg    We were using a relative target of 0, meaning "complete the flip ASAP".
43490f2b693Smrg    This could result in the flip sometimes, but not always completing in
43590f2b693Smrg    the same vertical blank period where the corresponding drawing occurred,
43690f2b693Smrg    potentially causing judder artifacts with applications updating their
43790f2b693Smrg    window contents synchronized to the display refresh. A good way to test
43890f2b693Smrg    this is the vsynctester.com site in a windowed browser, where the judder
43990f2b693Smrg    results in the large "VSYNC" text intermittently appearing red or cyan
44090f2b693Smrg    instead of the expected gray.
44190f2b693Smrg    
44290f2b693Smrg    To avoid this, use a relative target MSC of 1, meaning that if a
44390f2b693Smrg    vertical blank period is in progress, the flip will only complete in the
44490f2b693Smrg    next one.
44590f2b693Smrg    
44690f2b693Smrg    Reported by Julian Tempel and Brandon Wright in
44790f2b693Smrg    https://bugs.freedesktop.org/106175 .
44890f2b693Smrg    
44990f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
45090f2b693Smrg
45190f2b693Smrgcommit bf326f2ea19daa6c8da23d6788ff301ae70b8e69
45290f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
45390f2b693SmrgDate:   Thu Jan 10 18:33:04 2019 +0100
45490f2b693Smrg
45590f2b693Smrg    glamor: Avoid glamor_create_pixmap for pixmaps backing windows
45690f2b693Smrg    
45790f2b693Smrg    If the compositing manager uses direct rendering (as is usually the case
45890f2b693Smrg    these days), the storage of a pixmap allocated by glamor_create_pixmap
45990f2b693Smrg    needs to be reallocated for sharing it with the compositing manager.
46090f2b693Smrg    Instead, allocate pixmap storage which can be shared directly.
46190f2b693Smrg    
46290f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
46390f2b693Smrg
46490f2b693Smrgcommit ebd32b1c07208f8dbe853e089f5e4b7c6a7a658a
46590f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
46690f2b693SmrgDate:   Wed Jan 9 18:57:08 2019 +0100
46790f2b693Smrg
46890f2b693Smrg    dri2: Flush in dri2_create_buffer2 after calling glamor_set_pixmap_bo
46990f2b693Smrg    
47090f2b693Smrg    To make sure the client can't use the shared pixmap storage for direct
47190f2b693Smrg    rendering first, which could produce garbage.
47290f2b693Smrg    
47390f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/109235
47490f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
47590f2b693Smrg
47690f2b693Smrgcommit d168532ee739f7e33a2798051e64ba445dd3859f
47790f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
47890f2b693SmrgDate:   Wed Jan 9 17:24:11 2019 +0100
47990f2b693Smrg
48090f2b693Smrg    dri3: Flush if necessary in dri3_fd_from_pixmap
48190f2b693Smrg    
48290f2b693Smrg    To make sure the client can't use the shared pixmap storage for direct
48390f2b693Smrg    rendering first, which could produce garbage.
48490f2b693Smrg    
48590f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/109235
48690f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
48790f2b693Smrg
48890f2b693Smrgcommit 2058c4c469b172d4a3b0443f75466d84281a64c7
48990f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
49090f2b693SmrgDate:   Thu Jan 10 17:03:04 2019 +0100
49190f2b693Smrg
49290f2b693Smrg    Only call drmmode_validate_leases if RandR is enabled
49390f2b693Smrg    
49490f2b693Smrg    It would crash if RandR is disabled, e.g. because Xinerama is enabled.
49590f2b693Smrg    
49690f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/109230
49790f2b693Smrg    (Ported from radeon commit b1c01698f577577e4a88bad0ae08fb5d998e7ebb)
49890f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
49990f2b693Smrg
50090f2b693Smrgcommit f3c0939a0cbb93c367ece3d41dc69824f585af42
50190f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
50290f2b693SmrgDate:   Thu Jan 10 17:00:12 2019 +0100
50390f2b693Smrg
50490f2b693Smrg    Only call drmmode_uevent_init if RandR is enabled
50590f2b693Smrg    
50690f2b693Smrg    There's no point in listening for hotplug events if RandR is disabled,
50790f2b693Smrg    as there's no other mechanism for them to be propagated. We were already
50890f2b693Smrg    mostly ignoring them in that case.
50990f2b693Smrg    
51090f2b693Smrg    Inspired by
51190f2b693Smrg    https://gitlab.freedesktop.org/xorg/driver/xf86-video-intel/commit/1a489142c8e6a4828348cc9afbd0f430d3b1e2d8
51290f2b693Smrg    (via https://bugs.freedesktop.org/109230#c11).
51390f2b693Smrg    (Ported from radeon commit 38db1bbcfc019c92884c7819a6630c70e543f6b2)
51490f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
51590f2b693Smrg
51690f2b693Smrgcommit f3ddda618ec86650ed85f8b140a5db1394676748
51790f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
51890f2b693SmrgDate:   Mon Dec 17 17:54:05 2018 +0100
51990f2b693Smrg
52090f2b693Smrg    gitlab-ci: Use kaniko instead of docker-in-docker for image generation
52190f2b693Smrg    
52290f2b693Smrg    kaniko can also work in unprivileged runners.
52390f2b693Smrg    
52490f2b693Smrg    Based on v2 of
52590f2b693Smrg    https://gitlab.freedesktop.org/xorg/xserver/merge_requests/92 .
52690f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
52790f2b693Smrg
52890f2b693Smrgcommit b689dc5081493377a31759d24a8dc9fcde12948a
52990f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
53090f2b693SmrgDate:   Tue Dec 18 16:39:28 2018 +0100
53190f2b693Smrg
53290f2b693Smrg    Remove superfluous vrr_flipping field and clean up related code
53390f2b693Smrg    
53490f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
53590f2b693Smrg
53690f2b693Smrgcommit 233a0be82d5c317e58002f4daf836d4f95048465
53790f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
53890f2b693SmrgDate:   Tue Dec 18 16:42:53 2018 +0100
53990f2b693Smrg
54090f2b693Smrg    Don't clear info->flip_window in present_unflip
54190f2b693Smrg    
54290f2b693Smrg    present_unflip can get called between present_check_flip and
54390f2b693Smrg    present_flip, in which case the latter would pass a NULL WindowPtr to
54490f2b693Smrg    the former, resulting in a crash.
54590f2b693Smrg    
54690f2b693Smrg    present_flip should never get called for a window which has already been
54790f2b693Smrg    destroyed, so there's no need to clear info->flip_window.
54890f2b693Smrg    
54990f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/109067
55090f2b693Smrg    Fixes: 2d18b37159edc "Check last flip window instead of screen root
55190f2b693Smrg                          before flipping"
55290f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
55390f2b693Smrg
55490f2b693Smrgcommit d4eab5d108c4569f3a9e2892704ea89b7ee797b6
55590f2b693SmrgAuthor: Mario Kleiner <mario.kleiner.de@gmail.com>
55690f2b693SmrgDate:   Wed Dec 19 07:56:15 2018 +0100
55790f2b693Smrg
55890f2b693Smrg    Fix crash when page flipping in multi-X-Screen/Zaphod mode
55990f2b693Smrg    
56090f2b693Smrg    amdgpu_do_pageflip() indexed the flipdata->fb[] array
56190f2b693Smrg    indexing over config->num_crtc, but the flip completion
56290f2b693Smrg    routines, e.g., drmmode_flip_handler(), index that array
56390f2b693Smrg    via the crtc hw id from drmmode_get_crtc_id(crtc).
56490f2b693Smrg    
56590f2b693Smrg    This is mismatched and causes indexing into the wrong
56690f2b693Smrg    array slot at flip completion -> Server crash.
56790f2b693Smrg    
56890f2b693Smrg    Always use drmmode_get_crtc_id(crtc) for indexing into
56990f2b693Smrg    the array to fix this.
57090f2b693Smrg    
57190f2b693Smrg    Tested on a dual-X-Screen setup with one video output
57290f2b693Smrg    assigned to each X-Screen, page-flipping an OpenGL app
57390f2b693Smrg    on either of both X-Screens. This used to crash when
57490f2b693Smrg    flipping on X-Screen 1, now it doesn't anymore.
57590f2b693Smrg    
57690f2b693Smrg    Fixes: 9b6782c821e0 "Store FB for each CRTC in drmmode_flipdata_rec"
57790f2b693Smrg    (Ported from radeon commit 0058fd2ebf4c900b12f129984e98886a7ac84b2f)
57890f2b693Smrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
57990f2b693Smrg    Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
58090f2b693Smrg
58190f2b693Smrgcommit 0d60233d26ec70d4e1faa343b438e33829c6d5e4
58290f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
58390f2b693SmrgDate:   Thu Nov 22 19:02:20 2018 +0100
58490f2b693Smrg
58590f2b693Smrg    Use two HW cursor buffers per CRTC
58690f2b693Smrg    
58790f2b693Smrg    Switch to the other buffer when xf86_config->cursor changes. Avoids
58890f2b693Smrg    these issues possible when re-using the same buffer:
58990f2b693Smrg    
59090f2b693Smrg    * The HW may intermittently display a mix of the old and new cursor
59190f2b693Smrg      images.
59290f2b693Smrg    * If the hotspot changes, the HW may intermittently display the new
59390f2b693Smrg      cursor image at the location corresponding to the old image's hotspot.
59490f2b693Smrg    
59590f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/108832
59690f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
59790f2b693Smrg
59890f2b693Smrgcommit b04697de5270e8e45744a7025c24df1f454a4cf0
59990f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
60090f2b693SmrgDate:   Fri Nov 23 18:41:00 2018 +0100
60190f2b693Smrg
60290f2b693Smrg    Update cursor position in drmmode_show_cursor if hotspot changed
60390f2b693Smrg    
60490f2b693Smrg    The cursor position is updated to be consistent with the new hotspot in
60590f2b693Smrg    the same ioctl call.
60690f2b693Smrg    
60790f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
60890f2b693Smrg
60990f2b693Smrgcommit b344e1559e936046ef02c777fc4f6bcefa3830bc
61090f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
61190f2b693SmrgDate:   Fri Nov 23 18:22:25 2018 +0100
61290f2b693Smrg
61390f2b693Smrg    Use drmIoctl in drmmode_show_cursor
61490f2b693Smrg    
61590f2b693Smrg    This should be functionally equivalent to what drmModeSetCursor(2) do
61690f2b693Smrg    behind the scenes, but allows for new tricks in following changes.
61790f2b693Smrg    
61890f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
61990f2b693Smrg
62090f2b693Smrgcommit e95044e45350870fa7e237860e89ade91ac03550
62190f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
62290f2b693SmrgDate:   Thu Nov 22 17:54:45 2018 +0100
62390f2b693Smrg
62490f2b693Smrg    Drop AMDGPUInfoRec::cursor_buffer array
62590f2b693Smrg    
62690f2b693Smrg    Not needed or even useful for anything.
62790f2b693Smrg    
62890f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
62990f2b693Smrg
63090f2b693Smrgcommit 13c85e8a136e8626ba84656c6f8321394750f5c7
63190f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
63290f2b693SmrgDate:   Thu Nov 22 17:50:19 2018 +0100
63390f2b693Smrg
63490f2b693Smrg    Don't use GBM for allocating HW cursor BOs
63590f2b693Smrg    
63690f2b693Smrg    GBM doesn't really buy us anything for the cursor BOs. This simplifies
63790f2b693Smrg    the code and following changes.
63890f2b693Smrg    
63990f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
64090f2b693Smrg
64190f2b693Smrgcommit bcfa6c258fdf41a9928f8a3c78fc528d0fafee25
64290f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
64390f2b693SmrgDate:   Wed Nov 21 18:32:04 2018 +0100
64490f2b693Smrg
64590f2b693Smrg    Automatically try re-enabling TearFree after a flip failed
64690f2b693Smrg    
64790f2b693Smrg    Specifically, after both the page flip and vblank ioctls failed, but
64890f2b693Smrg    then the vblank ioctl started working again. This can happen
64990f2b693Smrg    intermittently e.g. when hotplugging a DP display. Previously, TearFree
65090f2b693Smrg    would stay disabled in that case until a modeset was triggered somehow.
65190f2b693Smrg    
65290f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/103791
65390f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
65490f2b693Smrg
65590f2b693Smrgcommit 4e7a24ac5a64e402146953ec5850d13c05742116
65690f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
65790f2b693SmrgDate:   Wed Nov 21 17:54:18 2018 +0100
65890f2b693Smrg
65990f2b693Smrg    Cancel pending scanout update in drmmode_crtc_scanout_update
66090f2b693Smrg    
66190f2b693Smrg    drmmode_crtc_scanout_update does the equivalent of a scanout update,
66290f2b693Smrg    so no need to do it again. This might also avoid issues if there's a
66390f2b693Smrg    pending scanout update at this point.
66490f2b693Smrg    
66590f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
66690f2b693Smrg
66790f2b693Smrgcommit 500fadb16285146e91f62fce3a0ce1360ca684ba
66890f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
66990f2b693SmrgDate:   Wed Nov 21 12:42:22 2018 +0100
67090f2b693Smrg
67190f2b693Smrg    Perform scanout buffer update immediately if drmmode_wait_vblank fails
67290f2b693Smrg    
67390f2b693Smrg    Otherwise the damaged screen contents may never be displayed in that
67490f2b693Smrg    case.
67590f2b693Smrg    
67690f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
67790f2b693Smrg
67890f2b693Smrgcommit be862ed459b06ab7dfc80b5c3d1e2ac7e9327a6e
67990f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
68090f2b693SmrgDate:   Tue Dec 11 11:47:16 2018 +0100
68190f2b693Smrg
68290f2b693Smrg    Generate docker image as part of CI pipeline
68390f2b693Smrg    
68490f2b693Smrg    This removes the dependency on an externally generated docker image, and
68590f2b693Smrg    should make it easier to update the docker image or make other changes
68690f2b693Smrg    related to it.
68790f2b693Smrg    
68890f2b693Smrg    v2:
68990f2b693Smrg    * If the image doesn't exist, try pulling it from the main repo's
69090f2b693Smrg      registry.
69190f2b693Smrg    * Use debian:testing-slim as the base, might result in a slightly
69290f2b693Smrg      smaller image.
69390f2b693Smrg    
69490f2b693Smrg    v3:
69590f2b693Smrg    * Prevent installation of packages which are only recommended, for an
69690f2b693Smrg      even smaller image.
69790f2b693Smrg    * Add recommendation to remove new image from source repository in
69890f2b693Smrg      favour of the main repository's.
69990f2b693Smrg    
70090f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com> # v2
70190f2b693Smrg
70290f2b693Smrgcommit b11ee02c4596ddee3c9ff2141be5c91815efacc3
70390f2b693SmrgAuthor: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
70490f2b693SmrgDate:   Thu Oct 4 09:51:40 2018 -0400
70590f2b693Smrg
70690f2b693Smrg    Support CRTC variable refresh for windows using Present flips
70790f2b693Smrg    
70890f2b693Smrg    This patch adds support for setting the CRTC variable refresh property
70990f2b693Smrg    for suitable windows flipping via the Present extension.
71090f2b693Smrg    
71190f2b693Smrg    The "VariableRefresh" Option is added to AMDGPU in this patch. This
71290f2b693Smrg    option defaults to false, and must be set to "true" in an X conf
71390f2b693Smrg    file for variable refresh support in the driver.
71490f2b693Smrg    
71590f2b693Smrg    In order for a window to be suitable for variable refresh it must have
71690f2b693Smrg    the _VARIABLE_REFRESH property with a 32-bit CARDINAL value of 1.
71790f2b693Smrg    
71890f2b693Smrg    Then the window must pass the checks required to be suitable for
71990f2b693Smrg    Present extension flips - it must cover the entire X screen and no
72090f2b693Smrg    other window may already be flipping.
72190f2b693Smrg    
72290f2b693Smrg    With these conditions met every CRTC for the X screen will have their
72390f2b693Smrg    variable refresh property set to true.
72490f2b693Smrg    
72590f2b693Smrg    Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
72690f2b693Smrg
72790f2b693Smrgcommit 2d18b37159edc526c73a36143fe9b5d6b75e610a
72890f2b693SmrgAuthor: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
72990f2b693SmrgDate:   Tue Nov 13 09:08:01 2018 -0500
73090f2b693Smrg
73190f2b693Smrg    Check last flip window instead of screen root before flipping
73290f2b693Smrg    
73390f2b693Smrg    A significant amount of time can pass between the X call into
73490f2b693Smrg    check_flip for a window and when amdgpu_present_flip actually occurs.
73590f2b693Smrg    To ensure that flipping is still possible there was an additional check
73690f2b693Smrg    performed on screen->root in amdgpu_present_flip - but what should
73790f2b693Smrg    be checked instead is the window itself. This only really worked before
73890f2b693Smrg    because X ensures that the window has the same dimensions as the screen
73990f2b693Smrg    to allow for present extension flipping.
74090f2b693Smrg    
74190f2b693Smrg    This patch tracks the flip window between calls to check_flip and flip
74290f2b693Smrg    and uses that window instead of screen->root.
74390f2b693Smrg    
74490f2b693Smrg    Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
74590f2b693Smrg
74690f2b693Smrgcommit 13c94a373b4858a2d2aa14c22b5f98d53c84c0d9
74790f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
74890f2b693SmrgDate:   Thu Nov 15 16:40:46 2018 +0100
74990f2b693Smrg
75090f2b693Smrg    Skip gamma correction of cursor data if premultiplied R/G/B > alpha
75190f2b693Smrg    
75290f2b693Smrg    The un-premultiplied R/G/B values would overflow the gamma LUT, so just
75390f2b693Smrg    pass through the data unchanged, and leave it up to the HW how to
75490f2b693Smrg    interpret such weird premultiplied alpha pixels.
75590f2b693Smrg    
75690f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/108355
75790f2b693Smrg
75890f2b693Smrgcommit 51ba6dddee40c3688d4c7b12eabeab516ed153b7
75990f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
76090f2b693SmrgDate:   Fri Nov 9 11:00:04 2018 +0100
76190f2b693Smrg
76290f2b693Smrg    Move deferred vblank events to separate drm_vblank_deferred list
76390f2b693Smrg    
76490f2b693Smrg    It was still possible for nested xorg_list_for_each_entry_safe loops
76590f2b693Smrg    to occur over the drm_vblank_signalled list, which could mess up that
76690f2b693Smrg    list. Moving deferred events to a separate list allows processing the
76790f2b693Smrg    drm_vblank_signalled list without xorg_list_for_each_entry_safe.
76890f2b693Smrg    
76990f2b693Smrg    v2:
77090f2b693Smrg    * Refactor drm_handle_vblank_signalled helper function, less code
77190f2b693Smrg      duplication => better readability (Alex Deucher)
77290f2b693Smrg    
77390f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/108600
77490f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
77590f2b693Smrg
77690f2b693Smrgcommit e2c7369cae65069aa93eed1c0b678f975ce5c274
77790f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
77890f2b693SmrgDate:   Mon Nov 5 19:02:31 2018 +0100
77990f2b693Smrg
78090f2b693Smrg    Explicitly keep track of whether a DRM event is for a flip or not
78190f2b693Smrg    
78290f2b693Smrg    When an async flip is performed, and TearFree is enabled on the CRTC
78390f2b693Smrg    used for timing, we schedule a vblank event for completing the page
78490f2b693Smrg    flip. The DRM event queuing code treated this event like a vblank event,
78590f2b693Smrg    but it needs to be treated like a page flip event.
78690f2b693Smrg    
78790f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
78890f2b693Smrg
78990f2b693Smrgcommit eda571222f5a6be47f8897e82d85199bb9d95251
79090f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
79190f2b693SmrgDate:   Mon Nov 5 18:07:54 2018 +0100
79290f2b693Smrg
79390f2b693Smrg    Use drm_abort_one in drm_queue_handler
79490f2b693Smrg    
79590f2b693Smrg    At this point, we've already established that e->handler is NULL, no
79690f2b693Smrg    need to check again in drm_queue_handle_one. This also makes it clearer
79790f2b693Smrg    what's happening.
79890f2b693Smrg    
79990f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
80090f2b693Smrg
80190f2b693Smrgcommit 426f9a49655f01863cf4d898f525e5f95984e0c4
80290f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
80390f2b693SmrgDate:   Tue Nov 6 12:06:20 2018 +0100
80490f2b693Smrg
80590f2b693Smrg    Relax detection of non-premultiplied alpha cursor data
80690f2b693Smrg    
80790f2b693Smrg    The stricter detection broke the cursor in some games. Apparently those
80890f2b693Smrg    use cursor data with premultiplied alpha, but with some pixels having
80990f2b693Smrg    r/g/b values larger than the alpha value (which corresponds to original
81090f2b693Smrg    r/g/b values > 1.0), triggering the workaround.
81190f2b693Smrg    
81290f2b693Smrg    Relax the detection to match what's in the X server since 1.18.4, but
81390f2b693Smrg    keep the workaround for older versions.
81490f2b693Smrg    
81590f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/108650
81690f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
81790f2b693Smrg
81890f2b693Smrgcommit a9da219e13bd0cdec65554382b5cd15abc3e3778
81990f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
82090f2b693SmrgDate:   Wed Nov 14 09:58:28 2018 +0100
82190f2b693Smrg
82290f2b693Smrg    Add README.md to EXTRA_DIST
82390f2b693Smrg    
82490f2b693Smrg    Otherwise it isn't included in the generated tarballs.
82590f2b693Smrg    
82690f2b693Smrg    Suggested-by: Alan Coopersmith <alan.coopersmith@oracle.com>
82790f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
82890f2b693Smrg
82990f2b693Smrgcommit 1cb338253af9c539fc1f13fc12b255ed6303f8b1
83090f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
83190f2b693SmrgDate:   Wed Oct 24 18:07:31 2018 +0200
83290f2b693Smrg
83390f2b693Smrg    man: This driver supports colour depths 8, 15 and 16
83490f2b693Smrg    
83590f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
83690f2b693Smrg
83790f2b693Smrgcommit 0734cdf544ffd3f2ac8749ad0e4bf43f8a5cea50
83890f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
83990f2b693SmrgDate:   Fri Oct 5 12:35:37 2018 +0200
84090f2b693Smrg
84190f2b693Smrg    glamor: Can work at depth >= 15 with current xserver Git master
84290f2b693Smrg    
84390f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
84490f2b693Smrg
84590f2b693Smrgcommit ad6dfb0124860cf67730bde85867f81d9258c84d
84690f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
84790f2b693SmrgDate:   Fri Oct 19 11:02:41 2018 +0200
84890f2b693Smrg
84990f2b693Smrg    Detect and fix up non-premultiplied cursor data
85090f2b693Smrg    
85190f2b693Smrg    X server >= 1.18 already had code for this, but it only caught cases
85290f2b693Smrg    where some pixels have 0 for alpha and non-0 for a non-alpha component.
85390f2b693Smrg    Turns out some apps (e.g. the Civilization VI game) use
85490f2b693Smrg    non-premultiplied cursor data which doesn't have such pixels, but can
85590f2b693Smrg    still result in visual artifacts.
85690f2b693Smrg    
85790f2b693Smrg    This uses the method suggested by Kamil in
85890f2b693Smrg    https://bugs.freedesktop.org/92309#c19: check for pixels where any
85990f2b693Smrg    colour component value is larger than the alpha value, which isn't
86090f2b693Smrg    possible with premultiplied alpha.
86190f2b693Smrg    
86290f2b693Smrg    There can still be non-premultiplied data which won't be caught by this,
86390f2b693Smrg    but that should result in slightly incorrect colours and/or blending at
86490f2b693Smrg    the worst, not wildly incorrect colours such as shown in the bug report
86590f2b693Smrg    below.
86690f2b693Smrg    
86790f2b693Smrg    v2:
86890f2b693Smrg    * Disable the check with current xserver Git master, which already does
86990f2b693Smrg      the same check now.
87090f2b693Smrg    
87190f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/108355
87290f2b693Smrg    Suggested-by: Kamil Páral <kamil.paral@gmail.com>
87390f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
87490f2b693Smrg
87590f2b693Smrgcommit c9d43c1deb9a9cfc41a8d6439caf46d12d220853
87690f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
87790f2b693SmrgDate:   Thu Oct 4 12:54:13 2018 +0200
87890f2b693Smrg
87990f2b693Smrg    Allow up to six instances in Zaphod mode
88090f2b693Smrg    
88190f2b693Smrg    Corresponding to up to six CRTCs being available in the hardware.
88290f2b693Smrg    
88390f2b693Smrg    v2:
88490f2b693Smrg    * Move instance overflow check from PreInit to the probe hooks, in
88590f2b693Smrg      order to further minimize wasted effort.
88690f2b693Smrg    
88790f2b693Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com> # v1
88890f2b693Smrg
88990f2b693Smrgcommit aa572683d86174be2bfc09d4e173ae2a9907d40e
89090f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
89190f2b693SmrgDate:   Wed Oct 10 17:28:35 2018 +0200
89290f2b693Smrg
89390f2b693Smrg    Fix condition for calling set_pixmap_bo in drmmode_xf86crtc_resize
89490f2b693Smrg    
89590f2b693Smrg    This matches CreateScreenResources_KMS.
89690f2b693Smrg    
89790f2b693Smrg    Fixes crash when resizing the screen (e.g. using xrandr) with depth <
89890f2b693Smrg    24.
89990f2b693Smrg    
90090f2b693Smrg    Bugzilla: https://bugs.freedesktop.org/104914
90190f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
90290f2b693Smrg
90390f2b693Smrgcommit 05a1ba9abc941dec616ef7f836f4c54ac93ff9be
90490f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
90590f2b693SmrgDate:   Tue Oct 2 18:01:14 2018 +0200
90690f2b693Smrg
90790f2b693Smrg    Add GitLab CI configuration
90890f2b693Smrg    
90990f2b693Smrg    Builds the driver against all supported versions of xserver, with both
91090f2b693Smrg    gcc and clang for xserver >= 1.18 (older versions cause warnings with
91190f2b693Smrg    clang). Compiler warnings are treated as errors.
91290f2b693Smrg    
91390f2b693Smrg    The xserver 1.15 build uses standalone glamor, the xserver 1.13 & 1.14
91490f2b693Smrg    builds use --disable-glamor.
91590f2b693Smrg    
91690f2b693Smrg    With the latest xserver version, make install and make distcheck are
91790f2b693Smrg    tested as well.
91890f2b693Smrg
91990f2b693Smrgcommit babbd38057559471ab3cb6970010b9a4adf1ef3d
92090f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
92190f2b693SmrgDate:   Tue Oct 2 17:55:03 2018 +0200
92290f2b693Smrg
92390f2b693Smrg    Fix --disable-glamor build
92490f2b693Smrg    
92590f2b693Smrg    We were still relying on the glamor.h header being picked up implicitly.
92690f2b693Smrg
92790f2b693Smrgcommit b6ee7f92cfaa2c134bee101cf89983db73f4c28d
92890f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
92990f2b693SmrgDate:   Tue Oct 2 17:52:10 2018 +0200
93090f2b693Smrg
93190f2b693Smrg    Cast return value of amdgpu_get_marketing_name to char*
93290f2b693Smrg    
93390f2b693Smrg    Avoids compiler warning with xserver < 1.16:
93490f2b693Smrg    
93590f2b693Smrg    ../../src/amdgpu_kms.c: In function ‘AMDGPUPreInitChipType_KMS’:
93690f2b693Smrg    ../../src/amdgpu_kms.c:1203:17: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
93790f2b693Smrg      pScrn->chipset = amdgpu_get_marketing_name(pAMDGPUEnt->pDev);
93890f2b693Smrg                     ^
93990f2b693Smrg
94090f2b693Smrgcommit 955373a3e69baa241a1f267e96d04ddb902f689f
94190f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
94290f2b693SmrgDate:   Tue Sep 25 18:40:01 2018 +0200
94390f2b693Smrg
94490f2b693Smrg    Make wait_pending_flip / handle_deferred symmetric in set_mode_major
94590f2b693Smrg    
94690f2b693Smrg    We were always calling the latter, but not always the former, which
94790f2b693Smrg    could result in handling deferred DRM events prematurely.
94890f2b693Smrg    
94990f2b693Smrg    Acked-by: Slava Abramov <slava.abramov@amd.com>
95090f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
95190f2b693Smrg
95290f2b693Smrgcommit 0cd2c337d2c02b8ec2bd994d6124b4aaaad10741
95390f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
95490f2b693SmrgDate:   Thu Sep 20 17:35:40 2018 +0200
95590f2b693Smrg
95690f2b693Smrg    Handle pending scanout update in drmmode_crtc_scanout_free
95790f2b693Smrg    
95890f2b693Smrg    We have to wait for a pending scanout flip or abort a pending scanout
95990f2b693Smrg    update, otherwise the corresponding event handler will likely crash
96090f2b693Smrg    after drmmode_crtc_scanout_free cleaned up the data structures.
96190f2b693Smrg    
96290f2b693Smrg    Fixes crash after VT switch while dedicated scanout pixmaps are enabled
96390f2b693Smrg    for any CRTC.
96490f2b693Smrg    
96590f2b693Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
96690f2b693Smrg
96790f2b693Smrgcommit ac5b6f96e97aaf95f4e668b4057006b221cffaec
96890f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
96990f2b693SmrgDate:   Thu Sep 20 18:53:05 2018 +0200
97090f2b693Smrg
97190f2b693Smrg    Convert README to markdown
97290f2b693Smrg    
97390f2b693Smrg    And update it a little for the current Gitlab infrastructure.
97490f2b693Smrg
97590f2b693Smrgcommit 451fe96809771ed4e2be3851a65f5360ba9912cb
97690f2b693SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
97790f2b693SmrgDate:   Thu Sep 20 18:48:43 2018 +0200
97890f2b693Smrg
97990f2b693Smrg    Post-release version bump
98090f2b693Smrg
98135d5b7c7Smrgcommit d5e17dc4c78aee5d37de399728066b9be881e044
98235d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
98335d5b7c7SmrgDate:   Fri Sep 14 17:00:17 2018 +0200
98435d5b7c7Smrg
98535d5b7c7Smrg    Bump version for the 18.1.0 release
98635d5b7c7Smrg
98735d5b7c7Smrgcommit 6572be49b713a26eca14f16e1854cabf28101288
98835d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
98935d5b7c7SmrgDate:   Thu Sep 13 11:44:21 2018 +0200
99035d5b7c7Smrg
99135d5b7c7Smrg    Bail from drmmode_cm_init if there's no CRTC
99235d5b7c7Smrg    
99335d5b7c7Smrg    We would crash due to dereferencing the NULL mode_res->crtc pointer.
99435d5b7c7Smrg    
99535d5b7c7Smrg    Bugzilla: https://bugs.freedesktop.org/107913
99635d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
99735d5b7c7Smrg
99835d5b7c7Smrgcommit ca5eb9894fff153c0a1df7bdc4a4745713309e27
99935d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
100035d5b7c7SmrgDate:   Wed Aug 29 18:50:45 2018 +0200
100135d5b7c7Smrg
100235d5b7c7Smrg    Bail early from drm_wait_pending_flip if there's no pending flip
100335d5b7c7Smrg    
100435d5b7c7Smrg    No need to process any events in that case.
100535d5b7c7Smrg    
100635d5b7c7Smrg    v2:
100735d5b7c7Smrg    * Re-check drmmode_crtc->flip_pending after processing each event
100835d5b7c7Smrg
100935d5b7c7Smrgcommit a923bedfd91d39977dbf95f296cf9b68439490f2
101035d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
101135d5b7c7SmrgDate:   Fri Aug 31 12:44:37 2018 +0200
101235d5b7c7Smrg
101335d5b7c7Smrg    Do not push the CM_GAMMA_LUT property values in drmmode_crtc_cm_init
101435d5b7c7Smrg    
101535d5b7c7Smrg    The crtc->gamma_lut values aren't initialized yet at this point, and
101635d5b7c7Smrg    the property values are pushed again from drmmode_setup_colormap
101735d5b7c7Smrg    anyway.
101835d5b7c7Smrg    
101935d5b7c7Smrg    Fixes intermittent flicker due to random gamma LUT values during server
102035d5b7c7Smrg    startup.
102135d5b7c7Smrg    
102235d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
102335d5b7c7Smrg
102435d5b7c7Smrgcommit 26770be44b89b83bf39c28f2fe284c8cb92ed0c0
102535d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
102635d5b7c7SmrgDate:   Wed Aug 29 18:49:19 2018 +0200
102735d5b7c7Smrg
102835d5b7c7Smrg    Don't use xorg_list_for_each_entry_safe for signalled flips
102935d5b7c7Smrg    
103035d5b7c7Smrg    drm_wait_pending_flip can get called from drm_handle_event, in which
103135d5b7c7Smrg    case xorg_list_for_each_entry_safe can end up processing the same entry
103235d5b7c7Smrg    in both. To avoid this, just process the first list entry until the list
103335d5b7c7Smrg    is empty.
103435d5b7c7Smrg
103535d5b7c7Smrgcommit 7eea3e2cd74eed22e982319144e18ae5b1087b78
103635d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
103735d5b7c7SmrgDate:   Wed Aug 29 18:41:19 2018 +0200
103835d5b7c7Smrg
103935d5b7c7Smrg    Always delete entry from list in drm_queue_handler
104035d5b7c7Smrg    
104135d5b7c7Smrg    We left entries without a handler hook in the list, so the list could
104235d5b7c7Smrg    keep taking longer to process and use up more memory.
104335d5b7c7Smrg
104435d5b7c7Smrgcommit b804d7f85d8a07389ba7d3f9b8af8773f852f1c7
104535d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
104635d5b7c7SmrgDate:   Wed Aug 29 17:34:55 2018 +0200
104735d5b7c7Smrg
104835d5b7c7Smrg    glamor: Handle ihandle == -1 in amdgpu_glamor_set_shared_pixmap_backing
104935d5b7c7Smrg    
105035d5b7c7Smrg    (Ported from radeon commit de88ea2755611bdcb18d91d8234d2ab5be8ff2e9)
105135d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
105235d5b7c7Smrg
105335d5b7c7Smrgcommit ae2a450cb98707c4cab8a8265a284cf708bcd43d
105435d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
105535d5b7c7SmrgDate:   Wed Aug 29 17:31:49 2018 +0200
105635d5b7c7Smrg
105735d5b7c7Smrg    Handle ihandle == -1 in amdgpu_set_shared_pixmap_backing
105835d5b7c7Smrg    
105935d5b7c7Smrg    It means to stop using the shared pixmap backing.
106035d5b7c7Smrg    
106135d5b7c7Smrg    (Ported from radeon commit 1799680f7bd84e0618f34f4c7486799521ddaf83)
106235d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
106335d5b7c7Smrg
106435d5b7c7Smrgcommit 34e851d1f284da5afcfe449f349cf1eb5e962408
106535d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
106635d5b7c7SmrgDate:   Fri Aug 24 17:18:10 2018 +0200
106735d5b7c7Smrg
106835d5b7c7Smrg    Use AC_CONFIG_MACRO_DIR instead of AC_CONFIG_MACRO_DIRS
106935d5b7c7Smrg    
107035d5b7c7Smrg    Older versions of autoconf only supported the former.
107135d5b7c7Smrg    
107235d5b7c7Smrg    (Cherry picked from radeon commit cba8fe4d64819aaa8ba516aa68dbe6d2aa153046)
107335d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
107435d5b7c7Smrg
107535d5b7c7Smrgcommit afdfa2a1b6d4b594e0ed345b32279d4a2fd5e188
107635d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
107735d5b7c7SmrgDate:   Fri Aug 24 17:17:43 2018 +0200
107835d5b7c7Smrg
107935d5b7c7Smrg    Add m4 directory
108035d5b7c7Smrg    
108135d5b7c7Smrg    Although normally it only warns about it, under some circumstances,
108235d5b7c7Smrg    aclocal can error out if this directory doesn't exist.
108335d5b7c7Smrg    
108435d5b7c7Smrg    Reported-by: John Lumby <johnlumby@hotmail.com>
108535d5b7c7Smrg    (Cherry picked from radeon commit 7b01c10137aba24c8f61dd9b2a19ea257ad24371)
108635d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
108735d5b7c7Smrg
108835d5b7c7Smrgcommit f6cd72e64e85896b6d155bee0930e59771dcb701
108935d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
109035d5b7c7SmrgDate:   Thu Aug 16 16:31:01 2018 +0200
109135d5b7c7Smrg
109235d5b7c7Smrg    Use correct FB handle in amdgpu_do_pageflip
109335d5b7c7Smrg    
109435d5b7c7Smrg    We were always using the handle of the client provided FB, which
109535d5b7c7Smrg    prevented RandR transforms from working, and could result in a black
109635d5b7c7Smrg    screen.
109735d5b7c7Smrg    
109835d5b7c7Smrg    Fixes: 9b6782c821e0 "Store FB for each CRTC in drmmode_flipdata_rec"
109935d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
110035d5b7c7Smrg
110135d5b7c7Smrgcommit 85cd8eef0cbed7b409b07f58d76dacd34aa3ddea
110235d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
110335d5b7c7SmrgDate:   Tue Jul 24 18:58:27 2018 +0200
110435d5b7c7Smrg
110535d5b7c7Smrg    Remove drmmode_crtc_private_rec::present_vblank_* related code
110635d5b7c7Smrg    
110735d5b7c7Smrg    Not needed anymore with the more robust mechanisms for preventing nested
110835d5b7c7Smrg    drmHandleEvent calls introduced in the previous changes.
110935d5b7c7Smrg    
111035d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
111135d5b7c7Smrg
111235d5b7c7Smrgcommit e52872da69ecc84dafb3355839e35b0383f0d228
111335d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
111435d5b7c7SmrgDate:   Fri Jul 20 16:56:22 2018 +0200
111535d5b7c7Smrg
111635d5b7c7Smrg    Defer vblank event handling while waiting for a pending flip
111735d5b7c7Smrg    
111835d5b7c7Smrg    This is to avoid submitting more flips while we are waiting for pending
111935d5b7c7Smrg    ones to complete.
112035d5b7c7Smrg    
112135d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
112235d5b7c7Smrg
112335d5b7c7Smrgcommit 739181c8d3334ff14b5a607895dfdeb29b0d9020
112435d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
112535d5b7c7SmrgDate:   Wed Jul 25 13:00:15 2018 +0200
112635d5b7c7Smrg
112735d5b7c7Smrg    Add amdgpu_drm_handle_event wrapper for drmHandleEvent
112835d5b7c7Smrg    
112935d5b7c7Smrg    Instead of processing DRM events directly from drmHandleEvent's
113035d5b7c7Smrg    callbacks, there are three phases:
113135d5b7c7Smrg    
113235d5b7c7Smrg    1. drmHandleEvent is called, and signalled events are re-queued to
113335d5b7c7Smrg       _signalled lists from its callbacks.
113435d5b7c7Smrg    2. Signalled page flip completion events are processed.
113535d5b7c7Smrg    3. Signalled vblank events are processed.
113635d5b7c7Smrg    
113735d5b7c7Smrg    This should make sure that we never call drmHandleEvent from one of its
113835d5b7c7Smrg    callbacks, which would usually result in blocking forever.
113935d5b7c7Smrg
114035d5b7c7Smrgcommit 6029794e8a35417faf825491a89b85f713c77fc1
114135d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
114235d5b7c7SmrgDate:   Fri Jul 20 17:07:23 2018 +0200
114335d5b7c7Smrg
114435d5b7c7Smrg    Add amdgpu_drm_wait_pending_flip function
114535d5b7c7Smrg    
114635d5b7c7Smrg    Replacing the drmmode_crtc_wait_pending_event macro.
114735d5b7c7Smrg    
114835d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
114935d5b7c7Smrg
115035d5b7c7Smrgcommit 0148283984c77f7a6e97026edc3093497547e0a4
115135d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
115235d5b7c7SmrgDate:   Fri Jul 20 16:37:05 2018 +0200
115335d5b7c7Smrg
115435d5b7c7Smrg    Move DRM event queue related initialization to amdgpu_drm_queue_init
115535d5b7c7Smrg    
115635d5b7c7Smrg    And make amdgpu_drm_queue_handler not directly accessible outside of
115735d5b7c7Smrg    amdgpu_drm_queue.c.
115835d5b7c7Smrg    
115935d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
116035d5b7c7Smrg
116135d5b7c7Smrgcommit 7f65a8c9e03bddf2378aaa928460632ed6b1a688
116235d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
116335d5b7c7SmrgDate:   Fri Aug 3 17:52:28 2018 +0200
116435d5b7c7Smrg
116535d5b7c7Smrg    glamor: Check glamor module version for depth 30 support
116635d5b7c7Smrg    
116735d5b7c7Smrg    Instead of the Xorg version. This should allow glamor backported from
116835d5b7c7Smrg    xserver >= 1.20 to work with older Xorg versions.
116935d5b7c7Smrg    
117035d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
117135d5b7c7Smrg
117235d5b7c7Smrgcommit 08c4d42f43f80baa4bbc2ff9d0a422202cdc3538
117335d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
117435d5b7c7SmrgDate:   Thu Aug 2 18:41:04 2018 +0200
117535d5b7c7Smrg
117635d5b7c7Smrg    glamor: Use glamor_egl_create_textured_pixmap_from_gbm_bo when possible
117735d5b7c7Smrg    
117835d5b7c7Smrg    Inspired by the modesetting driver.
117935d5b7c7Smrg    
118035d5b7c7Smrg    (Ported from radeon commit db28d35ce9fd07a2a4703f3df0633d4c8291ff9b)
118135d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
118235d5b7c7Smrg
118335d5b7c7Smrgcommit 9b6782c821e0bdc53336d98f87ddde752faf7902
118435d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
118535d5b7c7SmrgDate:   Fri Jul 27 17:55:11 2018 +0200
118635d5b7c7Smrg
118735d5b7c7Smrg    Store FB for each CRTC in drmmode_flipdata_rec
118835d5b7c7Smrg    
118935d5b7c7Smrg    We were only storing the FB provided by the client, but on CRTCs with
119035d5b7c7Smrg    TearFree enabled, we use a separate FB. This could cause
119135d5b7c7Smrg    drmmode_flip_handler to fail to clear drmmode_crtc->flip_pending, which
119235d5b7c7Smrg    could result in a hang when waiting for the pending flip to complete. We
119335d5b7c7Smrg    were trying to avoid that by always clearing drmmode_crtc->flip_pending
119435d5b7c7Smrg    when TearFree is enabled, but that wasn't reliable, because
119535d5b7c7Smrg    drmmode_crtc->tear_free can already be FALSE at this point when
119635d5b7c7Smrg    disabling TearFree.
119735d5b7c7Smrg    
119835d5b7c7Smrg    Now that we're keeping track of each CRTC's flip FB separately,
119935d5b7c7Smrg    drmmode_flip_handler can reliably clear flip_pending, and we no longer
120035d5b7c7Smrg    need the TearFree hack.
120135d5b7c7Smrg    
120235d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
120335d5b7c7Smrg
120435d5b7c7Smrgcommit 2989d40ef74d9966e8e8df2ef7727b2cc48d4960
120535d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
120635d5b7c7SmrgDate:   Wed Jul 25 18:37:48 2018 +0200
120735d5b7c7Smrg
120835d5b7c7Smrg    glamor: Set AMDGPU_CREATE_PIXMAP_DRI2 for DRI3 pixmaps
120935d5b7c7Smrg    
121035d5b7c7Smrg    Not doing this resulted in falling back to software for DRI3 client
121135d5b7c7Smrg    presentation operations with ShadowPrimary.
121235d5b7c7Smrg    
121335d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
121435d5b7c7Smrg
121535d5b7c7Smrgcommit f3b2ed37d683f8616a0a31ff63133ddb8fe1a4a3
121635d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
121735d5b7c7SmrgDate:   Mon Jul 23 18:42:39 2018 +0200
121835d5b7c7Smrg
121935d5b7c7Smrg    Use strcpy for RandR output property names
122035d5b7c7Smrg    
122135d5b7c7Smrg    Instead of strncpy with the string length. Avoids new warnings with GCC
122235d5b7c7Smrg    8:
122335d5b7c7Smrg    
122435d5b7c7Smrg    ../../src/drmmode_display.c: In function ‘drmmode_output_create_resources’:
122535d5b7c7Smrg    ../../src/drmmode_display.c:2240:2: warning: ‘strncpy’ output truncated before terminating nul copying 8 bytes from a string of the same length [-Wstringop-truncation]
122635d5b7c7Smrg      strncpy(tearfree_prop->name, "TearFree", 8);
122735d5b7c7Smrg      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
122835d5b7c7Smrg    ../../src/drmmode_display.c:2244:2: warning: ‘strncpy’ output truncated before terminating nul copying 3 bytes from a string of the same length [-Wstringop-truncation]
122935d5b7c7Smrg      strncpy(tearfree_prop->enums[0].name, "off", 3);
123035d5b7c7Smrg      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
123135d5b7c7Smrg    ../../src/drmmode_display.c:2245:2: warning: ‘strncpy’ output truncated before terminating nul copying 2 bytes from a string of the same length [-Wstringop-truncation]
123235d5b7c7Smrg      strncpy(tearfree_prop->enums[1].name, "on", 2);
123335d5b7c7Smrg      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
123435d5b7c7Smrg    ../../src/drmmode_display.c:2247:2: warning: ‘strncpy’ output truncated before terminating nul copying 4 bytes from a string of the same length [-Wstringop-truncation]
123535d5b7c7Smrg      strncpy(tearfree_prop->enums[2].name, "auto", 4);
123635d5b7c7Smrg      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
123735d5b7c7Smrg    
123835d5b7c7Smrg    Reviewed-by: Slava Abramov <slava.abramov@amd.com>
123935d5b7c7Smrg
124035d5b7c7Smrgcommit 5f06d6b8ba570b500956ad26fee711d5ac427818
124135d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
124235d5b7c7SmrgDate:   Tue Jul 17 19:00:51 2018 +0200
124335d5b7c7Smrg
124435d5b7c7Smrg    Remove drmmode_terminate_leases
124535d5b7c7Smrg    
124635d5b7c7Smrg    The RandR screen private is already freed when our CloseScreen runs, so
124735d5b7c7Smrg    this can't do anything useful. This cleanup has to be done by the X
124835d5b7c7Smrg    server itself.
124935d5b7c7Smrg
125035d5b7c7Smrgcommit 7cc2d4515a63845a027214daf4d391cf56e35bb3
125135d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
125235d5b7c7SmrgDate:   Thu Jul 19 16:59:22 2018 +0200
125335d5b7c7Smrg
125435d5b7c7Smrg    Remove AMDGPUInfoRec::fbcon_pixmap
125535d5b7c7Smrg    
125635d5b7c7Smrg    We always destroy the fbcon pixmap in drmmode_copy_fb anyway.
125735d5b7c7Smrg    
125835d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
125935d5b7c7Smrg
126035d5b7c7Smrgcommit 46d87187c6a0b8f941cc6f30af1f53a98ff2e635
126135d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
126235d5b7c7SmrgDate:   Thu Jul 19 12:37:42 2018 +0200
126335d5b7c7Smrg
126435d5b7c7Smrg    Don't use DRM_IOCTL_GEM_FLINK in create_pixmap_for_fbcon
126535d5b7c7Smrg    
126635d5b7c7Smrg    We don't need it.
126735d5b7c7Smrg
126835d5b7c7Smrgcommit b8d8416792488f7b15c94234d7e0e35d5ce10ed9
126935d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
127035d5b7c7SmrgDate:   Thu Jul 19 11:36:19 2018 +0200
127135d5b7c7Smrg
127235d5b7c7Smrg    Free previous xf86CrtcRec gamma LUT memory
127335d5b7c7Smrg    
127435d5b7c7Smrg    We were leaking it.
127535d5b7c7Smrg    
127635d5b7c7Smrg    Also, don't bother allocating new memory if it's already the expected
127735d5b7c7Smrg    size.
127835d5b7c7Smrg    
127935d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
128035d5b7c7Smrg
128135d5b7c7Smrgcommit ae8e02c6fc4ef5d5340b8cd4739e66b19b9e3386
128235d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
128335d5b7c7SmrgDate:   Fri Jul 13 10:38:56 2018 +0200
128435d5b7c7Smrg
128535d5b7c7Smrg    Hardcode "non-desktop" RandR property name
128635d5b7c7Smrg    
128735d5b7c7Smrg    It's a bit silly to require current randrproto just for this definition,
128835d5b7c7Smrg    which can't really change anyway.
128935d5b7c7Smrg    
129035d5b7c7Smrg    Suggested-by: Qiang Yu <qiang.yu@amd.com>
129135d5b7c7Smrg    Reviewed-by: Qiang Yu <Qiang.Yu@amd.com>
129235d5b7c7Smrg
129335d5b7c7Smrgcommit 1247be21704dd185ce26097e11b3685815ffac4f
129435d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
129535d5b7c7SmrgDate:   Fri Jul 13 18:30:04 2018 +0200
129635d5b7c7Smrg
129735d5b7c7Smrg    Support gamma correction & colormaps at depth 30 as well
129835d5b7c7Smrg    
129935d5b7c7Smrg    Only supported with the advanced colour management properties available
130035d5b7c7Smrg    with DC as of kernel 4.17.
130135d5b7c7Smrg    
130235d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
130335d5b7c7Smrg
130435d5b7c7Smrgcommit 9dfbae76b179285d142b97852211b900ebfae51d
130535d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
130635d5b7c7SmrgDate:   Tue Jul 10 18:13:39 2018 +0200
130735d5b7c7Smrg
130835d5b7c7Smrg    Move flush from radeon_scanout_do_update to its callers
130935d5b7c7Smrg    
131035d5b7c7Smrg    No functional change intended.
131135d5b7c7Smrg    
131235d5b7c7Smrg    (Ported from radeon commit 90b94d40449f665f2d12874598062a5e5e5b64cd)
131335d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
131435d5b7c7Smrg
131535d5b7c7Smrgcommit ace6ea016ce0013a34e1d4637aeacbf4d0e83c79
131635d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
131735d5b7c7SmrgDate:   Tue Jul 10 18:11:04 2018 +0200
131835d5b7c7Smrg
131935d5b7c7Smrg    glamor: Bail CreatePixmap on unsupported pixmap depth
132035d5b7c7Smrg    
132135d5b7c7Smrg    Fixes crash in that case.
132235d5b7c7Smrg    
132335d5b7c7Smrg    Bugzilla: https://bugs.freedesktop.org/106293
132435d5b7c7Smrg    (Ported from radeon commit 65c9dfea4e841b7d6f795c7489fede58c5e9631f)
132535d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
132635d5b7c7Smrg
132735d5b7c7Smrgcommit c160302abcdb18eec35c377d80e34f5bd857df45
132835d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
132935d5b7c7SmrgDate:   Thu May 17 09:50:50 2018 +0200
133035d5b7c7Smrg
133135d5b7c7Smrg    Bail from dri2_create_buffer2 if we can't get a pixmap
133235d5b7c7Smrg    
133335d5b7c7Smrg    We would store the NULL pointer and continue, which would lead to a
133435d5b7c7Smrg    crash down the road.
133535d5b7c7Smrg    
133635d5b7c7Smrg    Bugzilla: https://bugs.freedesktop.org/106293
133735d5b7c7Smrg    (Ported from radeon commit 3dcfce8d0f495d09d7836caf98ef30d625b78a13)
133835d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
133935d5b7c7Smrg
134035d5b7c7Smrgcommit 61040bdfa360975614fb47aa7ea1b3a1abac3427
134135d5b7c7SmrgAuthor: Keith Packard <keithp@keithp.com>
134235d5b7c7SmrgDate:   Mon Feb 12 13:51:56 2018 -0800
134335d5b7c7Smrg
134435d5b7c7Smrg    Add RandR leases support
134535d5b7c7Smrg    
134635d5b7c7Smrg    Signed-off-by: Keith Packard <keithp@keithp.com>
134735d5b7c7Smrg    (Ported from xserver commit e4e3447603b5fd3a38a92c3f972396d1f81168ad)
134835d5b7c7Smrg    Reviewed-by: Keith Packard <keithp@keithp.com>
134935d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
135035d5b7c7Smrg
135135d5b7c7Smrgcommit ab7e39c5a03e24c3ce3ee2f22ada7572bc2d9aa7
135235d5b7c7SmrgAuthor: Keith Packard <keithp@keithp.com>
135335d5b7c7SmrgDate:   Mon Feb 12 13:51:55 2018 -0800
135435d5b7c7Smrg
135535d5b7c7Smrg    modesetting: Create CONNECTOR_ID properties for outputs [v2]
135635d5b7c7Smrg    
135735d5b7c7Smrg    This lets a DRM client map between X outputs and kernel connectors.
135835d5b7c7Smrg    
135935d5b7c7Smrg    v2:
136035d5b7c7Smrg            Change CONNECTOR_ID to enum -- Adam Jackson <ajax@nwnk.net>
136135d5b7c7Smrg    
136235d5b7c7Smrg    Signed-off-by: Keith Packard <keithp@keithp.com>
136335d5b7c7Smrg    (Ported from xserver commit 023d4aba8d45e9e3630b944ecfb650c081799b96)
136435d5b7c7Smrg    Reviewed-by: Keith Packard <keithp@keithp.com>
136535d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
136635d5b7c7Smrg
136735d5b7c7Smrgcommit 14db71a606128c4a207f43298809af279b77e2a8
136835d5b7c7SmrgAuthor: Keith Packard <keithp@keithp.com>
136935d5b7c7SmrgDate:   Mon Feb 12 13:51:53 2018 -0800
137035d5b7c7Smrg
137135d5b7c7Smrg    modesetting: Record non-desktop kernel property at PreInit time
137235d5b7c7Smrg    
137335d5b7c7Smrg    Save any value of the kernel non-desktop property in the xf86Output
137435d5b7c7Smrg    structure to avoid non-desktop outputs in the default configuration.
137535d5b7c7Smrg    
137635d5b7c7Smrg    [Also bump randrproto requirement to a version that defines
137735d5b7c7Smrg    RR_PROPERTY_NON_DESKTOP - ajax]
137835d5b7c7Smrg    
137935d5b7c7Smrg    Signed-off-by: Keith Packard <keithp@keithp.com>
138035d5b7c7Smrg    (Ported from xserver commit b91c787c4cd2d20685db69426c539938c556128a)
138135d5b7c7Smrg    Reviewed-by: Keith Packard <keithp@keithp.com>
138235d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
138335d5b7c7Smrg
138435d5b7c7Smrgcommit baea4fa492f635cdfe746a84be2e337d9aeae8a9
138535d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
138635d5b7c7SmrgDate:   Tue Jun 26 19:02:21 2018 +0200
138735d5b7c7Smrg
138835d5b7c7Smrg    Call drmmode_crtc_gamma_do_set from drmmode_setup_colormap
138935d5b7c7Smrg    
139035d5b7c7Smrg    Instead of from drmmode_set_mode_major. There's no need to re-set the
139135d5b7c7Smrg    gamma LUT on every modeset, the kernel should preserve it.
139235d5b7c7Smrg    
139335d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
139435d5b7c7Smrg
139535d5b7c7Smrgcommit 19a40758be04e1d451a030f452efb49e8aaad541
139635d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
139735d5b7c7SmrgDate:   Wed Jun 27 18:36:43 2018 +0200
139835d5b7c7Smrg
139935d5b7c7Smrg    Remove #if 0'd code
140035d5b7c7Smrg    
140135d5b7c7Smrg    This has always been disabled, no need to keep it.
140235d5b7c7Smrg    
140335d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
140435d5b7c7Smrg    Reviewed-by: Slava Abramov <slava.abramov@amd.com>
140535d5b7c7Smrg
140635d5b7c7Smrgcommit 8e98195e58f77fd1f354b2707360bd4445aef5b4
140735d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
140835d5b7c7SmrgDate:   Tue Jun 26 18:40:23 2018 +0200
140935d5b7c7Smrg
141035d5b7c7Smrg    Don't apply gamma to HW cursor data if colour management is enabled
141135d5b7c7Smrg    
141235d5b7c7Smrg    In that case (with DC as of 4.17 kernels), the display hardware applies
141335d5b7c7Smrg    gamma to the HW cursor.
141435d5b7c7Smrg    
141535d5b7c7Smrg    v2:
141635d5b7c7Smrg    * Also use all 0s when alpha == 0 in the gamma passthrough case.
141735d5b7c7Smrg    
141835d5b7c7Smrg    Bugzilla: https://bugs.freedesktop.org/106578
141935d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
142035d5b7c7Smrg
142135d5b7c7Smrgcommit 606075b852d8e1d40ed0a56b5a928abdd7012f95
142235d5b7c7SmrgAuthor: Leo Li (Sunpeng) <sunpeng.li@amd.com>
142335d5b7c7SmrgDate:   Fri Jun 15 17:05:52 2018 -0400
142435d5b7c7Smrg
142535d5b7c7Smrg    Also compose LUT when setting legacy gamma
142635d5b7c7Smrg    
142735d5b7c7Smrg    We compose the two LUTs when pushing non-legacy gamma changes, and the
142835d5b7c7Smrg    same needs to be done when setting legacy gamma.
142935d5b7c7Smrg    
143035d5b7c7Smrg    To do so, we just call push_cm_prop() on the gamma LUT. It will compose
143135d5b7c7Smrg    the LUTs for us, and fall back to using legacy LUT (upscaled to non-
143235d5b7c7Smrg    legacy size) if non-legacy is unavailable.
143335d5b7c7Smrg    
143435d5b7c7Smrg    It's also possible that the Kernel has no support support for non-
143535d5b7c7Smrg    legacy color. In which case, we fall back to legacy gamma.
143635d5b7c7Smrg    
143735d5b7c7Smrg    v2: Remove per-CRTC check for color management support.
143835d5b7c7Smrg    
143935d5b7c7Smrg    Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
144035d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
144135d5b7c7Smrg
144235d5b7c7Smrgcommit e0a4c0e2155a5fcfad747ea5bddcf5b4b551f151
144335d5b7c7SmrgAuthor: Leo Li (Sunpeng) <sunpeng.li@amd.com>
144435d5b7c7SmrgDate:   Fri Jun 15 17:12:48 2018 -0400
144535d5b7c7Smrg
144635d5b7c7Smrg    Compose non-legacy with legacy regamma LUT
144735d5b7c7Smrg    
144835d5b7c7Smrg    Frequently, a user may have non-legacy gamma enabled for monitor
144935d5b7c7Smrg    correction, while using legacy gamma for things like
145035d5b7c7Smrg    redshift/nightlight.
145135d5b7c7Smrg    
145235d5b7c7Smrg    To do so, we compose the two LUTs. Legacy gamma will be applied first,
145335d5b7c7Smrg    then non-legacy. i.e. non-legacy_LUT(legacy_LUT(in_color)).
145435d5b7c7Smrg    
145535d5b7c7Smrg    Note that the staged gamma LUT within the driver-private CRTC will
145635d5b7c7Smrg    always contain the non-legacy LUT. This is to ensure that we have a
145735d5b7c7Smrg    cached copy for future compositions.
145835d5b7c7Smrg    
145935d5b7c7Smrg    v2: Don't compose LUTs if legacy gamma is disabled (which is the case
146035d5b7c7Smrg        for deep 30bpp color). The legacy LUT won't be computed here,
146135d5b7c7Smrg        causing composition to spit out something invalid.
146235d5b7c7Smrg    
146335d5b7c7Smrg    v3: Use LUT sizes that are now cached in drmmode.
146435d5b7c7Smrg    
146535d5b7c7Smrg    Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
146635d5b7c7Smrg    
146735d5b7c7Smrg    [ Michel Dänzer: Replace "crtc->funcs->gamma_set == NULL" with
146835d5b7c7Smrg      !crtc->funcs->gamma_set ]
146935d5b7c7Smrg    
147035d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
147135d5b7c7Smrg
147235d5b7c7Smrgcommit e1fe46013c281f4644ca49915ae0ff081582a5b9
147335d5b7c7SmrgAuthor: Leo Li (Sunpeng) <sunpeng.li@amd.com>
147435d5b7c7SmrgDate:   Fri Jun 15 17:05:39 2018 -0400
147535d5b7c7Smrg
147635d5b7c7Smrg    Enable setting of color properties via RandR
147735d5b7c7Smrg    
147835d5b7c7Smrg    Setting a color property involves:
147935d5b7c7Smrg    1. Staging the property onto the driver-private CRTC object
148035d5b7c7Smrg    2. Pushing the staged property into kernel DRM, for HW programming
148135d5b7c7Smrg    
148235d5b7c7Smrg    Add a function to do the staging, and execute the above steps in
148335d5b7c7Smrg    output_property_set.
148435d5b7c7Smrg    
148535d5b7c7Smrg    v2:
148635d5b7c7Smrg    - Remove per-CRTC check for color management support in stage_cm_prop.
148735d5b7c7Smrg    - Use switch statement instead of if statements.
148835d5b7c7Smrg    
148935d5b7c7Smrg    Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
149035d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
149135d5b7c7Smrg
149235d5b7c7Smrgcommit 29de2859e296b4e9f0b4ae7564c353c5518f3f08
149335d5b7c7SmrgAuthor: Leo Li (Sunpeng) <sunpeng.li@amd.com>
149435d5b7c7SmrgDate:   Fri Jun 15 17:05:28 2018 -0400
149535d5b7c7Smrg
149635d5b7c7Smrg    Update color properties on output_get_property
149735d5b7c7Smrg    
149835d5b7c7Smrg    Notify RandR of any updated color properties on the output's CRTC when
149935d5b7c7Smrg    its get_property() hook is called.
150035d5b7c7Smrg    
150135d5b7c7Smrg    v2: Remove per-CRTC check for color management support.
150235d5b7c7Smrg    
150335d5b7c7Smrg    Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
150435d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
150535d5b7c7Smrg
150635d5b7c7Smrgcommit 639acf54b4de6f62000d12cc6dbf4f5e49cae888
150735d5b7c7SmrgAuthor: Leo Li (Sunpeng) <sunpeng.li@amd.com>
150835d5b7c7SmrgDate:   Fri Jun 15 17:04:58 2018 -0400
150935d5b7c7Smrg
151035d5b7c7Smrg    Configure color properties when creating output resources
151135d5b7c7Smrg    
151235d5b7c7Smrg    List color management properties on outputs if there is kernel support.
151335d5b7c7Smrg    Otherwise, don't list them at all.
151435d5b7c7Smrg    
151535d5b7c7Smrg    v2:
151635d5b7c7Smrg    - Use switch statement in configure_and_change
151735d5b7c7Smrg    - Also configure LUT sizes for outputs that don't have an attached CRTC.
151835d5b7c7Smrg      We can do this since LUT sizes are now cached on the drmmode object.
151935d5b7c7Smrg    
152035d5b7c7Smrg    Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
152135d5b7c7Smrg    
152235d5b7c7Smrg    [ Michel Dänzer: Drop const from data pointer declaration in
152335d5b7c7Smrg      rr_configure_and_change_cm_property, to avoid warning when building
152435d5b7c7Smrg      against xserver 1.13 ]
152535d5b7c7Smrg    
152635d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
152735d5b7c7Smrg
152835d5b7c7Smrgcommit 3cf5a281d8481c997029dae164d6fdeca66b9447
152935d5b7c7SmrgAuthor: Leo Li (Sunpeng) <sunpeng.li@amd.com>
153035d5b7c7SmrgDate:   Fri Jun 15 17:04:44 2018 -0400
153135d5b7c7Smrg
153235d5b7c7Smrg    Initialize color properties on CRTC during CRTC init
153335d5b7c7Smrg    
153435d5b7c7Smrg    And destroy them on the CRTC destroy hook.
153535d5b7c7Smrg    
153635d5b7c7Smrg    When initializing color management properties on the private
153735d5b7c7Smrg    drmmode_crtc, we want to:
153835d5b7c7Smrg    
153935d5b7c7Smrg    1. Default its color transform matrix (CTM) to identity
154035d5b7c7Smrg    2. Program hardware with default color management values (SRGB for
154135d5b7c7Smrg       de/regamma, identity for CTM)
154235d5b7c7Smrg    
154335d5b7c7Smrg    It's possible that cm initialization fails due to memory error or DRM
154435d5b7c7Smrg    error. In which case, the RandR state may not reflect the actual
154535d5b7c7Smrg    hardware state.
154635d5b7c7Smrg    
154735d5b7c7Smrg    v2:
154835d5b7c7Smrg    - Use switch statement in push_cm_prop
154935d5b7c7Smrg    - Get rid of per-CRTC cm support checks. Keep it simple and only check
155035d5b7c7Smrg      the first CRTC, since kernel will always report all or nothing for AMD
155135d5b7c7Smrg      hardware.
155235d5b7c7Smrg    - Remove per-CRTC LUT size caching, drmmode now holds that. Update
155335d5b7c7Smrg      commit message to reflect this.
155435d5b7c7Smrg    
155535d5b7c7Smrg    Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
155635d5b7c7Smrg    
155735d5b7c7Smrg    [ Michel Dänzer: Replace "drmmode_crtc->ctm == NULL" with
155835d5b7c7Smrg      !drmmode_crtc->ctm ]
155935d5b7c7Smrg    
156035d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
156135d5b7c7Smrg
156235d5b7c7Smrgcommit 810ed133cd67b3deb38d1af87e252a094e9ee8f2
156335d5b7c7SmrgAuthor: Leo Li (Sunpeng) <sunpeng.li@amd.com>
156435d5b7c7SmrgDate:   Fri Jun 15 17:02:57 2018 -0400
156535d5b7c7Smrg
156635d5b7c7Smrg    Cache color property IDs and LUT sizes during pre-init
156735d5b7c7Smrg    
156835d5b7c7Smrg    DRM creates property types with unique IDs during kernel driver init.
156935d5b7c7Smrg    Cache the color property IDs on DDX init for use later, when we need
157035d5b7c7Smrg    to modify these properties. Also cache the (de)gamma LUT sizes, since
157135d5b7c7Smrg    they are the same for all CRTCs on AMD hardware.
157235d5b7c7Smrg    
157335d5b7c7Smrg    Since these values are the same regardless of the CRTC, they can be
157435d5b7c7Smrg    cached within the private drmmode_rec object. We can also use any color-
157535d5b7c7Smrg    management-enabled CRTC to initially fetch them.
157635d5b7c7Smrg    
157735d5b7c7Smrg    Also introduce an enumeration of possible color management properties,
157835d5b7c7Smrg    to provide a easy and unified way of referring to them.
157935d5b7c7Smrg    
158035d5b7c7Smrg    v2:
158135d5b7c7Smrg    - Reorder cm property enum so that LUT sizes are at the end. This allows
158235d5b7c7Smrg      us to use DEGAMMA_LUT_SIZE as an anchor for iterating over mutable cm
158335d5b7c7Smrg      properties.
158435d5b7c7Smrg    - Cache (de)gamma LUT sizes within drmmode, since it's the same for all
158535d5b7c7Smrg      CRTCs on AMD hardware. Update commit message to reflect this.
158635d5b7c7Smrg    
158735d5b7c7Smrg    Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
158835d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
158935d5b7c7Smrg
159035d5b7c7Smrgcommit 940c8b39f79789d4d5ddb8ab8d25a8ae05932756
159135d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
159235d5b7c7SmrgDate:   Tue Jun 12 18:45:08 2018 +0200
159335d5b7c7Smrg
159435d5b7c7Smrg    Check dimensions passed to drmmode_xf86crtc_resize
159535d5b7c7Smrg    
159635d5b7c7Smrg    When enabling a secondary GPU output, Xorg can try resizing the screen
159735d5b7c7Smrg    beyond the limit advertised by the driver, leading to drmModeAddFB
159835d5b7c7Smrg    failing and primary GPU outputs turning off. Check for this and bail
159935d5b7c7Smrg    instead.
160035d5b7c7Smrg
160135d5b7c7Smrgcommit 74124f2c17dbb4b752707bb7eee398ae099e8a2c
160235d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
160335d5b7c7SmrgDate:   Fri May 18 12:31:57 2018 +0200
160435d5b7c7Smrg
160535d5b7c7Smrg    Use drmmode_crtc_dpms in drmmode_set_desired_modes
160635d5b7c7Smrg    
160735d5b7c7Smrg    Simplifies the latter slightly.
160835d5b7c7Smrg    
160935d5b7c7Smrg    Reviewed-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
161035d5b7c7Smrg
161135d5b7c7Smrgcommit ceeacb455cd058492a493aac954deab8455804b5
161235d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
161335d5b7c7SmrgDate:   Fri May 18 12:13:23 2018 +0200
161435d5b7c7Smrg
161535d5b7c7Smrg    Call drmmode_do_crtc_dpms from drmmode_crtc_dpms as well
161635d5b7c7Smrg    
161735d5b7c7Smrg    Leo pointed out that drmmode_do_crtc_dpms wasn't getting called when
161835d5b7c7Smrg    turning off an output with
161935d5b7c7Smrg    
162035d5b7c7Smrg     xrandr --output <output> --off
162135d5b7c7Smrg    
162235d5b7c7Smrg    This meant that the vblank sequence number and timestamp wouldn't be
162335d5b7c7Smrg    saved before turning off the CRTC in this case.
162435d5b7c7Smrg    
162535d5b7c7Smrg    Reported-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
162635d5b7c7Smrg    Reviewed-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
162735d5b7c7Smrg
162835d5b7c7Smrgcommit e8e688f3852fb06b0c34ed5bce47c9493bcd1613
162935d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
163035d5b7c7SmrgDate:   Wed May 16 16:49:20 2018 +0200
163135d5b7c7Smrg
163235d5b7c7Smrg    Replace 'foo == NULL' with '!foo'
163335d5b7c7Smrg    
163435d5b7c7Smrg    Shorter and sweeter. :)
163535d5b7c7Smrg    
163635d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
163735d5b7c7Smrg
163835d5b7c7Smrgcommit 103bd6f44cc5f1a6cd6cc9a5cb34d0419c4cece9
163935d5b7c7SmrgAuthor: Slava Grigorev <slava.grigorev@amd.com>
164035d5b7c7SmrgDate:   Fri Apr 27 13:04:36 2018 -0400
164135d5b7c7Smrg
164235d5b7c7Smrg    Include xf86platformBus.h unconditionally
164335d5b7c7Smrg    
164435d5b7c7Smrg    Compilation failed with XSERVER_PLATFORM_BUS undefined:
164535d5b7c7Smrg    
164635d5b7c7Smrg    ../../src/amdgpu_probe.c: In function ‘amdgpu_kernel_open_fd’:
164735d5b7c7Smrg    ../../src/amdgpu_probe.c:133:21: error: dereferencing pointer to incomplete type ‘struct xf86_platform_device’
164835d5b7c7Smrg       dev = platform_dev->pdev;
164935d5b7c7Smrg                         ^~
165035d5b7c7Smrg    
165135d5b7c7Smrg    Signed-off-by: Slava Grigorev <slava.grigorev@amd.com>
165235d5b7c7Smrg    
165335d5b7c7Smrg    [ Michel Dänzer:
165435d5b7c7Smrg      * Fixed remaining preprocessor guards to work with xserver 1.13
165535d5b7c7Smrg      * Touched up commit log ]
165635d5b7c7Smrg
165735d5b7c7Smrgcommit 04947b83cce3a7782e59dece2c7797cc396c1e05
165835d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
165935d5b7c7SmrgDate:   Thu Apr 26 17:58:08 2018 +0200
166035d5b7c7Smrg
166135d5b7c7Smrg    Wait for pending flips in drmmode_output_set_tear_free
166235d5b7c7Smrg    
166335d5b7c7Smrg    This prevents a nested call to drmHandleEvent, which would hang.
166435d5b7c7Smrg    
166535d5b7c7Smrg    Fixes hangs when disabling TearFree on a CRTC while a DRI3 client is
166635d5b7c7Smrg    page flipping.
166735d5b7c7Smrg    
166835d5b7c7Smrg    Reviewed-by: Samuel Li <Samuel.Li@amd.com>
166935d5b7c7Smrg
167035d5b7c7Smrgcommit fa30f4601de7a44edfb4a95873bd648946fd4292
167135d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
167235d5b7c7SmrgDate:   Thu Apr 26 17:55:30 2018 +0200
167335d5b7c7Smrg
167435d5b7c7Smrg    Refactor drmmode_output_set_tear_free helper
167535d5b7c7Smrg    
167635d5b7c7Smrg    Preparation for the following fix, no functional change intended.
167735d5b7c7Smrg    
167835d5b7c7Smrg    Reviewed-by: Samuel Li <Samuel.Li@amd.com>
167935d5b7c7Smrg
168035d5b7c7Smrgcommit 7db0c8e9d7586cff4312d4b93684d35de3e6376f
168135d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
168235d5b7c7SmrgDate:   Tue Apr 24 11:56:03 2018 +0200
168335d5b7c7Smrg
168435d5b7c7Smrg    Set drmmode_crtc->scanout_id = 0 when TearFree is disabled
168535d5b7c7Smrg    
168635d5b7c7Smrg    When disabling TearFree, drmmode_crtc->scanout_id could remain as 1,
168735d5b7c7Smrg    but drmmode_set_mode_major would destroy drmmode_crtc->scanout[1], so
168835d5b7c7Smrg    scanout_do_update() would keep bailing, and the scanout buffer would
168935d5b7c7Smrg    stop being updated.
169035d5b7c7Smrg    
169135d5b7c7Smrg    Fixes freeze after disabling TearFree on a CRTC with active RandR
169235d5b7c7Smrg    rotation or other transform.
169335d5b7c7Smrg    
169435d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
169535d5b7c7Smrg
169635d5b7c7Smrgcommit 8e544b4a0de6717feb4abf00052d57c5b726b5ce
169735d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
169835d5b7c7SmrgDate:   Mon Apr 23 18:52:02 2018 +0200
169935d5b7c7Smrg
170035d5b7c7Smrg    Simplify drmmode_handle_transform
170135d5b7c7Smrg    
170235d5b7c7Smrg    Set crtc->driverIsPerformingTransform for any case we can handle before
170335d5b7c7Smrg    calling xf86CrtcRotate. We already clear it afterwards when the latter
170435d5b7c7Smrg    clears crtc->transform_in_use.
170535d5b7c7Smrg    
170635d5b7c7Smrg    This should allow our separate scanout buffer mechanism to be used in
170735d5b7c7Smrg    more cases.
170835d5b7c7Smrg    
170935d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
171035d5b7c7Smrg
171135d5b7c7Smrgcommit 463477661c88cab3a87746499e5838c5b9f9a13b
171235d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
171335d5b7c7SmrgDate:   Mon Apr 23 18:44:06 2018 +0200
171435d5b7c7Smrg
171535d5b7c7Smrg    Don't call scanout_flip/update with a legacy RandR scanout buffer
171635d5b7c7Smrg    
171735d5b7c7Smrg    It means we are not using our own scanout buffers.
171835d5b7c7Smrg    
171935d5b7c7Smrg    Fixes crash when TearFree is supposed to be enabled, but
172035d5b7c7Smrg    drmmode_handle_transform doesn't set crtc->driverIsPerformingTransform.
172135d5b7c7Smrg    
172235d5b7c7Smrg    Bugzilla: https://bugs.freedesktop.org/105736
172335d5b7c7Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
172435d5b7c7Smrg
172535d5b7c7Smrgcommit 72c3e9c7308fbcdf85708b72f9be14a5f2f8e7b5
172635d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
172735d5b7c7SmrgDate:   Thu Mar 8 19:07:21 2018 +0100
172835d5b7c7Smrg
172935d5b7c7Smrg    Simplify drmmode_crtc_scanout_update
173035d5b7c7Smrg    
173135d5b7c7Smrg    Use our own BoxRec for the extents, and RegionEmpty for clearing the
173235d5b7c7Smrg    scanout damage region.
173335d5b7c7Smrg
173435d5b7c7Smrgcommit 4dcda0b48d62944c841cd9540f4ad4c7ac8dee47
173535d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
173635d5b7c7SmrgDate:   Fri Apr 20 17:34:55 2018 +0200
173735d5b7c7Smrg
173835d5b7c7Smrg    Update RandR CRTC state if set_mode_major fails in set_desired_modes
173935d5b7c7Smrg    
174035d5b7c7Smrg    Without this, RandR would report the CRTC and its outputs as enabled,
174135d5b7c7Smrg    even though they were actually off due to the failure.
174235d5b7c7Smrg
174335d5b7c7Smrgcommit 36d01989cd842588f12fdae5b2cba5fdcf9c91dd
174435d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
174535d5b7c7SmrgDate:   Wed Apr 18 11:17:02 2018 +0200
174635d5b7c7Smrg
174735d5b7c7Smrg    Abort scanout_update_pending event when possible
174835d5b7c7Smrg    
174935d5b7c7Smrg    We don't need to wait for a non-TearFree scanout update before scanning
175035d5b7c7Smrg    out from the screen pixmap or before flipping, as the scanout update
175135d5b7c7Smrg    won't be visible anyway. Instead, just abort it.
175235d5b7c7Smrg
175335d5b7c7Smrgcommit 04a5c5f7cfacad8d9ccffe81e388cc3da2036cb5
175435d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
175535d5b7c7SmrgDate:   Wed Apr 18 11:03:14 2018 +0200
175635d5b7c7Smrg
175735d5b7c7Smrg    Track DRM event queue sequence number in scanout_update_pending
175835d5b7c7Smrg    
175935d5b7c7Smrg    Preparation for next change, no behaviour change intended.
176035d5b7c7Smrg
176135d5b7c7Smrgcommit 8fcc3a9b43d3907052a83a96e5a2423afab5ad3f
176235d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
176335d5b7c7SmrgDate:   Wed Apr 18 11:18:59 2018 +0200
176435d5b7c7Smrg
176535d5b7c7Smrg    Ignore AMDGPU_DRM_QUEUE_ERROR (0) in amdgpu_drm_abort_entry
176635d5b7c7Smrg    
176735d5b7c7Smrg    This allows a following change to be slightly simpler.
176835d5b7c7Smrg
176935d5b7c7Smrgcommit 720a61000aeb139005bd8125908cec66a6e69554
177035d5b7c7SmrgAuthor: Emil Velikov <emil.velikov@collabora.com>
177135d5b7c7SmrgDate:   Wed Apr 4 15:29:51 2018 +0100
177235d5b7c7Smrg
177335d5b7c7Smrg    Remove set but unused amdgpu_dri2::pKernelDRMVersion
177435d5b7c7Smrg    
177535d5b7c7Smrg    Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
177635d5b7c7Smrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
177735d5b7c7Smrg
177835d5b7c7Smrgcommit 7fb8b49895e225b3908c8bd186539de23afe91d1
177935d5b7c7SmrgAuthor: Emil Velikov <emil.velikov@collabora.com>
178035d5b7c7SmrgDate:   Wed Apr 4 15:29:50 2018 +0100
178135d5b7c7Smrg
178235d5b7c7Smrg    Do not export the DriverRec AMDGPU
178335d5b7c7Smrg    
178435d5b7c7Smrg    Unused externally and should not be exported.
178535d5b7c7Smrg    
178635d5b7c7Smrg    Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
178735d5b7c7Smrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
178835d5b7c7Smrg
178935d5b7c7Smrgcommit 00c128b45fc196c3a3a788ddb4453e7521be5860
179035d5b7c7SmrgAuthor: Emil Velikov <emil.velikov@collabora.com>
179135d5b7c7SmrgDate:   Wed Apr 4 15:29:36 2018 +0100
179235d5b7c7Smrg
179335d5b7c7Smrg    Move amdgpu_bus_id/amgpu_kernel_mode within amdgpu_kernel_open_fd
179435d5b7c7Smrg    
179535d5b7c7Smrg    Small step towards unifying the code paths and removing a handful of
179635d5b7c7Smrg    duplication.
179735d5b7c7Smrg    
179835d5b7c7Smrg    Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
179935d5b7c7Smrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
180035d5b7c7Smrg
180135d5b7c7Smrgcommit 9f6a8905611b5b1d8fcd31bebbc9af7ca1355cc3
180235d5b7c7SmrgAuthor: Jim Qu <Jim.Qu@amd.com>
180335d5b7c7SmrgDate:   Tue Apr 17 19:11:16 2018 +0800
180435d5b7c7Smrg
180535d5b7c7Smrg    Wait for pending scanout update before calling drmmode_crtc_scanout_free
180635d5b7c7Smrg    
180735d5b7c7Smrg    There is a case that when set screen from reverse to normal, the old
180835d5b7c7Smrg    scanout damage is freed in modesetting before scanout update handler,
180935d5b7c7Smrg    so it causes segment fault issue.
181035d5b7c7Smrg    
181135d5b7c7Smrg    Signed-off-by: Jim Qu <Jim.Qu@amd.com>
181235d5b7c7Smrg    
181335d5b7c7Smrg    [ Michel Dänzer: Only call drmmode_crtc_wait_pending_event before
181435d5b7c7Smrg      drmmode_crtc_scanout_free is actually called, slightly tweak commit
181535d5b7c7Smrg      message ]
181635d5b7c7Smrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
181735d5b7c7Smrg
181835d5b7c7Smrgcommit c6f1559eba551a5a3bf374c7e7e875928f3b138d
181935d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
182035d5b7c7SmrgDate:   Wed Apr 18 10:41:46 2018 +0200
182135d5b7c7Smrg
182235d5b7c7Smrg    Post-release version bump
182335d5b7c7Smrg
182435d5b7c7Smrgcommit 9f37a44473ded8c669897379acbc750362c15ec6
182535d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
182635d5b7c7SmrgDate:   Thu Mar 15 16:34:19 2018 +0100
182735d5b7c7Smrg
182835d5b7c7Smrg    Bump version for 18.0.1 release
182935d5b7c7Smrg
183035d5b7c7Smrgcommit 8af989546907ad9fb491d940e1936d3bfc89276b
183135d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
183235d5b7c7SmrgDate:   Thu Mar 8 18:48:28 2018 +0100
183335d5b7c7Smrg
183435d5b7c7Smrg    Pass extents to amdgpu_scanout_do_update by value
183535d5b7c7Smrg    
183635d5b7c7Smrg    amdgpu_scanout_extents_intersect could leave the scanout damage region
183735d5b7c7Smrg    in an invalid state, triggering debugging checks in pixman:
183835d5b7c7Smrg    
183935d5b7c7Smrg    *** BUG ***
184035d5b7c7Smrg    In pixman_region_append_non_o: The expression r->x1 < r->x2 was false
184135d5b7c7Smrg    Set a breakpoint on '_pixman_log_error' to debug
184235d5b7c7Smrg
184335d5b7c7Smrgcommit 29649652a08ece7e07741be161b067a4484455ca
184435d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
184535d5b7c7SmrgDate:   Wed Mar 7 17:51:25 2018 +0100
184635d5b7c7Smrg
184735d5b7c7Smrg    Wrap the whole miPointerScreenFuncRec, instead of only Set/MoveCursor
184835d5b7c7Smrg    
184935d5b7c7Smrg    We were clobbering entries in mi's global miSpritePointerFuncs struct,
185035d5b7c7Smrg    which cannot work correctly with multiple primary screens. Instead,
185135d5b7c7Smrg    assign a pointer to our own wrapper struct to PointPriv->spriteFuncs.
185235d5b7c7Smrg    
185335d5b7c7Smrg    Fixes crashes with multiple primary screens.
185435d5b7c7Smrg    
185535d5b7c7Smrg    Fixes: 69e20839bfeb ("Keep track of how many SW cursors are visible on
185635d5b7c7Smrg                          each screen")
185735d5b7c7Smrg    Reported-by: Mario Kleiner <mario.kleiner.de@gmail.com>
185835d5b7c7Smrg
185935d5b7c7Smrgcommit b4a28bdcfa7089e1cf708490ddf048b7df4c7eed
186035d5b7c7SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
186135d5b7c7SmrgDate:   Tue Mar 6 17:59:26 2018 +0100
186235d5b7c7Smrg
186335d5b7c7Smrg    Only change Set/MoveCursor hooks from what we expect
186435d5b7c7Smrg    
186535d5b7c7Smrg    Since xf86CursorCloseScreen runs after AMDGPUCloseScreen_KMS,
186635d5b7c7Smrg    PointPriv->spriteFuncs doesn't point to the same struct in the latter as
186735d5b7c7Smrg    in AMDGPUCursorInit_KMS. So we were restoring info->Set/MoveCursor to
186835d5b7c7Smrg    the wrong struct. Then in the next server generation,
186935d5b7c7Smrg    info->Set/MoveCursor would end up pointing to
187035d5b7c7Smrg    drmmode_sprite_set/move_cursor, resulting in an infinite loop if one of
187135d5b7c7Smrg    them was called.
187235d5b7c7Smrg    
187335d5b7c7Smrg    To avoid this, only change the Set/MoveCursor hooks if their values
187435d5b7c7Smrg    match our expectations, otherwise leave them as is. This is kind of a
187535d5b7c7Smrg    hack, but the alternative would be invasive and thus risky changes to
187635d5b7c7Smrg    the way we're wrapping CloseScreen, and it's not even clear that can
187735d5b7c7Smrg    work without changing xserver code.
187835d5b7c7Smrg    
187935d5b7c7Smrg    Fixes: 69e20839bfeb ("Keep track of how many SW cursors are visible on
188035d5b7c7Smrg                          each screen")
188135d5b7c7Smrg    (Ported from radeon commit 504b8721b17a672caf1ed3eab087027c02458cab)
188235d5b7c7Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
188335d5b7c7Smrg
188424b90cf4Smrgcommit 5cfba7b6221779832be915993765cb128a561087
188524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
188624b90cf4SmrgDate:   Fri Mar 2 18:10:40 2018 +0100
188724b90cf4Smrg
188824b90cf4Smrg    Bump version for 18.0.0 release
188924b90cf4Smrg
189024b90cf4Smrgcommit 374cb8fef4fdbb648af089ee80803ec78321f1b2
189124b90cf4SmrgAuthor: Keith Packard <keithp@keithp.com>
189224b90cf4SmrgDate:   Thu Dec 21 18:54:34 2017 -0800
189324b90cf4Smrg
189424b90cf4Smrg    modesetting: Update property values at detect and uevent time
189524b90cf4Smrg    
189624b90cf4Smrg    We were updating the link-status property when a uevent came in, but
189724b90cf4Smrg    we also want to update the non-desktop property, and potentially
189824b90cf4Smrg    others as well. We also want to check at detect time in case we don't
189924b90cf4Smrg    get a hotplug event.
190024b90cf4Smrg    
190124b90cf4Smrg    This patch updates every property provided by the kernel, sending
190224b90cf4Smrg    changes to DIX so it can track things as well.
190324b90cf4Smrg    
190424b90cf4Smrg    Signed-off-by: Keith Packard <keithp@keithp.com>
190524b90cf4Smrg    
190624b90cf4Smrg    (Ported from xserver commit a12485ed846b852ca14d17d1e58c8b0f2399e577,
190724b90cf4Smrg     slightly modifying logic to reduce indentation depth)
190824b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
190924b90cf4Smrg
191024b90cf4Smrgcommit 10054b6c3d9a755b30abb43020121b9631fa296d
191124b90cf4SmrgAuthor: Daniel Martin <consume.noise@gmail.com>
191224b90cf4SmrgDate:   Mon Nov 20 10:47:41 2017 +0100
191324b90cf4Smrg
191424b90cf4Smrg    modesetting: Reset output_id if drmModeGetConnector failed
191524b90cf4Smrg    
191624b90cf4Smrg    If drmModeGetConnector() fails in drmmode_output_detect(), we have to
191724b90cf4Smrg    reset the output_id to -1 too.
191824b90cf4Smrg    
191924b90cf4Smrg    Yet another spot leading to a potential NULL dereference when handling
192024b90cf4Smrg    the mode_output member as output_id was != -1. Though, this case should
192124b90cf4Smrg    be very hard to hit.
192224b90cf4Smrg    
192324b90cf4Smrg    Signed-off-by: Daniel Martin <consume.noise@gmail.com>
192424b90cf4Smrg    
192524b90cf4Smrg    (Ported from xserver commit 6804875662363764683a86c1614e4cf3cc70a20a)
192624b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
192724b90cf4Smrg
192824b90cf4Smrgcommit fb58e06acd6c6bd59de2dbdadbca27eb1dd0025b
192924b90cf4SmrgAuthor: Daniel Martin <consume.noise@gmail.com>
193024b90cf4SmrgDate:   Mon Oct 23 10:31:21 2017 +0200
193124b90cf4Smrg
193224b90cf4Smrg    modesetting: Use helper to fetch drmModeProperty(Blob)s
193324b90cf4Smrg    
193424b90cf4Smrg    Replace the various loops to lookup drmModeProperty(Blob)s by
193524b90cf4Smrg    introducing helper functions.
193624b90cf4Smrg    
193724b90cf4Smrg    Signed-off-by: Daniel Martin <consume.noise@gmail.com>
193824b90cf4Smrg    
193924b90cf4Smrg    (Ported from xserver commit f44935cdb7321af242ce9f242975f096807b97f7)
194024b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
194124b90cf4Smrg
194224b90cf4Smrgcommit 7854ace03f12207600ec8159ef8b2c5a562c4aee
194324b90cf4SmrgAuthor: Christoph Haag <haagch@frickel.club>
194424b90cf4SmrgDate:   Thu Mar 1 15:07:00 2018 +0100
194524b90cf4Smrg
194624b90cf4Smrg    fix include order for present.h configure test
194724b90cf4Smrg    
194824b90cf4Smrg    xorg-server.h defines _XSERVER64 which is used in X.h to choose the
194924b90cf4Smrg    correct definition of XID
195024b90cf4Smrg    
195124b90cf4Smrg    this prevents a failure in the present.h configure test that disables
195224b90cf4Smrg    DRI3 on X.Org 1.20
195324b90cf4Smrg    
195424b90cf4Smrg    Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
195524b90cf4Smrg
195624b90cf4Smrgcommit e3aae7a24296f640c0153d1459f3e0820485468a
195724b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
195824b90cf4SmrgDate:   Fri Feb 16 17:15:24 2018 +0100
195924b90cf4Smrg
196024b90cf4Smrg    Disable all unused CRTCs before setting desired modes
196124b90cf4Smrg    
196224b90cf4Smrg    This might avoid modeset failures in some cases where a CRTC which isn't
196324b90cf4Smrg    used by Xorg was enabled before.
196424b90cf4Smrg
196524b90cf4Smrgcommit f5ac5f385f41d1547cfd7ccc8bb35a537a8fffeb
196624b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
196724b90cf4SmrgDate:   Thu Feb 15 18:37:09 2018 +0100
196824b90cf4Smrg
196924b90cf4Smrg    Don't bail from drmmode_set_desired_modes immediately
197024b90cf4Smrg    
197124b90cf4Smrg    If we fail to find or set the mode for a CRTC, keep trying for the
197224b90cf4Smrg    remaining CRTCs, and only return FALSE if we failed for all CRTCs that
197324b90cf4Smrg    should be on.
197424b90cf4Smrg    
197524b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
197624b90cf4Smrg    Acked-by: Harry Wentland <harry.wentland@amd.com>
197724b90cf4Smrg
197824b90cf4Smrgcommit 37c7260bdef3a53b0f0295a531f33938e9aad8cf
197924b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
198024b90cf4SmrgDate:   Wed Feb 14 19:06:33 2018 +0100
198124b90cf4Smrg
198224b90cf4Smrg    If glamor is too old for depth 30, fall back to ShadowFB
198324b90cf4Smrg    
198424b90cf4Smrg    Instead of not starting up at all.
198524b90cf4Smrg    
198624b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
198724b90cf4Smrg
198824b90cf4Smrgcommit 63b0c73a99fdf0eb7550a88df3a0052ce784e758
198924b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
199024b90cf4SmrgDate:   Wed Feb 14 18:50:18 2018 +0100
199124b90cf4Smrg
199224b90cf4Smrg    Revert "Guard against pAMDGPUEnt == NULL in AMDGPUFreeRec"
199324b90cf4Smrg    
199424b90cf4Smrg    This reverts commit a23d1ff700d486138c624c2023d8d251c73709af.
199524b90cf4Smrg    
199624b90cf4Smrg    pAMDGPUEnt cannot be NULL anymore here now that we no longer call
199724b90cf4Smrg    AMDGPUFreeRec directly from AMDGPUPreInit_KMS.
199824b90cf4Smrg    
199924b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
200024b90cf4Smrg
200124b90cf4Smrgcommit 103b7285845b786929fb509083c57e074c48f9be
200224b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
200324b90cf4SmrgDate:   Tue Feb 13 19:11:00 2018 +0100
200424b90cf4Smrg
200524b90cf4Smrg    Don't call AMDGPUFreeRec from AMDGPUPreInit_KMS
200624b90cf4Smrg    
200724b90cf4Smrg    If the latter fails, Xorg will call AMDGPUFreeScreen_KMS, which calls
200824b90cf4Smrg    the former.
200924b90cf4Smrg    
201024b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
201124b90cf4Smrg
201224b90cf4Smrgcommit a23d1ff700d486138c624c2023d8d251c73709af
201324b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
201424b90cf4SmrgDate:   Tue Feb 13 18:57:48 2018 +0100
201524b90cf4Smrg
201624b90cf4Smrg    Guard against pAMDGPUEnt == NULL in AMDGPUFreeRec
201724b90cf4Smrg    
201824b90cf4Smrg    This can happen if PreInit fails early.
201924b90cf4Smrg    
202024b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
202124b90cf4Smrg
202224b90cf4Smrgcommit b3095710b7c240ddefce794033a77033806f639d
202324b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
202424b90cf4SmrgDate:   Tue Feb 13 18:26:06 2018 +0100
202524b90cf4Smrg
202624b90cf4Smrg    Always use screen depth/bpp for KMS framebuffers
202724b90cf4Smrg    
202824b90cf4Smrg    DRI clients can use depth 32 pixmaps while the screen is depth 24, in
202924b90cf4Smrg    which case page flipping would fail.
203024b90cf4Smrg    
203124b90cf4Smrg    Reported-by: Mario Kleiner <mario.kleiner.de@gmail.com>
203224b90cf4Smrg    (Ported from radeon commit 733f606dd6ca8350e6e7f0858bfff5454ddc98ed)
203324b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
203424b90cf4Smrg
203524b90cf4Smrgcommit 6aee5770fb913713bb1b9a1af8f0d0892a66f21a
203624b90cf4SmrgAuthor: Hawking Zhang <Hawking.Zhang@amd.com>
203724b90cf4SmrgDate:   Sat Jul 16 00:09:21 2016 +0800
203824b90cf4Smrg
203924b90cf4Smrg    Add 30bit RGB color format support
204024b90cf4Smrg    
204124b90cf4Smrg    Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
204224b90cf4Smrg    
204324b90cf4Smrg    [ Michel Dänzer:
204424b90cf4Smrg    * Require Xorg >= 1.19.99.1 for depth 30, otherwise it can't work with glamor
204524b90cf4Smrg    * Update manpage, per radeon commit
204624b90cf4Smrg      574bfab4bf1fcd95163a8f33cea2889189429d30 ]
204724b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
204824b90cf4Smrg
204924b90cf4Smrgcommit ec397f7d3bfc89a5d8b8429c96e1b9572f6ee47d
205024b90cf4SmrgAuthor: Qiang Yu <Qiang.Yu@amd.com>
205124b90cf4SmrgDate:   Thu Nov 2 14:00:23 2017 +0800
205224b90cf4Smrg
205324b90cf4Smrg    Disable gamma set when deep color
205424b90cf4Smrg    
205524b90cf4Smrg    gamma set is disabled in kernel driver when deep color.
205624b90cf4Smrg    Enable it will confuse the user.
205724b90cf4Smrg    
205824b90cf4Smrg    Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
205924b90cf4Smrg    
206024b90cf4Smrg    [ Michel Dänzer: Align drmmode_pre_init change with radeon commit
206124b90cf4Smrg      1f1d4b1fa7d4b22dd8553f7e71251bf17ca7a7b1 ]
206224b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
206324b90cf4Smrg
206424b90cf4Smrgcommit c849081e24377a81afc1a05f2a5634b1e60c67db
206524b90cf4SmrgAuthor: Mario Kleiner <mario.kleiner.de@gmail.com>
206624b90cf4SmrgDate:   Mon Feb 12 18:18:46 2018 +0100
206724b90cf4Smrg
206824b90cf4Smrg    Define per x-screen individual drmmode_crtc_funcs
206924b90cf4Smrg    
207024b90cf4Smrg    This allows to en-/disable some functions depending on individual screen
207124b90cf4Smrg    settings.
207224b90cf4Smrg    
207324b90cf4Smrg    Prep work for more efficient depth 30 support.
207424b90cf4Smrg    
207524b90cf4Smrg    Suggested-by: Michel Dänzer <michel.daenzer@amd.com>
207624b90cf4Smrg    Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
207724b90cf4Smrg    (Ported from radeon commit 21f6753462464acfd3c452393328c977a375ce26)
207824b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
207924b90cf4Smrg
208024b90cf4Smrgcommit 348023cea43e0474352df0c2aa6345eb0b25c2f7
208124b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
208224b90cf4SmrgDate:   Mon Jan 22 18:23:18 2018 +0100
208324b90cf4Smrg
208424b90cf4Smrg    Fix linear check in amdgpu_glamor_share_pixmap_backing
208524b90cf4Smrg    
208624b90cf4Smrg    We were incorrectly interpreting the tiling information.
208724b90cf4Smrg    
208824b90cf4Smrg    Reported-by: Marek Olšák <marek.olsak@amd.com>
208924b90cf4Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
209024b90cf4Smrg    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
209124b90cf4Smrg
209224b90cf4Smrgcommit 69e20839bfeb3ee0b0a732d72de0a32d6c5435fc
209324b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
209424b90cf4SmrgDate:   Fri Dec 22 18:33:58 2017 +0100
209524b90cf4Smrg
209624b90cf4Smrg    Keep track of how many SW cursors are visible on each screen
209724b90cf4Smrg    
209824b90cf4Smrg    And use this to determine when we cannot use page flipping for DRI
209924b90cf4Smrg    clients. We previously did this based on whether the HW cursor cannot
210024b90cf4Smrg    be used on at least one CRTC, which had at least two issues:
210124b90cf4Smrg    
210224b90cf4Smrg    * Even while the HW cursor cannot be used, no SW cursor may actually be
210324b90cf4Smrg      visible (e.g. because all cursors are disabled), in which case we can
210424b90cf4Smrg      use page flipping for DRI clients anyway
210524b90cf4Smrg    * Even while the HW cursor can be used, there may be SW cursors visible
210624b90cf4Smrg      from non-core pointer devices, in which case we cannot use page
210724b90cf4Smrg      flipping for DRI clients anyway
210824b90cf4Smrg    
210924b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
211024b90cf4Smrg
211124b90cf4Smrgcommit dfccaa7043ccb157a1f8be7313123792bb7e7001
211224b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
211324b90cf4SmrgDate:   Fri Dec 22 17:09:07 2017 +0100
211424b90cf4Smrg
211524b90cf4Smrg    Move cursor related ScreenInit calls into AMDGPUCursorInit_KMS
211624b90cf4Smrg    
211724b90cf4Smrg    And bail if xf86_cursors_init fails.
211824b90cf4Smrg    
211924b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
212024b90cf4Smrg
212124b90cf4Smrgcommit 1d65ac395971571094df21ca0408d5972c6b56ec
212224b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
212324b90cf4SmrgDate:   Wed Nov 15 18:22:27 2017 +0100
212424b90cf4Smrg
212524b90cf4Smrg    Add amdgpu_dirty_src_drawable helper
212624b90cf4Smrg    
212724b90cf4Smrg    Allows tidying up amdgpu_dirty_src_equals and redisplay_dirty slightly.
212824b90cf4Smrg    
212924b90cf4Smrg    v2:
213024b90cf4Smrg    * Different approach for amdgpu_dirty_master
213124b90cf4Smrg    
213224b90cf4Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
213324b90cf4Smrg
213424b90cf4Smrgcommit 3a4f7422913093ed9e26b73ecd7f9e773478cb1e
213524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
213624b90cf4SmrgDate:   Wed Nov 8 18:44:25 2017 +0100
213724b90cf4Smrg
213824b90cf4Smrg    Use correct ScrnInfoPtr in redisplay_dirty
213924b90cf4Smrg    
214024b90cf4Smrg    We used the destination pixmap's screen for flushing glamor. But when
214124b90cf4Smrg    we are the master screen, the destination pixmap is from the slave
214224b90cf4Smrg    screen.
214324b90cf4Smrg    
214424b90cf4Smrg    Fixes crash when the slave screen isn't using glamor as well.
214524b90cf4Smrg    
214624b90cf4Smrg    Bugzilla: https://bugs.freedesktop.org/103613
214724b90cf4Smrg    Fixes: e15b23663cd1 ("Adapt to PixmapDirtyUpdateRec::src being a
214824b90cf4Smrg                         DrawablePtr")
214924b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
215024b90cf4Smrg
215124b90cf4Smrgcommit 875339c1064f666a2391b4a5a495eddda9407ab6
215224b90cf4SmrgAuthor: Daniel Martin <consume.noise@gmail.com>
215324b90cf4SmrgDate:   Fri Oct 20 10:05:35 2017 +0200
215424b90cf4Smrg
215524b90cf4Smrg    modesetting: Check crtc before searching link-status property
215624b90cf4Smrg    
215724b90cf4Smrg    No need to lookup the link-status property if we don't have a crtc.
215824b90cf4Smrg    
215924b90cf4Smrg    Signed-off-by: Daniel Martin <consume.noise@gmail.com>
216024b90cf4Smrg    (Ported from xserver commit 8d7f7e24261e68459e6f0a865e243473f65fe7ad)
216124b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
216224b90cf4Smrg
216324b90cf4Smrgcommit 91cd0ceab2cabba75e3552d0fbfcfc55f6d132ee
216424b90cf4SmrgAuthor: Keith Packard <keithp@keithp.com>
216524b90cf4SmrgDate:   Mon Sep 25 16:18:22 2017 -0700
216624b90cf4Smrg
216724b90cf4Smrg    modesetting: Skip no-longer-present connectors when resetting BAD links
216824b90cf4Smrg    
216924b90cf4Smrg    Outputs may have NULL mode_output (connector) pointers if the
217024b90cf4Smrg    connector disappears while the server is running. Skip these when
217124b90cf4Smrg    resetting outputs with BAD link status.
217224b90cf4Smrg    
217324b90cf4Smrg    (Ported from xserver commit 37f4e7651a2fd51efa613a08a1e705553be33e76)
217424b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
217524b90cf4Smrg
217624b90cf4Smrgcommit f6b39bcd45cb06976ba8a3600df77fc471c63995
217724b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
217824b90cf4SmrgDate:   Thu Oct 19 18:02:05 2017 +0200
217924b90cf4Smrg
218024b90cf4Smrg    Always call drmModeFreeProperty after drmModeGetProperty
218124b90cf4Smrg    
218224b90cf4Smrg    We were not doing so in all cases, leaking memory allocated by the
218324b90cf4Smrg    latter.
218424b90cf4Smrg    
218524b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
218624b90cf4Smrg
218724b90cf4Smrgcommit 84aad09f18fed6b52b0c073f0bbd675a6de07807
218824b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
218924b90cf4SmrgDate:   Thu Oct 19 17:54:13 2017 +0200
219024b90cf4Smrg
219124b90cf4Smrg    Call TimerFree for timer created in LeaveVT
219224b90cf4Smrg    
219324b90cf4Smrg    We were leaking the memory allocated by TimerSet.
219424b90cf4Smrg    
219524b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
219624b90cf4Smrg
219724b90cf4Smrgcommit cfccf4c4e7e5c73fe4040fabeb1b43283cf29b33
219824b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
219924b90cf4SmrgDate:   Thu Oct 19 17:41:44 2017 +0200
220024b90cf4Smrg
220124b90cf4Smrg    Free memory returned by xf86GetEntityInfo
220224b90cf4Smrg    
220324b90cf4Smrg    We were leaking it.
220424b90cf4Smrg    
220524b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
220624b90cf4Smrg
220724b90cf4Smrgcommit 9d84934309e4ccd9a43c73d958b8ff10ef2fc990
220824b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
220924b90cf4SmrgDate:   Thu Oct 19 17:28:53 2017 +0200
221024b90cf4Smrg
221124b90cf4Smrg    Free pAMDGPUEnt memory in AMDGPUFreeRec
221224b90cf4Smrg    
221324b90cf4Smrg    We were freeing it earlier but then still trying to access it in
221424b90cf4Smrg    AMDGPUFreeRec.
221524b90cf4Smrg    
221624b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
221724b90cf4Smrg
221824b90cf4Smrgcommit b67a2b62b20c17db7471f5bbea591ab55806cb29
221924b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
222024b90cf4SmrgDate:   Thu Oct 19 16:46:35 2017 +0200
222124b90cf4Smrg
222224b90cf4Smrg    Bail if there's a problem with ShadowFB
222324b90cf4Smrg    
222424b90cf4Smrg    If we hit a problem while setting up ShadowFB, just carrying on trying
222524b90cf4Smrg    to set up HW acceleration instead is unlikely to work.
222624b90cf4Smrg    
222724b90cf4Smrg    (Ported from radeon commit 7d435354099119234d443b07e2df1c7b9f97cf3c)
222824b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
222924b90cf4Smrg
223024b90cf4Smrgcommit 55396cc45c9aae3b1985ced1044b6b93064667c3
223124b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
223224b90cf4SmrgDate:   Thu Oct 19 16:20:03 2017 +0200
223324b90cf4Smrg
223424b90cf4Smrg    Fix VT switching with ShadowFB
223524b90cf4Smrg    
223624b90cf4Smrg    We were trying to call acceleration specific functions from LeaveVT.
223724b90cf4Smrg    Instead, memset the scanout buffer to all 0 in LeaveVT and allocate a
223824b90cf4Smrg    new one in EnterVT.
223924b90cf4Smrg    
224024b90cf4Smrg    Bugzilla: https://bugs.freedesktop.org/102948
224124b90cf4Smrg    Fixes: c16ff42f927d ("Make all active CRTCs scan out an all-black
224224b90cf4Smrg                          framebuffer in LeaveVT")
224324b90cf4Smrg    (Ported from radeon commit 34da04daec82077571558ac3fe1ec0c1203a01ad)
224424b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
224524b90cf4Smrg
224624b90cf4Smrgcommit 2f72be038d22c54620e436af30121dd89f79a003
224724b90cf4SmrgAuthor: Darren Salt <devspam@moreofthesa.me.uk>
224824b90cf4SmrgDate:   Wed Sep 13 03:22:19 2017 +0100
224924b90cf4Smrg
225024b90cf4Smrg    Clarify when TearFree is automatically enabled.
225124b90cf4Smrg    
225224b90cf4Smrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
225324b90cf4Smrg
225424b90cf4Smrgcommit 2ce59dfa1c57655137fcc7ccdf15a341e51383ff
225524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
225624b90cf4SmrgDate:   Thu Oct 5 11:15:34 2017 +0200
225724b90cf4Smrg
225824b90cf4Smrg    Post-release version bump
225924b90cf4Smrg
226024b90cf4Smrgcommit cf1767a9a58a3ec95622a7b8ca661113e2148da9
226124b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
226224b90cf4SmrgDate:   Fri Sep 8 16:19:48 2017 +0900
226324b90cf4Smrg
226424b90cf4Smrg    Bump version for 1.4.0 release
226524b90cf4Smrg
226624b90cf4Smrgcommit 114de91e3548cd30b709b19f1447f597e71175e0
226724b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
226824b90cf4SmrgDate:   Thu Aug 31 17:59:08 2017 +0900
226924b90cf4Smrg
227024b90cf4Smrg    Require xserver >= 1.13
227124b90cf4Smrg    
227224b90cf4Smrg    xserver 1.13.0 was released on September 6th, 2012, almost 5 years ago.
227324b90cf4Smrg    
227424b90cf4Smrg    This allows cleaning up a bunch of backwards compatibility code.
227524b90cf4Smrg    
227624b90cf4Smrg    (Ported from radeon commit 5cdd334b3402c2431deb3a87a8d04ef590da53ee)
227724b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
227824b90cf4Smrg
227924b90cf4Smrgcommit 456e5841233a8a79c23ad13649bbdaf8428b50f3
228024b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
228124b90cf4SmrgDate:   Wed Aug 30 17:17:49 2017 +0900
228224b90cf4Smrg
228324b90cf4Smrg    Use a timer for unreferencing the all-black FB
228424b90cf4Smrg    
228524b90cf4Smrg    The timer fires 1 second after LeaveVT. This gives the next DRM master
228624b90cf4Smrg    enough time to set up scanout of its own buffers.
228724b90cf4Smrg    
228824b90cf4Smrg    Fixes prolonged intermittent black screen when switching from Xorg to
228924b90cf4Smrg    e.g. the GDM Wayland mode login VT.
229024b90cf4Smrg    
229124b90cf4Smrg    Fixes: c16ff42f927d ("Make all active CRTCs scan out an all-black
229224b90cf4Smrg                          framebuffer in LeaveVT")
229324b90cf4Smrg    (Ported from radeon commit 9d9c565c84601f4c6c73ad769f86491088683f7a)
229424b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
229524b90cf4Smrg
229624b90cf4Smrgcommit 639076efb06cdf13a211a8df1acb00c3908992b9
229724b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
229824b90cf4SmrgDate:   Tue Aug 29 17:24:18 2017 +0900
229924b90cf4Smrg
230024b90cf4Smrg    Remove drmmode_scanout_free
230124b90cf4Smrg    
230224b90cf4Smrg    Not used anymore.
230324b90cf4Smrg    
230424b90cf4Smrg    (Cherry picked from radeon commit e4a3df19d588a4310fcb889ef34e205d0e92e4d7)
230524b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
230624b90cf4Smrg
230724b90cf4Smrgcommit c16ff42f927df805619a5255bc383841474daff8
230824b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
230924b90cf4SmrgDate:   Tue Aug 29 17:06:58 2017 +0900
231024b90cf4Smrg
231124b90cf4Smrg    Make all active CRTCs scan out an all-black framebuffer in LeaveVT
231224b90cf4Smrg    
231324b90cf4Smrg    And destroy all other FBs. This is so that other DRM masters can only
231424b90cf4Smrg    get access to this all-black FB, not to any other FB we created, while
231524b90cf4Smrg    we're switched away and not DRM master.
231624b90cf4Smrg    
231724b90cf4Smrg    Fixes: b09fde0d81e0 ("Use reference counting for tracking KMS
231824b90cf4Smrg                          framebuffer lifetimes")
231924b90cf4Smrg    (Ported from radeon commit 06a465484101f21e99d3a0a62fb03440bcaff93e)
232024b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
232124b90cf4Smrg
232224b90cf4Smrgcommit 19672625df0531c12acc05999ea09ea763e5db59
232324b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
232424b90cf4SmrgDate:   Tue Aug 29 17:05:19 2017 +0900
232524b90cf4Smrg
232624b90cf4Smrg    Create amdgpu_master_screen helper
232724b90cf4Smrg    
232824b90cf4Smrg    Preparatory, no functional change intended yet.
232924b90cf4Smrg    
233024b90cf4Smrg    (Ported from radeon commit 7f0cd68d1b0c132e32ae736371bce3e12ed33c7a)
233124b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
233224b90cf4Smrg
233324b90cf4Smrgcommit 6b376c8d73b20c92755527edb0527a233886e4eb
233424b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
233524b90cf4SmrgDate:   Tue Aug 29 16:56:56 2017 +0900
233624b90cf4Smrg
233724b90cf4Smrg    Create amdgpu_pixmap_get_fb_ptr helper
233824b90cf4Smrg    
233924b90cf4Smrg    Preparatory, no functional change intended yet.
234024b90cf4Smrg    
234124b90cf4Smrg    Also inline amdgpu_pixmap_create_fb into amdgpu_pixmap_get_fb, since
234224b90cf4Smrg    there's only one call-site.
234324b90cf4Smrg    
234424b90cf4Smrg    (Ported from radeon commit 20f6b56fdb74d88086e8e094013fedbb14e50a24)
234524b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
234624b90cf4Smrg
234724b90cf4Smrgcommit 5af396253f6a03fa3f8f92e81da231dd581b50c9
234824b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
234924b90cf4SmrgDate:   Tue Aug 29 16:54:10 2017 +0900
235024b90cf4Smrg
235124b90cf4Smrg    Create drmmode_set_mode helper
235224b90cf4Smrg    
235324b90cf4Smrg    Preparatory, no functional change intended yet.
235424b90cf4Smrg    
235524b90cf4Smrg    (Ported from radeon commit 4bc992c31059eb50e22df4ebf5b92d08411f41ef)
235624b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
235724b90cf4Smrg
235824b90cf4Smrgcommit 1afd4a526c97e77ec882988e35d4977880b9d16c
235924b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
236024b90cf4SmrgDate:   Tue Aug 29 16:46:33 2017 +0900
236124b90cf4Smrg
236224b90cf4Smrg    Create amdgpu_pixmap_clear helper
236324b90cf4Smrg    
236424b90cf4Smrg    Preparatory, no functional change intended yet.
236524b90cf4Smrg    
236624b90cf4Smrg    (Ported from radeon commit 3f6210ca2c8ef60d59efc8139151d3b9838bb875)
236724b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
236824b90cf4Smrg
236924b90cf4Smrgcommit 0de05767adb79d417284dae83e9a77857633fd80
237024b90cf4SmrgAuthor: Martin Peres <martin.peres@linux.intel.com>
237124b90cf4SmrgDate:   Tue Aug 22 18:43:24 2017 +0900
237224b90cf4Smrg
237324b90cf4Smrg    modesetting: re-set the crtc's mode when link-status goes BAD
237424b90cf4Smrg    
237524b90cf4Smrg    Despite all the careful planning of the kernel, a link may become
237624b90cf4Smrg    insufficient to handle the currently-set mode. At this point, the
237724b90cf4Smrg    kernel should mark this particular configuration as being broken
237824b90cf4Smrg    and potentially prune the mode before setting the offending connector's
237924b90cf4Smrg    link-status to BAD and send the userspace a hotplug event. This may
238024b90cf4Smrg    happen right after a modeset or later on.
238124b90cf4Smrg    
238224b90cf4Smrg    Upon receiving a hot-plug event, we iterate through the connectors to
238324b90cf4Smrg    re-apply the currently-set mode on all the connectors that have a
238424b90cf4Smrg    link-status property set to BAD. The kernel may be able to get the
238524b90cf4Smrg    link to work by dropping to using a lower link bpp (with the same
238624b90cf4Smrg    display bpp). However, the modeset may fail if the kernel has pruned
238724b90cf4Smrg    the mode, so to make users aware of this problem a warning is outputed
238824b90cf4Smrg    in the logs to warn about having a potentially-black display.
238924b90cf4Smrg    
239024b90cf4Smrg    This patch does not modify the current behaviour of always propagating
239124b90cf4Smrg    the events to the randr clients. This allows desktop environments to
239224b90cf4Smrg    re-probe the connectors and select a new resolution based on the new
239324b90cf4Smrg    (currated) mode list if a mode disapeared. This behaviour is expected in
239424b90cf4Smrg    order to pass the Display Port compliance tests.
239524b90cf4Smrg    
239624b90cf4Smrg    (Ported from xserver commit bcee1b76aa0db8525b491485e90b8740763d7de6)
239724b90cf4Smrg    
239824b90cf4Smrg    [ Michel: Bump libdrm dependency to >= 2.4.78 for
239924b90cf4Smrg      DRM_MODE_LINK_STATUS_BAD ]
240024b90cf4Smrg    (Ported from radeon commit 0472a605e0ec8fec1892bbc3a84698b7ef9c5296)
240124b90cf4Smrg    Acked-by: Harry Wentland <harry.wentland@amd.com>
240224b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
240324b90cf4Smrg
240424b90cf4Smrgcommit a2ee5c36c7d4fdcd067fdc1ef424be474f1ad2cb
240524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
240624b90cf4SmrgDate:   Fri Aug 18 17:24:45 2017 +0900
240724b90cf4Smrg
240824b90cf4Smrg    Make amdgpu_scanout_do_update take a PixmapPtr instead of a DrawablePtr
240924b90cf4Smrg    
241024b90cf4Smrg    All callers were already passing in a pixmap.
241124b90cf4Smrg    
241224b90cf4Smrg    This allows simplifying the rotated scanout case slightly.
241324b90cf4Smrg    
241424b90cf4Smrg    (Ported from radeon commit d822a0f47070374ad0c1a97b559bae27724dc52a)
241524b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
241624b90cf4Smrg
241724b90cf4Smrgcommit 828fb44cf953f78bd65d8f391bdabe2b1b3d53ae
241824b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
241924b90cf4SmrgDate:   Fri Aug 18 17:22:12 2017 +0900
242024b90cf4Smrg
242124b90cf4Smrg    Use xorg_list_append for the DRM event list
242224b90cf4Smrg    
242324b90cf4Smrg    We were adding entries at the start of the list, i.e. the list was
242424b90cf4Smrg    ordered from most recently added to least recently added. However, the
242524b90cf4Smrg    corresponding DRM events are generally expected to arrive in the same
242624b90cf4Smrg    order as they are queued, which means that amdgpu_drm_queue_alloc would
242724b90cf4Smrg    generally have to traverse the whole list to find the entry
242824b90cf4Smrg    corresponding to an arrived event. Fix this by adding entries at the end
242924b90cf4Smrg    of the list.
243024b90cf4Smrg    
243124b90cf4Smrg    (Ported from radeon commit 3e24770b1b472fc15df56d06f5f04778c9db63dd)
243224b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
243324b90cf4Smrg
243424b90cf4Smrgcommit 22740f86d028cdd0f556543df7444516a86f923b
243524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
243624b90cf4SmrgDate:   Fri Aug 18 17:15:54 2017 +0900
243724b90cf4Smrg
243824b90cf4Smrg    Consolidate amdgpu_scanout_flip_abort/handler helpers
243924b90cf4Smrg    
244024b90cf4Smrg    While at it, make them use crtc->driver_private.
244124b90cf4Smrg    
244224b90cf4Smrg    (Ported from radeon commit 36ce7920136c0d723c9397a84e7dd5926a9c7943)
244324b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
244424b90cf4Smrg
244524b90cf4Smrgcommit 2692508ae8920ce62f488a9384444c1645964913
244624b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
244724b90cf4SmrgDate:   Fri Aug 18 17:12:15 2017 +0900
244824b90cf4Smrg
244924b90cf4Smrg    Always allow DRI2 page flipping with TearFree
245024b90cf4Smrg    
245124b90cf4Smrg    Even if TearFree is enabled for the CRTC we're synchronizing to.
245224b90cf4Smrg    
245324b90cf4Smrg    (Ported from radeon commit d314cbfb228bb4b8762714f98d0c114a8ee3f061)
245424b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
245524b90cf4Smrg
245624b90cf4Smrgcommit 8c82878c6ef1b984ba289383dc17152192c916ee
245724b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
245824b90cf4SmrgDate:   Fri Aug 18 16:57:13 2017 +0900
245924b90cf4Smrg
246024b90cf4Smrg    Always allow Present page flipping with TearFree
246124b90cf4Smrg    
246224b90cf4Smrg    Even if TearFree is active for the the CRTC we're synchronizing to. In
246324b90cf4Smrg    that case, for Present flips synchronized to vertical blank, the other
246424b90cf4Smrg    scanout buffer is immediately synchronized and flipped to during the
246524b90cf4Smrg    target vertical blank period. For Present flips not synchronized to
246624b90cf4Smrg    vertical blank, we simply use the MSC and timestamp values of the last
246724b90cf4Smrg    vertical blank period for timing purposes, and let the normal TearFree
246824b90cf4Smrg    mechanism handle display updates.
246924b90cf4Smrg    
247024b90cf4Smrg    (Ported from radeon commit 4445765af5b97d0cfd10889fe6d6f58f2ce85659)
247124b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
247224b90cf4Smrg
247324b90cf4Smrgcommit d8e8f0107bb3e83a787917f4db16a7a54ce4768b
247424b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
247524b90cf4SmrgDate:   Fri Aug 18 16:46:18 2017 +0900
247624b90cf4Smrg
247724b90cf4Smrg    Pass extents to amdgpu_scanout_do_update
247824b90cf4Smrg    
247924b90cf4Smrg    Preparation for following change, no functional change intended yet.
248024b90cf4Smrg    
248124b90cf4Smrg    (Ported from radeon commit 65e0c5ea1b4adff21d673dbf54af99704c429627)
248224b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
248324b90cf4Smrg
248424b90cf4Smrgcommit cc1dfb88eb6714fcdcb9b576a70f400a5d0d58ca
248524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
248624b90cf4SmrgDate:   Fri Aug 18 16:34:50 2017 +0900
248724b90cf4Smrg
248824b90cf4Smrg    Add source drawable parameter to amdgpu_scanout_do_update
248924b90cf4Smrg    
249024b90cf4Smrg    Preparation for following changes, no functional change intended yet.
249124b90cf4Smrg    
249224b90cf4Smrg    (Ported from radeon commit 1443270e52e8562bd8dc3603f301963bd4027cef)
249324b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
249424b90cf4Smrg
249524b90cf4Smrgcommit b82d1b6063a36facc9cdd0e0189fdb6932be94e2
249624b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
249724b90cf4SmrgDate:   Fri Aug 18 16:23:39 2017 +0900
249824b90cf4Smrg
249924b90cf4Smrg    Handle multiple "pending" Present flips
250024b90cf4Smrg    
250124b90cf4Smrg    The xserver Present code can submit a flip in response to notifying it
250224b90cf4Smrg    that a vblank event arrived. This can happen before the completion event
250324b90cf4Smrg    of the previous flip is processed. In that case, we were clearing the
250424b90cf4Smrg    drmmode_crtc->flip_pending field prematurely.
250524b90cf4Smrg    
250624b90cf4Smrg    Prevent this by only clearing drmmode_crtc->flip_pending when it matches
250724b90cf4Smrg    the framebuffer being scanned out since the flip whose completion event
250824b90cf4Smrg    we're processing.
250924b90cf4Smrg    
251024b90cf4Smrg    (Ported from radeon commit 7c10ee9c88378d773c0bcf651fdc5d9f2c6dc5e5)
251124b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
251224b90cf4Smrg
251324b90cf4Smrgcommit 2cbe7f2dff5eef159486f875b3ec67516c85862d
251424b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
251524b90cf4SmrgDate:   Fri Aug 18 16:13:17 2017 +0900
251624b90cf4Smrg
251724b90cf4Smrg    Wait for pending flips synchronously before turning off a CRTC
251824b90cf4Smrg    
251924b90cf4Smrg    Allows removing drmmode_clear_pending_flip and the pending_dpms_mode
252024b90cf4Smrg    field and cleaning up the code considerably.
252124b90cf4Smrg    
252224b90cf4Smrg    (Ported from radeon commit e6d7dc2070f4d21a6900916bb70a31839112882c)
252324b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
252424b90cf4Smrg
252524b90cf4Smrgcommit e8d0bfab276d47338c337955b9d2fcbff3af225f
252624b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
252724b90cf4SmrgDate:   Fri Aug 18 16:11:41 2017 +0900
252824b90cf4Smrg
252924b90cf4Smrg    Create drmmode_crtc_wait_pending_event helper macro
253024b90cf4Smrg    
253124b90cf4Smrg    Preparation for following change, no functional change intended yet.
253224b90cf4Smrg    
253324b90cf4Smrg    (Ported from radeon commit f87acdbfb1b0b6d2769764772a52ea8b81675e20)
253424b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
253524b90cf4Smrg
253624b90cf4Smrgcommit fd5b78b7edff2021111bca37642b8b508f0c3328
253724b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
253824b90cf4SmrgDate:   Fri Aug 18 15:12:35 2017 +0900
253924b90cf4Smrg
254024b90cf4Smrg    Create drmmode_wait_vblank helper
254124b90cf4Smrg    
254224b90cf4Smrg    Allows cleaning up the code considerably.
254324b90cf4Smrg    
254424b90cf4Smrg    (Ported from radeon commit 99f1d7a474af3683fe1a66f50c0bb8935478ff0a)
254524b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
254624b90cf4Smrg
254724b90cf4Smrgcommit 24b2718992e4bbc859c07e5b29b571f53314045d
254824b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
254924b90cf4SmrgDate:   Fri Aug 18 15:03:52 2017 +0900
255024b90cf4Smrg
255124b90cf4Smrg    Pass reference CRTC to amdgpu_do_pageflip directly
255224b90cf4Smrg    
255324b90cf4Smrg    Simplifies the code slightly.
255424b90cf4Smrg    
255524b90cf4Smrg    (Ported from radeon commit 49cc61ab970ee28d4509b4e2dd0a57165136889f)
255624b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
255724b90cf4Smrg
255824b90cf4Smrgcommit 87a1f577f1de62f6b628bbe221cd8d551531e708
255924b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
256024b90cf4SmrgDate:   Fri Aug 18 14:56:10 2017 +0900
256124b90cf4Smrg
256224b90cf4Smrg    Remove drmmode_crtc->scanout_destroy[] array
256324b90cf4Smrg    
256424b90cf4Smrg    No longer necessary since we're reference counting framebuffers.
256524b90cf4Smrg    
256624b90cf4Smrg    (Ported from radeon commit 3f120fa1d5d921656a367751bc079e020e9ab105)
256724b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
256824b90cf4Smrg
256924b90cf4Smrgcommit e15b23663cd1a6f85394253b3fb566b55828b1c5
257024b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
257124b90cf4SmrgDate:   Tue Apr 18 18:21:24 2017 +0900
257224b90cf4Smrg
257324b90cf4Smrg    Adapt to PixmapDirtyUpdateRec::src being a DrawablePtr
257424b90cf4Smrg
257524b90cf4Smrgcommit 9caa9dd9cc5eb9882c4bb85275bc318948dab71f
257624b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
257724b90cf4SmrgDate:   Wed Aug 2 19:07:40 2017 +0900
257824b90cf4Smrg
257924b90cf4Smrg    Allow DRI page flipping when some CRTCs use separate scanout buffers
258024b90cf4Smrg    
258124b90cf4Smrg    As long as the CRTC we're synchronizing to doesn't.
258224b90cf4Smrg    
258324b90cf4Smrg    (Ported from radeon commit 5309bde0c4e28adf2b167191c6d7011a19e31eed)
258424b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
258524b90cf4Smrg
258624b90cf4Smrgcommit 4441c7c6dde2d71bd44c3031c5679ee3186ea8f9
258724b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
258824b90cf4SmrgDate:   Tue Aug 1 17:29:16 2017 +0900
258924b90cf4Smrg
259024b90cf4Smrg    Add drmmode_crtc_can_flip helper
259124b90cf4Smrg    
259224b90cf4Smrg    To reduce code duplication between DRI2 and Present. No functional
259324b90cf4Smrg    change intended yet.
259424b90cf4Smrg    
259524b90cf4Smrg    (Ported from radeon commit 9bc3eef74452d924f9101c024f66ad9b14c404c8)
259624b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
259724b90cf4Smrg
259824b90cf4Smrgcommit 3e08409344a2fd504429522507592f98555bec05
259924b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
260024b90cf4SmrgDate:   Wed Aug 2 19:03:40 2017 +0900
260124b90cf4Smrg
260224b90cf4Smrg    Use root window (pixmap) instead of screen pixmap for scanout updates
260324b90cf4Smrg    
260424b90cf4Smrg    Preparation for following changes, no functional change intended yet.
260524b90cf4Smrg    
260624b90cf4Smrg    (Ported from radeon commit c2d26890691ec105858f086b63170ad94c6f7f05)
260724b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
260824b90cf4Smrg
260924b90cf4Smrgcommit 35106fc0a948957cbb7e1e9649c89993a3d5c95c
261024b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
261124b90cf4SmrgDate:   Thu Jul 27 15:22:02 2017 +0900
261224b90cf4Smrg
261324b90cf4Smrg    Only handle reflection in the driver with Xorg < 1.16
261424b90cf4Smrg    
261524b90cf4Smrg    Xorg doesn't handle the hardware cursor correctly in that case for
261624b90cf4Smrg    rotation and general transforms, and we can't force the SW cursor.
261724b90cf4Smrg    
261824b90cf4Smrg    Fixes: ba2aa0a8c12a ("Handle rotation in the driver also with Xorg
261924b90cf4Smrg                          1.12-1.18")
262024b90cf4Smrg    (Cherry picked from radeon commit 7d7abf99b5441ddb04dbee99bc8fa7abc30d4c46)
262124b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
262224b90cf4Smrg
262324b90cf4Smrgcommit a47c0093338d80d84e7033ad15d051925d542ca0
262424b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
262524b90cf4SmrgDate:   Wed Jul 26 16:46:14 2017 +0900
262624b90cf4Smrg
262724b90cf4Smrg    autogen.sh: Pass -f to autoreconf
262824b90cf4Smrg    
262924b90cf4Smrg    To ensure that any existing copies of autotools files will be replaced
263024b90cf4Smrg    with the current versions.
263124b90cf4Smrg    
263224b90cf4Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
263324b90cf4Smrg
263424b90cf4Smrgcommit 842bad4b951296ca25f47b50cb358e502bf30ebb
263524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
263624b90cf4SmrgDate:   Wed Jul 26 16:44:00 2017 +0900
263724b90cf4Smrg
263824b90cf4Smrg    Makefile.am: Set ACLOCAL_AMFLAGS = -I m4
263924b90cf4Smrg    
264024b90cf4Smrg    Suggested by one of the tools called by autoreconf.
264124b90cf4Smrg    
264224b90cf4Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
264324b90cf4Smrg
264424b90cf4Smrgcommit 227b399badaad9bbef0be5a776ce008d0d243449
264524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
264624b90cf4SmrgDate:   Wed Jul 26 16:42:58 2017 +0900
264724b90cf4Smrg
264824b90cf4Smrg    Add AC_CONFIG_MACRO_DIRS([m4]) to configure.ac
264924b90cf4Smrg    
265024b90cf4Smrg    Suggested by one of the tools called by autoreconf.
265124b90cf4Smrg    
265224b90cf4Smrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
265324b90cf4Smrg
265424b90cf4Smrgcommit 4d36306bcebb8548455a21eae6a7216a9439d9e4
265524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
265624b90cf4SmrgDate:   Thu Jul 13 17:40:58 2017 +0900
265724b90cf4Smrg
265824b90cf4Smrg    If a TearFree flip fails, fall back to non-TearFree operation
265924b90cf4Smrg    
266024b90cf4Smrg    In order to avoid possible freeze / log file spam in that case.
266124b90cf4Smrg    
266224b90cf4Smrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99769
266324b90cf4Smrg    (Ported from radeon commit 94dc2b80f3ef0b2c17c20501d824fb0447d52e7a)
266424b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
266524b90cf4Smrg
266624b90cf4Smrgcommit 88147c1a532a9275eb57e14d8c11be41bf4c1fe1
266724b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
266824b90cf4SmrgDate:   Thu Jul 13 17:35:55 2017 +0900
266924b90cf4Smrg
267024b90cf4Smrg    Use drmmode_crtc->scanout_id instead of 0 to check for scanout buffer
267124b90cf4Smrg    
267224b90cf4Smrg    Preparation for following change, no functional change intended.
267324b90cf4Smrg    
267424b90cf4Smrg    (Ported from radeon commit aff267ee36cc6a703a532f91f82adc1ba1425ff3)
267524b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
267624b90cf4Smrg
267724b90cf4Smrgcommit e90721ba654d70db5eeb1cf552308c73151530ee
267824b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
267924b90cf4SmrgDate:   Tue Jun 27 18:13:05 2017 +0900
268024b90cf4Smrg
268124b90cf4Smrg    Only call drmmode_scanout_free for non-GPU screens in LeaveVT
268224b90cf4Smrg    
268324b90cf4Smrg    Destroying the scanout buffers of GPU screens resulted in a crash when
268424b90cf4Smrg    switching back to the Xorg VT.
268524b90cf4Smrg    
268624b90cf4Smrg    Fixes: b10ecdbd89b0 ("Use drmmode_crtc_scanout_* helpers for RandR 1.4
268724b90cf4Smrg                          scanout pixmaps")
268824b90cf4Smrg    (Ported from radeon commit c9dd28cb0c9c3de676eadac61e727732510f6b9b)
268924b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
269024b90cf4Smrg
269124b90cf4Smrgcommit 1b6ff5fd9933c00ec1ec90dfc62e0b531927749b
269224b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
269324b90cf4SmrgDate:   Thu Jun 22 16:27:32 2017 +0900
269424b90cf4Smrg
269524b90cf4Smrg    Improve drmmode_fb_reference debugging code
269624b90cf4Smrg    
269724b90cf4Smrg    If a reference count is <= 0, call FatalError with the call location
269824b90cf4Smrg    (in case it doesn't get resolved in the backtrace printed by
269924b90cf4Smrg    FatalError).
270024b90cf4Smrg    
270124b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
270224b90cf4Smrg
270324b90cf4Smrgcommit af7221e1c4d2dbdfd488eb0976a835584ea8441c
270424b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
270524b90cf4SmrgDate:   Wed Jun 21 19:01:54 2017 +0900
270624b90cf4Smrg
270724b90cf4Smrg    Increase reference count of FB assigned to drmmode_crtc->flip_pending
270824b90cf4Smrg    
270924b90cf4Smrg    Otherwise, it could happen that we destroy the FB before the flip
271024b90cf4Smrg    completes, resulting in use-after-free and most likely a crash.
271124b90cf4Smrg    
271224b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
271324b90cf4Smrg
271424b90cf4Smrgcommit 184d50e008b9b31f4dda1425e255af068b6ab068
271524b90cf4SmrgAuthor: Adam Jackson <ajax@redhat.com>
271624b90cf4SmrgDate:   Tue Jun 13 09:36:21 2017 -0400
271724b90cf4Smrg
271824b90cf4Smrg    modesetting: Validate the atom for enum properties
271924b90cf4Smrg    
272024b90cf4Smrg    The client could have said anything here, and if what they said doesn't
272124b90cf4Smrg    actually name an atom NameForAtom() will return NULL, and strcmp() will
272224b90cf4Smrg    be unhappy about that.
272324b90cf4Smrg    
272424b90cf4Smrg    [copied from xserver d4995a3936ae283b9080fdaa0905daa669ebacfc]
272524b90cf4Smrg    
272624b90cf4Smrg    Signed-off-by: Adam Jackson <ajax@redhat.com>
272724b90cf4Smrg    Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
272824b90cf4Smrg
272924b90cf4Smrgcommit bbdac40e2af472d37aa0f4f26df77a0b1b12a830
273024b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
273124b90cf4SmrgDate:   Thu Jun 8 10:46:26 2017 +0900
273224b90cf4Smrg
273324b90cf4Smrg    Improve AMDGPUPreInitAccel_KMS log messages
273424b90cf4Smrg    
273524b90cf4Smrg    Now it should always be clear in the log file why acceleration isn't
273624b90cf4Smrg    enabled.
273724b90cf4Smrg    
273824b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
273924b90cf4Smrg
274024b90cf4Smrgcommit b09fde0d81e07fbe96139289098b4d4b9f5e3c35
274124b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
274224b90cf4SmrgDate:   Thu May 11 19:04:11 2017 +0900
274324b90cf4Smrg
274424b90cf4Smrg    Use reference counting for tracking KMS framebuffer lifetimes
274524b90cf4Smrg    
274624b90cf4Smrg    References are held by the pixmaps corresponding to the FBs (so
274724b90cf4Smrg    the same KMS FB can be reused as long as the pixmap exists) and by the
274824b90cf4Smrg    CRTCs scanning out from them (so a KMS FB is only destroyed once it's
274924b90cf4Smrg    not being scanned out anymore, preventing intermittent black screens and
275024b90cf4Smrg    worse issues due to a CRTC turning off when it should be on).
275124b90cf4Smrg    
275224b90cf4Smrg    v2:
275324b90cf4Smrg    * Only increase reference count in drmmode_fb_reference if it was sane
275424b90cf4Smrg      before
275524b90cf4Smrg    * Make drmmode_fb_reference's indentation match the rest of
275624b90cf4Smrg      drmmode_display.h
275724b90cf4Smrg    
275824b90cf4Smrg    (Ported from radeon commit 55e513b978b2afc52b7cafc5bfcb0d1dc78d75f6)
275924b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
276024b90cf4Smrg
276124b90cf4Smrgcommit 000e5eaeb20607508c5c5371654615a30a8a1b0b
276224b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
276324b90cf4SmrgDate:   Wed May 24 10:12:55 2017 +0900
276424b90cf4Smrg
276524b90cf4Smrg    Update URLs
276624b90cf4Smrg    
276724b90cf4Smrg    * Point to the amd-gfx mailing list
276824b90cf4Smrg    * Specify the component in all bugzilla URLs
276924b90cf4Smrg    * Use https:// for all HTML URLs
277024b90cf4Smrg    
277124b90cf4Smrg    (Ported from radeon commit d80d01a73c2eaba2e3649b7bc0a3541b3ff782f6)
277224b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
277324b90cf4Smrg
277424b90cf4Smrgcommit 2ea2d4d827f086098be198f110ca822ed2c290cd
277524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
277624b90cf4SmrgDate:   Fri May 12 19:01:18 2017 +0900
277724b90cf4Smrg
277824b90cf4Smrg    Simplify tracking of PRIME scanout pixmap
277924b90cf4Smrg    
278024b90cf4Smrg    Remember the shared pixmap passed to drmmode_set_scanout_pixmap for each
278124b90cf4Smrg    CRTC, and just compare against that.
278224b90cf4Smrg    
278324b90cf4Smrg    Fixes leaving stale entries in ScreenRec::pixmap_dirty_list under some
278424b90cf4Smrg    circumstances, which would usually result in use-after-free and a crash
278524b90cf4Smrg    down the line.
278624b90cf4Smrg    
278724b90cf4Smrg    (Ported from radeon commit 7dc68e26755466f9056f8c72195ab8690660693d)
278824b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
278924b90cf4Smrg
279024b90cf4Smrgcommit 8cb41b962eb06b9cb1b3a573a4087e4d89f733fb
279124b90cf4SmrgAuthor: Eric Anholt <eric@anholt.net>
279224b90cf4SmrgDate:   Wed May 17 16:11:52 2017 +0900
279324b90cf4Smrg
279424b90cf4Smrg    Use plain glamor_egl_create_textured_screen().
279524b90cf4Smrg    
279624b90cf4Smrg    Since 5064ffab631 (2014), glamor's implementation of _ext just drops the
279724b90cf4Smrg    back_pixmap arg, which we were passing NULL (the default) to anyway.
279824b90cf4Smrg    
279924b90cf4Smrg    Signed-off-by: Eric Anholt <eric@anholt.net>
280024b90cf4Smrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
280124b90cf4Smrg    (Ported from radeon commit 2b7d77b90108911777a11ecaa63435552000c958)
280224b90cf4Smrg
280324b90cf4Smrgcommit e900e48a11a93cde7d8d2d7bdb4a15ec705c56b1
280424b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
280524b90cf4SmrgDate:   Wed May 10 18:37:56 2017 +0900
280624b90cf4Smrg
280724b90cf4Smrg    Don't enable DRI3 without glamor
280824b90cf4Smrg    
280924b90cf4Smrg    Can't work currently. Fixes crash when trying to run a DRI3 client when
281024b90cf4Smrg    glamor isn't enabled.
281124b90cf4Smrg    
281224b90cf4Smrg    Bugzilla: https://bugs.freedesktop.org/100968
281324b90cf4Smrg    
281424b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
281524b90cf4Smrg
281624b90cf4Smrgcommit 462ac3341e5bfbded9086d3d9043821d19352b3e
281724b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
281824b90cf4SmrgDate:   Tue May 2 17:58:55 2017 +0900
281924b90cf4Smrg
282024b90cf4Smrg    Remove unused struct members from drmmode_display.h
282124b90cf4Smrg    
282224b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
282324b90cf4Smrg
282424b90cf4Smrgcommit 82fa615f38137add75f9cd4bb49c48dd88de916f
282524b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
282624b90cf4SmrgDate:   Tue May 2 11:53:25 2017 +0900
282724b90cf4Smrg
282824b90cf4Smrg    Apply gamma correction to HW cursor
282924b90cf4Smrg    
283024b90cf4Smrg    The display hardware CLUT we're currently using for gamma correction
283124b90cf4Smrg    doesn't affect the HW cursor, so we have to apply it manually when
283224b90cf4Smrg    uploading the HW cursor data.
283324b90cf4Smrg    
283424b90cf4Smrg    This currently only works in depth 24/32.
283524b90cf4Smrg    
283624b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
283724b90cf4Smrg
283824b90cf4Smrgcommit 981bac185cfd74ae50dffc28f57cf34623a9595f
283924b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
284024b90cf4SmrgDate:   Thu Mar 23 18:51:38 2017 +0900
284124b90cf4Smrg
284224b90cf4Smrg    Don't set modes before AMDGPUWindowExposures_oneshot is called
284324b90cf4Smrg    
284424b90cf4Smrg    The root window contents may be undefined before that, so we don't want
284524b90cf4Smrg    to show anything yet.
284624b90cf4Smrg    
284724b90cf4Smrg    Fixes a crash on startup with rotation and virtual resolution set in
284824b90cf4Smrg    xorg.conf.
284924b90cf4Smrg    
285024b90cf4Smrg    Bugzilla: https://bugs.freedesktop.org/100276
285124b90cf4Smrg    Fixes: ad53635af150 ("Move DPMS check from amdgpu_scanout_do_update to
285224b90cf4Smrg                          amdgpu_scanout_flip")
285324b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
285424b90cf4Smrg
285524b90cf4Smrgcommit 51e17041cb89806c934c5cf795207940a6aaccfe
285624b90cf4SmrgAuthor: Daniel Stone <daniels@collabora.com>
285724b90cf4SmrgDate:   Mon Apr 10 17:36:01 2017 +0900
285824b90cf4Smrg
285924b90cf4Smrg    Set correct DRM event context version
286024b90cf4Smrg    
286124b90cf4Smrg    DRM_EVENT_CONTEXT_VERSION is the latest context version supported by
286224b90cf4Smrg    whatever version of libdrm is present. We were blindly asserting we
286324b90cf4Smrg    supported whatever version that may be, even if we actually didn't.
286424b90cf4Smrg    
286524b90cf4Smrg    Set the version as 2, which should be bumped only with the appropriate
286624b90cf4Smrg    version checks.
286724b90cf4Smrg    
286824b90cf4Smrg    Signed-off-by: Daniel Stone <daniels@collabora.com>
286924b90cf4Smrg    (Ported from xserver commit 0c8e6ed85810e96d84173a52d628863802a78d82)
287024b90cf4Smrg    v2: Remove second paragraph of commit log, we always initialize
287124b90cf4Smrg            page_flip_handler2 = NULL (Emil Velikov)
287224b90cf4Smrg    Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
287324b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com> # v1
287424b90cf4Smrg
287524b90cf4Smrgcommit 67d155e62f5e09af242b0181527c162576dae02e
287624b90cf4SmrgAuthor: Nicholas Molloy <nick.a.molloy@gmail.com>
287724b90cf4SmrgDate:   Sun Mar 26 02:38:40 2017 +1300
287824b90cf4Smrg
287924b90cf4Smrg    Fix a misspelling of 'acceleration' in amdgpu_kms.c
288024b90cf4Smrg    
288124b90cf4Smrg    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
288224b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
288324b90cf4Smrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
288424b90cf4Smrg
288524b90cf4Smrgcommit 165b51447643ce37f391f25ca6aecb8d76fabaa3
288624b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
288724b90cf4SmrgDate:   Wed Mar 22 18:58:32 2017 +0900
288824b90cf4Smrg
288924b90cf4Smrg    manpage: Don't put "'" at the beginning of a line
289024b90cf4Smrg    
289124b90cf4Smrg    It caused the whole line to be dropped.
289224b90cf4Smrg    
289324b90cf4Smrg    Fixes: af0b24c1aca4 ("Allow toggling TearFree at runtime via output
289424b90cf4Smrg                          property")
289524b90cf4Smrg    Reported-by: Andy Furniss <adf.lists@gmail.com>
289624b90cf4Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
289724b90cf4Smrg
289824b90cf4Smrgcommit 1b476d417f85fd1b97e813adbbf4970db07adf5c
289924b90cf4SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
290024b90cf4SmrgDate:   Thu Mar 23 18:03:56 2017 +0900
290124b90cf4Smrg
290224b90cf4Smrg    Post-release version bump
290324b90cf4Smrg
290411bf0794Smrgcommit 804e30e14e51f94403a0721ef2aae28f1fa9e9f2
290511bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
290611bf0794SmrgDate:   Thu Mar 16 17:28:11 2017 +0900
290711bf0794Smrg
290811bf0794Smrg    Bump version for 1.3.0 release
290911bf0794Smrg
291011bf0794Smrgcommit 3a8582944ed3fef1b75f8871489e6e19963e2ea6
291111bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
291211bf0794SmrgDate:   Thu Mar 9 15:56:59 2017 +0900
291311bf0794Smrg
291411bf0794Smrg    Pass TRUE to drmmode_set_desired_modes the first time for GPU screens
291511bf0794Smrg    
291611bf0794Smrg    This is the only place we call drmmode_set_desired_modes for GPU screens
291711bf0794Smrg    during server startup. Without this change, the display outputs of
291811bf0794Smrg    secondary GPUs may stay on even while Xorg isn't using them.
291911bf0794Smrg    
292011bf0794Smrg    (Ported from radeon commit 9a71445094b728f3d78db8f6808b4782ee19a453)
292111bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
292211bf0794Smrg
292311bf0794Smrgcommit 82b15a4da156e18da4c8fc0093500c32b549e487
292411bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
292511bf0794SmrgDate:   Thu Mar 9 15:47:24 2017 +0900
292611bf0794Smrg
292711bf0794Smrg    Skip some initialization steps for GPU screens
292811bf0794Smrg    
292911bf0794Smrg    Xorg doesn't use the following functionality of GPU screens, so don't
293011bf0794Smrg    bother initializing it:
293111bf0794Smrg    
293211bf0794Smrg    * DRI page flipping
293311bf0794Smrg    * DRI3 / Present / SYNC fences
293411bf0794Smrg    * XVideo / XvMC
293511bf0794Smrg    * Root window with background None
293611bf0794Smrg    
293711bf0794Smrg    (Ported from radeon commit 67ae5e00a748ad52cf92738d401afff2947b1891)
293811bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
293911bf0794Smrg
294011bf0794Smrgcommit fa85331f0ce27e16a9338516518433955133840e
294111bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
294211bf0794SmrgDate:   Tue Mar 7 18:02:29 2017 +0900
294311bf0794Smrg
294411bf0794Smrg    glamor: Use glamor_finish when available
294511bf0794Smrg    
294611bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
294711bf0794Smrg
294811bf0794Smrgcommit 7884e38e94c2cbd6c205f556f2b31ad59b4089b4
294911bf0794SmrgAuthor: Hans De Goede <hdegoede@redhat.com>
295011bf0794SmrgDate:   Tue Oct 18 16:48:40 2016 +0200
295111bf0794Smrg
295211bf0794Smrg    amdgpu_probe: Do not close server managed drm fds
295311bf0794Smrg    
295411bf0794Smrg    This fixes the xserver only seeing AMD/ATI devices supported by the amdgpu
295511bf0794Smrg    driver, as by the time xf86-video-ati gets a chance to probe them, the
295611bf0794Smrg    fd has been closed.
295711bf0794Smrg    
295811bf0794Smrg    This fixes e.g. Xorg not seeing the dGPU on a Lenovo Thinkpad E465 laptop
295911bf0794Smrg    with a CARRIZO iGPU and a HAINAN dGPU.
296011bf0794Smrg    
296111bf0794Smrg    Signed-off-by: Hans de Goede <hdegoede@redhat.com>
296211bf0794Smrg    
296311bf0794Smrg    v2: Rebased on top of new patch 1.
296411bf0794Smrg    
296511bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
296611bf0794Smrg
296711bf0794Smrgcommit a2c360fa1d33d6a5aa64c396197e119ff77d1379
296811bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
296911bf0794SmrgDate:   Mon Mar 6 18:59:23 2017 +0900
297011bf0794Smrg
297111bf0794Smrg    Refactor amdgpu_kernel_close_fd helper
297211bf0794Smrg    
297311bf0794Smrg    Preparation for the following change.
297411bf0794Smrg    
297511bf0794Smrg    Assign pAMDGPUEnt->fd = -1 instead of 0 when we're not using the file
297611bf0794Smrg    descriptor anymore.
297711bf0794Smrg    
297811bf0794Smrg    Reviewed-by: Hans de Goede <hdegoede@redhat.com>
297911bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
298011bf0794Smrg
298111bf0794Smrgcommit 947017194d07e32876a43ee0efc45fdc71385748
298211bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
298311bf0794SmrgDate:   Fri Mar 3 17:59:19 2017 +0900
298411bf0794Smrg
298511bf0794Smrg    glamor: Don't flush in BlockHandler with Xorg >= 1.19
298611bf0794Smrg    
298711bf0794Smrg    This was only necessary with older versions for driving the FBO cache
298811bf0794Smrg    expiry mechanism.
298911bf0794Smrg    
299011bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
299111bf0794Smrg
299211bf0794Smrgcommit 86907a5e4ce33154167b330570491f88218725d3
299311bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
299411bf0794SmrgDate:   Mon Mar 6 18:23:41 2017 +0900
299511bf0794Smrg
299611bf0794Smrg    Only define transform_region for XF86_CRTC_VERSION >= 4
299711bf0794Smrg    
299811bf0794Smrg    Not used with older versions of Xorg. Fixes warning in that case:
299911bf0794Smrg    
300011bf0794Smrg    ../../src/amdgpu_kms.c:328:1: warning: ‘transform_region’ defined but not used [-Wunused-function]
300111bf0794Smrg     transform_region(RegionPtr region, struct pict_f_transform *transform,
300211bf0794Smrg     ^~~~~~~~~~~~~~~~
300311bf0794Smrg    
300411bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
300511bf0794Smrg
300611bf0794Smrgcommit 8d2b7d1758e3fcac520a18a0684c073f0ac62389
300711bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
300811bf0794SmrgDate:   Mon Mar 6 18:09:58 2017 +0900
300911bf0794Smrg
301011bf0794Smrg    Use local implementation of RegionDuplicate for older xserver
301111bf0794Smrg    
301211bf0794Smrg    It was only added in xserver 1.15. Fixes build against older xserver.
301311bf0794Smrg    
301411bf0794Smrg    Reported-by: Pali Rohár <pali.rohar@gmail.com>
301511bf0794Smrg    (Ported from radeon commit 80cc892ee1ce54fad3cb7dd11bd9df18c359136f)
301611bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
301711bf0794Smrg
301811bf0794Smrgcommit cd73100114a18642d9c40f1df33cef8311e96a8b
301911bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
302011bf0794SmrgDate:   Mon Mar 6 18:07:19 2017 +0900
302111bf0794Smrg
302211bf0794Smrg    Don't use pScrn->is_gpu in AMDGPUCreateScreenResources_KMS
302311bf0794Smrg    
302411bf0794Smrg    Looks like this snuck in accidentally.
302511bf0794Smrg    
302611bf0794Smrg    Brings us back in line with the radeon driver, and fixes the build
302711bf0794Smrg    against older versions of xserver which didn't have the is_gpu field
302811bf0794Smrg    yet.
302911bf0794Smrg    
303011bf0794Smrg    Fixes: 6bab8fabb37e ("Remove info->dri2.drm_fd and info->drmmode->fd")
303111bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
303211bf0794Smrg
303311bf0794Smrgcommit 351baa89b9b0ecfb6c666af3a2d10c559a9224a9
303411bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
303511bf0794SmrgDate:   Fri Mar 3 16:44:15 2017 +0900
303611bf0794Smrg
303711bf0794Smrg    Don't call amdgpu_glamor_flush in drmmode_copy_fb
303811bf0794Smrg    
303911bf0794Smrg    AMDGPUWindowExposures_oneshot takes care of it.
304011bf0794Smrg    
304111bf0794Smrg    (Ported from radeon commit d63881623f0686a66a2e3e3c1f84e496aa52ec6b)
304211bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
304311bf0794Smrg
304411bf0794Smrgcommit ad53635af150cda9b8da413be5a011d74f972ac7
304511bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
304611bf0794SmrgDate:   Fri Mar 3 16:41:49 2017 +0900
304711bf0794Smrg
304811bf0794Smrg    Move DPMS check from amdgpu_scanout_do_update to amdgpu_scanout_flip
304911bf0794Smrg    
305011bf0794Smrg    When amdgpu_scanout_do_update is called from
305111bf0794Smrg    drmmode_crtc_scanout_update, drmmode_crtc->pending_dpms_mode may still
305211bf0794Smrg    be != DPMSModeOn, e.g. during server startup.
305311bf0794Smrg    
305411bf0794Smrg    Fixes intermittently showing garbage with TearFree enabled.
305511bf0794Smrg    
305611bf0794Smrg    (Ported from radeon commit cc9d6b7db9c2078be1e530a64af6d517c6a42024)
305711bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
305811bf0794Smrg
305911bf0794Smrgcommit 378bd05c849ad3092f138bdc8917d35d0b967389
306011bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
306111bf0794SmrgDate:   Fri Mar 3 16:36:24 2017 +0900
306211bf0794Smrg
306311bf0794Smrg    Call drmmode_set_desired_modes from a WindowExposures hook
306411bf0794Smrg    
306511bf0794Smrg    This is the earliest opportunity where the root window contents are
306611bf0794Smrg    guaranteed to be initialized, and prevents drmmode_set_mode_major from
306711bf0794Smrg    getting called before drmmode_set_desired_modes via AMDGPUUnblank ->
306811bf0794Smrg    drmmode_crtc_dpms. Also, in contrast to the BlockHandler hook, this is
306911bf0794Smrg    called when running Xorg with -pogo.
307011bf0794Smrg    
307111bf0794Smrg    Fixes intermittently showing garbage on server startup or after server
307211bf0794Smrg    reset.
307311bf0794Smrg    
307411bf0794Smrg    As a bonus, this avoids trouble due to higher layers (e.g. the tigervnc
307511bf0794Smrg    Xorg module) calling AMDGPUBlockHandler_oneshot repeatedly even after
307611bf0794Smrg    we set pScreen->BlockHandler = AMDGPUBlockHandler_KMS.
307711bf0794Smrg    
307811bf0794Smrg    Bugzilla: https://bugs.freedesktop.org/99457
307911bf0794Smrg    (Ported from radeon commits 0a12bf1085505017068dfdfd31d23133e51b45b9 and
308011bf0794Smrg    f0e7948e1c0e984fc27f235f365639e9cf628291)
308111bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
308211bf0794Smrg
308311bf0794Smrgcommit 8d4d73e05ce34eb353daec7b2c0e7c844113c7de
308411bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
308511bf0794SmrgDate:   Fri Mar 3 16:34:16 2017 +0900
308611bf0794Smrg
308711bf0794Smrg    present: Flush before flipping
308811bf0794Smrg    
308911bf0794Smrg    This isn't necessary for DRI clients, but the Present extension can also
309011bf0794Smrg    be used for presenting normal pixmaps rendered to via the X11 protocol.
309111bf0794Smrg    
309211bf0794Smrg    (Ported from radeon commit 9035b6abea557828e672ee455f0c84e43da0906f)
309311bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
309411bf0794Smrg
309511bf0794Smrgcommit 88725b68cad92418c9bb03cb7f20526ce238d64e
309611bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
309711bf0794SmrgDate:   Fri Mar 3 16:30:27 2017 +0900
309811bf0794Smrg
309911bf0794Smrg    present: Use async flip for unflip if possible
310011bf0794Smrg    
310111bf0794Smrg    In that case, unflip operations should finish faster in general.
310211bf0794Smrg    
310311bf0794Smrg    (Ported from radeon commit 0a4eb0e12f0c9c653cf4cea6fd62e1a507eb261c)
310411bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
310511bf0794Smrg
310611bf0794Smrgcommit b31489c086b4bc50c824e85fa26d97c0f43afb20
310711bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
310811bf0794SmrgDate:   Fri Mar 3 16:28:41 2017 +0900
310911bf0794Smrg
311011bf0794Smrg    present: Also flush before using a flip to unflip
311111bf0794Smrg    
311211bf0794Smrg    Not doing so might result in intermittently scanning out stale contents
311311bf0794Smrg    of the screen pixmap.
311411bf0794Smrg    
311511bf0794Smrg    (Ported from radeon commit 9a951a3e551db58ba50e7a594521ceac54d90615)
311611bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
311711bf0794Smrg
311811bf0794Smrgcommit f6a3c87c3097e8d5c1d2159bc90d6541a46ed8be
311911bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
312011bf0794SmrgDate:   Fri Mar 3 16:26:26 2017 +0900
312111bf0794Smrg
312211bf0794Smrg    present: Wait for GPU idle before setting modes for unflip
312311bf0794Smrg    
312411bf0794Smrg    To make sure the screen pixmap contents are up to date when it starts
312511bf0794Smrg    being scanned out.
312611bf0794Smrg    
312711bf0794Smrg    (Ported from radeon commit 244d4bc7f8c8f6bc90f49556c0b9344c8aa40295)
312811bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
312911bf0794Smrg
313011bf0794Smrgcommit 012ffffb45119059f3610fb8fd6ae103186b3e3c
313111bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
313211bf0794SmrgDate:   Fri Mar 3 16:22:39 2017 +0900
313311bf0794Smrg
313411bf0794Smrg    present: Only call drmModeRmFB after setting modes for unflip
313511bf0794Smrg    
313611bf0794Smrg    Fixes display intermittently blanking when a modeset is used for unflip.
313711bf0794Smrg    
313811bf0794Smrg    (Ported from radeon commit 3ff29e5a14451916bc66b4e0028e9a317f0723f8)
313911bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
314011bf0794Smrg
314111bf0794Smrgcommit f4719bb473df897012f8830f46e99cb781d67b6f
314211bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
314311bf0794SmrgDate:   Fri Mar 3 16:19:11 2017 +0900
314411bf0794Smrg
314511bf0794Smrg    Use drmmode_crtc_scanout_free in drmmode_fini
314611bf0794Smrg    
314711bf0794Smrg    We were leaking drmmode_crtc->scanout_damage, which caused trouble on
314811bf0794Smrg    server reset. Fixes server reset with active separate scanout pixmaps.
314911bf0794Smrg    
315011bf0794Smrg    (Cherry picked from radeon commit 0c29deb5a97d9a57e994cc0053c49ddf7aca6ecb)
315111bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
315211bf0794Smrg
315311bf0794Smrgcommit af0b24c1aca4cba2692d5aa410e63cb536478dbe
315411bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
315511bf0794SmrgDate:   Thu Mar 2 17:24:03 2017 +0900
315611bf0794Smrg
315711bf0794Smrg    Allow toggling TearFree at runtime via output property
315811bf0794Smrg    
315911bf0794Smrg    Option "TearFree" now sets the default value of the output property.
316011bf0794Smrg    See the manpage update for details.
316111bf0794Smrg    
316211bf0794Smrg    TearFree is now enabled by default for outputs using rotation or other
316311bf0794Smrg    RandR transforms, and for RandR 1.4 slave outputs.
316411bf0794Smrg    
316511bf0794Smrg    (Ported from radeon commit 58cd1600057e41aade0106d4acf78e23eac6e44f)
316611bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
316711bf0794Smrg
316811bf0794Smrgcommit 77853f02e5b879e7042f55c672cf2d8e6955309f
316911bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
317011bf0794SmrgDate:   Thu Mar 2 17:19:59 2017 +0900
317111bf0794Smrg
317211bf0794Smrg    Factor out drmmode_crtc_scanout_update helper
317311bf0794Smrg    
317411bf0794Smrg    Cleanup in preparation for following change, no functional change
317511bf0794Smrg    intended.
317611bf0794Smrg    
317711bf0794Smrg    (Ported from radeon commit 305e2cbf335837a2ab6a24e9ff65815afe038296)
317811bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
317911bf0794Smrg
318011bf0794Smrgcommit d25cc3b2b3b2d257aea247b85fea405d7e84e5b1
318111bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
318211bf0794SmrgDate:   Thu Mar 2 17:15:03 2017 +0900
318311bf0794Smrg
318411bf0794Smrg    Factor out amdgpu_prime_dirty_to_crtc helper
318511bf0794Smrg    
318611bf0794Smrg    Cleanup in preparation for the following change, no functional change
318711bf0794Smrg    intended.
318811bf0794Smrg    
318911bf0794Smrg    (Ported from radeon commit 649644a88347a6d03de68f8c41db03a82deeb23b)
319011bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
319111bf0794Smrg
319211bf0794Smrgcommit a6d363008e2b55f0aa6151be1a99f01b97870e91
319311bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
319411bf0794SmrgDate:   Thu Mar 2 17:13:06 2017 +0900
319511bf0794Smrg
319611bf0794Smrg    Don't destroy current FB if drmModeAddFB fails
319711bf0794Smrg    
319811bf0794Smrg    It would probably result in a black screen.
319911bf0794Smrg    
320011bf0794Smrg    (Ported from radeon commit 1351e48efe7a2c28eab447e16f36a00fbd02ae48)
320111bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
320211bf0794Smrg
320311bf0794Smrgcommit 53926db2355de0a324c205703a0377b498136f65
320411bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
320511bf0794SmrgDate:   Thu Mar 2 17:08:19 2017 +0900
320611bf0794Smrg
320711bf0794Smrg    Fix flip event data leak if calloc or drmModeAddFB fails
320811bf0794Smrg    
320911bf0794Smrg    (Ported from radeon commit 481394e3c9f9f7d88bb66fe9ae8834c87952a8ab)
321011bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
321111bf0794Smrg
321211bf0794Smrgcommit 45a8ec6257c370eecf43b6b8010863e37b704872
321311bf0794SmrgAuthor: Mihail Konev <k.mvc@ya.ru>
321411bf0794SmrgDate:   Thu Mar 2 17:04:36 2017 +0900
321511bf0794Smrg
321611bf0794Smrg    autogen: add default patch prefix
321711bf0794Smrg    
321811bf0794Smrg    (Ported from radeon commit 8e6a4e96b7b27559e186f71b5547abb0a80b96dd)
321911bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
322011bf0794Smrg
322111bf0794Smrgcommit ba2aa0a8c12a2bea1e8be01ca3134b518d4cb0f2
322211bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
322311bf0794SmrgDate:   Thu Mar 2 16:55:38 2017 +0900
322411bf0794Smrg
322511bf0794Smrg    Handle rotation in the driver also with Xorg 1.12-1.18
322611bf0794Smrg    
322711bf0794Smrg    We cannot use the HW cursor in that case, but in turn we get more
322811bf0794Smrg    efficient and less teary updates of rotated outputs.
322911bf0794Smrg    
323011bf0794Smrg    (Ported from radeon commit f2bc882f1c1082bed9f496cfab6c8f07a76bc122)
323111bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
323211bf0794Smrg
323311bf0794Smrgcommit 7f3abf35a2e1225ffd6a777b23f6a7a6355c1691
323411bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
323511bf0794SmrgDate:   Thu Mar 2 16:47:06 2017 +0900
323611bf0794Smrg
323711bf0794Smrg    Fold drmmode_crtc_scanout_allocate into drmmode_crtc_scanout_create
323811bf0794Smrg    
323911bf0794Smrg    Not used anywhere else anymore.
324011bf0794Smrg    
324111bf0794Smrg    (Ported from radeon commit ae921a3150f69c38b5b3c88a9e37d54fdf0d5093)
324211bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
324311bf0794Smrg
324411bf0794Smrgcommit 03c2db3c67bf5ad3c0744add9e0bb611b6cd3df7
324511bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
324611bf0794SmrgDate:   Thu Mar 2 16:42:04 2017 +0900
324711bf0794Smrg
324811bf0794Smrg    Call drmmode_crtc_scanout_create in drmmode_crtc_shadow_allocate as well
324911bf0794Smrg    
325011bf0794Smrg    Calling drmmode_crtc_scanout_allocate in drmmode_crtc_shadow_allocate
325111bf0794Smrg    resulted in drmmode_crtc_scanout_create called from
325211bf0794Smrg    drmmode_crtc_shadow_create passing an uninitialized pitch value to
325311bf0794Smrg    drmmode_create_bo_pixmap.
325411bf0794Smrg    
325511bf0794Smrg    Fixes issues such as failure to allocate the scanout pixmap or visual
325611bf0794Smrg    corruption and GPUVM faults when attempting to use rotation with Xorg
325711bf0794Smrg    <1.19.
325811bf0794Smrg    
325911bf0794Smrg    Bugzilla: https://bugs.freedesktop.org/99916
326011bf0794Smrg    Fixes: 5f7123808833 ("Pass pitch from drmmode_crtc_scanout_allocate to
326111bf0794Smrg                          drmmode_create_bo_pixmap")
326211bf0794Smrg    (Ported from radeon commit 987a34adb319923ad36e2b47a26837248f187c3e)
326311bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
326411bf0794Smrg
326511bf0794Smrgcommit 49b092563cb3958911d28a006f155b4f4e38ed73
326611bf0794SmrgAuthor: Emil Velikov <emil.l.velikov@gmail.com>
326711bf0794SmrgDate:   Thu Jan 26 11:10:12 2017 +0900
326811bf0794Smrg
326911bf0794Smrg    autogen.sh: use quoted string variables
327011bf0794Smrg    
327111bf0794Smrg    Place quotes around the $srcdir, $ORIGDIR and $0 variables to prevent
327211bf0794Smrg    fall-outs, when they contain space.
327311bf0794Smrg    
327411bf0794Smrg    Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
327511bf0794Smrg    Reviewed-by: Peter Hutterer <peter.hutterer@who-t.net>
327611bf0794Smrg    Signed-off-by: Peter Hutterer <peter.hutterer@who-t.net>
327711bf0794Smrg
327811bf0794Smrgcommit 457fcc5935c659aab5b88cf26d065180b47ed632
327911bf0794SmrgAuthor: Peter Hutterer <peter.hutterer@who-t.net>
328011bf0794SmrgDate:   Thu Jan 26 11:09:07 2017 +0900
328111bf0794Smrg
328211bf0794Smrg    autogen.sh: use exec instead of waiting for configure to finish
328311bf0794Smrg    
328411bf0794Smrg    Syncs the invocation of configure with the one from the server.
328511bf0794Smrg    
328611bf0794Smrg    Signed-off-by: Peter Hutterer <peter.hutterer@who-t.net>
328711bf0794Smrg    Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
328811bf0794Smrg
328911bf0794Smrgcommit 5f712380883357d03c9934a753ef302e109aeb14
329011bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
329111bf0794SmrgDate:   Fri Jan 6 17:42:25 2017 +0900
329211bf0794Smrg
329311bf0794Smrg    Pass pitch from drmmode_crtc_scanout_allocate to drmmode_create_bo_pixmap
329411bf0794Smrg    
329511bf0794Smrg    Mostly to align with radeon commit
329611bf0794Smrg    ea30d856ba5e7274c8ea499293b8b0e721b8e082, but also gets rid of a
329711bf0794Smrg    gbm_bo_get_stride call.
329811bf0794Smrg    
329911bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
330011bf0794Smrg
330111bf0794Smrgcommit b5c189473dba2cffc9e4df310ce5c86ceca99a94
330211bf0794SmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com>
330311bf0794SmrgDate:   Tue Dec 13 12:32:39 2016 +0900
330411bf0794Smrg
330511bf0794Smrg    Use render node for DRI3 if available
330611bf0794Smrg    
330711bf0794Smrg    Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
330811bf0794Smrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
330911bf0794Smrg    [ Second attempt, let's see if there's any fallout this time... ]
331011bf0794Smrg
331111bf0794Smrgcommit edd276185d42962a13faf9ec9eeebc754ef284e7
331211bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
331311bf0794SmrgDate:   Thu Dec 15 12:42:44 2016 +0900
331411bf0794Smrg
331511bf0794Smrg    Simplify drmmode_handle_uevents
331611bf0794Smrg    
331711bf0794Smrg    No functional change intended.
331811bf0794Smrg    
331911bf0794Smrg    Reviewed-by: Jim Qu <Jim.Qu@amd.com>
332011bf0794Smrg
332111bf0794Smrgcommit 732cf4d3a248b288532ad0f3443da49e08dc7507
332211bf0794SmrgAuthor: jimqu <Jim.Qu@amd.com>
332311bf0794SmrgDate:   Tue Dec 13 16:33:26 2016 +0800
332411bf0794Smrg
332511bf0794Smrg    udev_monitor_receive_device() will block when hotplug monitor
332611bf0794Smrg    
332711bf0794Smrg    udev_monitor_receive_device() will block and wait for the event of udev
332811bf0794Smrg    use select() to ensure that this will not block.
332911bf0794Smrg    
333011bf0794Smrg    Signed-off-by: JimQu <Jim.Qu@amd.com>
333111bf0794Smrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
333211bf0794Smrg
333311bf0794Smrgcommit d60ea478cf2215ded7e1acf5817a0dae07e54026
333411bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
333511bf0794SmrgDate:   Wed Nov 30 16:28:27 2016 +0900
333611bf0794Smrg
333711bf0794Smrg    Call amdgpu_drm_abort_entry on failure to flip to a scanout pixmap
333811bf0794Smrg    
333911bf0794Smrg    Fixes leaking the corresponding struct amdgpu_drm_queue list entry in
334011bf0794Smrg    that case.
334111bf0794Smrg    
334211bf0794Smrg    (Ported from radeon commit e2942449171fe628a7726e59bcaab65e27d88563)
334311bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
334411bf0794Smrg
334511bf0794Smrgcommit aea70298ef0d53fc81aa1fd22c8566920a856223
334611bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
334711bf0794SmrgDate:   Wed Nov 30 16:27:10 2016 +0900
334811bf0794Smrg
334911bf0794Smrg    Call ValidateGC after ChangeClip in amdgpu_sync_scanout_pixmaps
335011bf0794Smrg    
335111bf0794Smrg    The wrong order meant that the clipping region wasn't actually applied,
335211bf0794Smrg    so it always copied the full contents from the other scanout pixmap.
335311bf0794Smrg    
335411bf0794Smrg    (Ported from radeon commit 14c3f59f5157885ad8f941f0bad6c0c5e3db12f8)
335511bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
335611bf0794Smrg
335711bf0794Smrgcommit 0f79c30619168c6845b143c6ed94ade307383068
335811bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
335911bf0794SmrgDate:   Wed Nov 30 16:25:52 2016 +0900
336011bf0794Smrg
336111bf0794Smrg    Fix amdgpu_scanout_extents_intersect for GPU screens
336211bf0794Smrg    
336311bf0794Smrg    Fixes incorrect screen updates with TearFree enabled on PRIME slave
336411bf0794Smrg    outputs which are not located at (0, 0).
336511bf0794Smrg    
336611bf0794Smrg    (Ported from radeon commit a995f5830916a0fee5126263d1bfe48632be3a15)
336711bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
336811bf0794Smrg
336911bf0794Smrgcommit 082b6b8ca1878f4b7ab0b25d16b85ba40748ac57
337011bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
337111bf0794SmrgDate:   Wed Nov 30 16:21:28 2016 +0900
337211bf0794Smrg
337311bf0794Smrg    Take current scanout_id into account everywhere involved with TearFree
337411bf0794Smrg    
337511bf0794Smrg    Fixes various potential issues with TearFree enabled, e.g. outputs
337611bf0794Smrg    freezing after display configuration changes.
337711bf0794Smrg    
337811bf0794Smrg    (Ported from radeon commit e543ef3a2fb304cbe3a965fb780632af2e4186f4)
337911bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
338011bf0794Smrg
338111bf0794Smrgcommit 82729b1f3b9d57f3002ac2689bfbf37ece0bc3f2
338211bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
338311bf0794SmrgDate:   Mon Nov 28 17:47:17 2016 +0900
338411bf0794Smrg
338511bf0794Smrg    Add amdgpu_is_gpu_screen helper
338611bf0794Smrg    
338711bf0794Smrg    This will hopefully decrease the chance of accidentally breaking the
338811bf0794Smrg    build against xserver < 1.13 in the future.
338911bf0794Smrg    
339011bf0794Smrg    (Ported from radeon commit f130b10e63f7526360b41aa0918b4940f63f662a)
339111bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
339211bf0794Smrg
339311bf0794Smrgcommit 7fe2a8ed67ef82916a1eb5b241c5a602a26e10b2
339411bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
339511bf0794SmrgDate:   Tue Nov 22 16:50:59 2016 +0900
339611bf0794Smrg
339711bf0794Smrg    Don't install Flush/EventCallback for GPU screens
339811bf0794Smrg    
339911bf0794Smrg    Their purpose is to flush GPU rendering commands corresponding to damage
340011bf0794Smrg    events, but there can be no damage events corresponding to GPU screen
340111bf0794Smrg    rendering operations.
340211bf0794Smrg    
340311bf0794Smrg    (Ported from radeon commits 13c6bc5e382765fe567091e1c616c0a26eec04ca and
340411bf0794Smrg    487aa62a2a23b86e4ea4714fdfd465c9e513141f)
340511bf0794Smrg    
340611bf0794Smrg    v2: Squash in radeon fix for build against xserver < 1.13
340711bf0794Smrg    
340811bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
340911bf0794Smrg
341011bf0794Smrgcommit ff31320644b4d17b9b3f0abd612c99769d3d9643
341111bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
341211bf0794SmrgDate:   Fri Nov 25 18:34:40 2016 +0900
341311bf0794Smrg
341411bf0794Smrg    Make libdrm >= 2.4.72 requirement explicit
341511bf0794Smrg    
341611bf0794Smrg    And drop compatibility code for older versions.
341711bf0794Smrg    
341811bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
341911bf0794Smrg
342011bf0794Smrgcommit f9ba1e8fd48cd967a09c4e083b277505d08d3849
342111bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
342211bf0794SmrgDate:   Tue Nov 22 16:30:59 2016 +0900
342311bf0794Smrg
342411bf0794Smrg    Use DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags when available
342511bf0794Smrg    
342611bf0794Smrg    (Ported from radeon commits 1106b2f773ad0611c729b27f4c192a26b43ef1e7
342711bf0794Smrg    and 5fea5ef2f07eee4a0f94baab427010b936f1d4b4)
342811bf0794Smrg    
342911bf0794Smrg    v2:
343011bf0794Smrg    * Squash in radeon fix for TearFree regression
343111bf0794Smrg    * Remove preprocessor guards for compatibility with libdrm < 2.4.72
343211bf0794Smrg      (Emil Velikov)
343311bf0794Smrg    
343411bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
343511bf0794Smrg
343611bf0794Smrgcommit e8aa4e7ea59f00d5527654b7181a05aab8c78928
343711bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
343811bf0794SmrgDate:   Wed Oct 26 18:38:20 2016 +0900
343911bf0794Smrg
344011bf0794Smrg    Remove generated header files
344111bf0794Smrg    
344211bf0794Smrg    No longer used.
344311bf0794Smrg    
344411bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
344511bf0794Smrg
344611bf0794Smrgcommit d69fd22b6d13052d667929a0e3db61829ce1396e
344711bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
344811bf0794SmrgDate:   Wed Oct 26 18:36:18 2016 +0900
344911bf0794Smrg
345011bf0794Smrg    Stop using AMDGPU(Unique)Chipsets
345111bf0794Smrg    
345211bf0794Smrg    Use libdrm_amdgpu's amdgpu_get_marketing_name for the chipset name, or
345311bf0794Smrg    "Unknown AMD Radeon GPU" as a fallback.
345411bf0794Smrg    
345511bf0794Smrg    v2: Require libdrm_amdgpu >= 2.4.72 for amdgpu_get_marketing_name
345611bf0794Smrg    
345711bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
345811bf0794Smrg
345911bf0794Smrgcommit 8a5ff54af32a75ae56d3369a828a50ae28dd1acd
346011bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
346111bf0794SmrgDate:   Wed Oct 26 18:09:18 2016 +0900
346211bf0794Smrg
346311bf0794Smrg    Stop using AMDGPUPciChipsets
346411bf0794Smrg    
346511bf0794Smrg    Not actually used by Xorg.
346611bf0794Smrg    
346711bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
346811bf0794Smrg
346911bf0794Smrgcommit 298eaf58a57efa6acc53d374eea239b6bb55c0f8
347011bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
347111bf0794SmrgDate:   Wed Oct 26 18:05:58 2016 +0900
347211bf0794Smrg
347311bf0794Smrg    Remove amdpciids.h
347411bf0794Smrg    
347511bf0794Smrg    Not useful anymore.
347611bf0794Smrg    
347711bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
347811bf0794Smrg
347911bf0794Smrgcommit a0881d55fe80d639d31cdfeadd6014322c037791
348011bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
348111bf0794SmrgDate:   Wed Oct 26 18:02:39 2016 +0900
348211bf0794Smrg
348311bf0794Smrg    Stop using generated amdgpu_device_match
348411bf0794Smrg    
348511bf0794Smrg    Just match on PCI device ID 0x1002.
348611bf0794Smrg    
348711bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
348811bf0794Smrg
348911bf0794Smrgcommit 40ddc52b2ae32b17ef7eea1602fdf59b63f06f17
349011bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
349111bf0794SmrgDate:   Wed Oct 26 17:42:36 2016 +0900
349211bf0794Smrg
349311bf0794Smrg    Use family information from libdrm_amdgpu / kernel
349411bf0794Smrg    
349511bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
349611bf0794Smrg
349711bf0794Smrgcommit 5c9d1c5097e326c69f1be4427c62a0d348e8a4a6
349811bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
349911bf0794SmrgDate:   Wed Oct 26 17:32:56 2016 +0900
350011bf0794Smrg
350111bf0794Smrg    Move struct amdgpu_gpu_info out of amdgpu_get_tile_config
350211bf0794Smrg    
350311bf0794Smrg    Preparation for the following change, no functional change intended.
350411bf0794Smrg    
350511bf0794Smrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
350611bf0794Smrg
350711bf0794Smrgcommit adf7dabdf9c8acd674190e25050b0885a05d0e92
350811bf0794SmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
350911bf0794SmrgDate:   Mon Nov 21 17:50:22 2016 +0900
351011bf0794Smrg
351111bf0794Smrg    Post-release version bump
351211bf0794Smrg
3513504d986fSmrgcommit a00032050873fc99f3ceaa3293468dad1d94d4b1
3514504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3515504d986fSmrgDate:   Thu Nov 17 15:17:10 2016 +0900
3516504d986fSmrg
3517504d986fSmrg    Bump version for 1.2.0 release
3518504d986fSmrg
3519504d986fSmrgcommit a446b3af9b055056e9fb0f37069b08b979eba277
3520504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3521504d986fSmrgDate:   Thu Nov 17 15:13:59 2016 +0900
3522504d986fSmrg
3523504d986fSmrg    manpage updates for the 1.2.0 release
3524504d986fSmrg    
3525504d986fSmrg    Option "TearFree" is now effective for arbitrary transforms as well.
3526504d986fSmrg    
3527504d986fSmrg    Point to the amd-gfx mailing list instead of xorg-driver-ati.
3528504d986fSmrg
3529504d986fSmrgcommit 24e36c7044a24294d5709c0306efacc8de6df072
3530504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3531504d986fSmrgDate:   Thu Nov 10 12:30:10 2016 +0900
3532504d986fSmrg
3533504d986fSmrg    Use pAMDGPUEnt to find both screens of a GPU in amdgpu_mode_hotplug
3534504d986fSmrg    
3535504d986fSmrg    Fixes misbehaviour when hotplugging DisplayPort connectors on secondary
3536504d986fSmrg    GPUs.
3537504d986fSmrg    
3538504d986fSmrg    Fixes: 14606e127f4b ("Handle Zaphod mode correctly in amdgpu_mode_hotplug")
3539504d986fSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98626
3540504d986fSmrg    (Ported from radeon commit 9760ef33cba5795eddeda4d5c2fcbe2dcce21689)
3541504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3542504d986fSmrg
3543504d986fSmrgcommit 257be5b0853814a557a5337878a4311acbc89856
3544504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3545504d986fSmrgDate:   Thu Nov 10 12:28:03 2016 +0900
3546504d986fSmrg
3547504d986fSmrg    Refactor amdgpu_mode_hotplug
3548504d986fSmrg    
3549504d986fSmrg    Preparation for the next change, no functional change intended.
3550504d986fSmrg    
3551504d986fSmrg    (Cherry picked from radeon commit 35bec4937d89b48a79acfcb4f814b7370cb631b2)
3552504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3553504d986fSmrg
3554504d986fSmrgcommit 1352a1d2f78cb0433d421ef86bfce2a5a1646807
3555504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3556504d986fSmrgDate:   Wed Nov 2 12:35:55 2016 +0900
3557504d986fSmrg
3558504d986fSmrg    Check Xorg version at runtime instead of build time in two places
3559504d986fSmrg    
3560504d986fSmrg    This means that all possible paths can be handled as intended, no matter
3561504d986fSmrg    which Xorg version the driver happened to be compiled against.
3562504d986fSmrg    
3563504d986fSmrg    (Ported from radeon commit 350a2645a1b127227ff294c0b62d20000d0fd48a)
3564504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3565504d986fSmrg
3566504d986fSmrgcommit 5da43c5da8adc139d57d89975a52eef91a5595e1
3567504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3568504d986fSmrgDate:   Tue Nov 1 16:01:24 2016 +0900
3569504d986fSmrg
3570504d986fSmrg    Require xserver 1.10 or newer
3571504d986fSmrg    
3572504d986fSmrg    1.10.0 was released in February 2011.
3573504d986fSmrg    
3574504d986fSmrg    We've been accidentally requiring 1.10 or newer since c7d27c94cb65 ("Keep
3575504d986fSmrg    track of damage event related flushes per-client").
3576504d986fSmrg    
3577504d986fSmrg    (Ported from radeon commit 5df36de39952c3a26cb2fbc125f298139a9dd5bc)
3578504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3579504d986fSmrg
3580504d986fSmrgcommit dd4a740714e481b09312a04883aa6e0f5200ca81
3581504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3582504d986fSmrgDate:   Thu Oct 27 11:22:36 2016 +0900
3583504d986fSmrg
3584504d986fSmrg    present: Check tiling info for flips
3585504d986fSmrg    
3586504d986fSmrg    The kernel driver doesn't handle flipping between buffers with
3587504d986fSmrg    different tiling parameters correctly.
3588504d986fSmrg    
3589504d986fSmrg    Fixes display corruption with fullscreen apps using different tiling
3590504d986fSmrg    modes (e.g. due to R600_DEBUG=notiling or R600_DEBUG=no2d) via DRI3.
3591504d986fSmrg    
3592504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3593504d986fSmrg
3594504d986fSmrgcommit 3c1f4386ba7d0b6c16bdd2b2178f978f2f154ba8
3595504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3596504d986fSmrgDate:   Wed Oct 26 16:19:01 2016 +0900
3597504d986fSmrg
3598504d986fSmrg    Consume all available udev events at once
3599504d986fSmrg    
3600504d986fSmrg    We get multiple udev events for actions like docking a laptop into its
3601504d986fSmrg    station or plugging a monitor to the station. By consuming as many
3602504d986fSmrg    events as we can, we reduce the number of output re-evalutions.
3603504d986fSmrg    
3604504d986fSmrg    It depends on the timing how many events can be consumed at once.
3605504d986fSmrg    
3606504d986fSmrg    (Inspired by xserver commit 363f4273dd4aec3e26cc57ecb6c20f27e6c813d8)
3607504d986fSmrg    (Ported from radeon commit 22b5ce9548393ba2ff73ee234ecd82eeaf0ef6c4)
3608504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3609504d986fSmrg
3610504d986fSmrgcommit c87dff3257e797cfd80d208c9a612b21978ff4eb
3611504d986fSmrgAuthor: Hans de Goede <hdegoede@redhat.com>
3612504d986fSmrgDate:   Wed Oct 26 16:17:04 2016 +0900
3613504d986fSmrg
3614504d986fSmrg    PRIME: Fix swapping of provider sink / source capabilities
3615504d986fSmrg    
3616504d986fSmrg    When a card has import capability it can be an offload _sink_, not a
3617504d986fSmrg    source and vice versa for export capability.
3618504d986fSmrg    
3619504d986fSmrg    This went unnoticed sofar because most gpus have both import and export
3620504d986fSmrg    capability.
3621504d986fSmrg    
3622504d986fSmrg    Signed-off-by: Hans de Goede <hdegoede@redhat.com>
3623504d986fSmrg    (Ported from xserver commit 94a1c77259ce39ba59ad87615df39b570ffab435)
3624504d986fSmrg    (Ported from radeon commit 82d3c8f5500d2a6fb1495e217a0b79c396f1534c)
3625504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3626504d986fSmrg
3627504d986fSmrgcommit 9c4416422f2d07dbfa7c0b18beb1353f122fc1a1
3628504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3629504d986fSmrgDate:   Wed Oct 26 16:15:42 2016 +0900
3630504d986fSmrg
3631504d986fSmrg    Always call PixmapStopDirtyTracking in drmmode_set_scanout_pixmap
3632504d986fSmrg    
3633504d986fSmrg    Otherwise, we may leak screen->pixmap_dirty_list entries if
3634504d986fSmrg    drmmode_set_scanout_pixmap is called repatedly with ppix != NULL, which
3635504d986fSmrg    can happen from RRReplaceScanoutPixmap.
3636504d986fSmrg    
3637504d986fSmrg    (Inspired by xserver commit b773a9c8126222e5fed2904d012fbf917a9f22fd)
3638504d986fSmrg    (Ported from radeon commit 6c940446ddadf418ee4959e46fa552b6c1cf6704)
3639504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3640504d986fSmrg
3641504d986fSmrgcommit 0a91f11c03400e3f92a2b048505f39e7de7e87fc
3642504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3643504d986fSmrgDate:   Wed Oct 26 16:14:45 2016 +0900
3644504d986fSmrg
3645504d986fSmrg    Don't rely on randr_crtc->scanout_pixmap in drmmode_set_scanout_pixmap
3646504d986fSmrg    
3647504d986fSmrg    RRReplaceScanoutPixmap may set randr_crtc->scanout_pixmap = NULL before
3648504d986fSmrg    we get here.
3649504d986fSmrg    
3650504d986fSmrg    (Inspired by xserver commit f4c37eeee7953df1fe0e3196eda452acf0078e61)
3651504d986fSmrg    v2: Always return TRUE in the if (!ppix) block.
3652504d986fSmrg    (Cherry picked from radeon commit 61df12e2377cbb19a19ca9d5624df8959822da9f)
3653504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3654504d986fSmrg
3655504d986fSmrgcommit b37f4774880bfd0cbe50273ac0d9c539d81995f9
3656504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3657504d986fSmrgDate:   Tue Oct 25 16:30:46 2016 +0900
3658504d986fSmrg
3659504d986fSmrg    Sayōnara, AM_MAINTAINER_MODE!
3660504d986fSmrg    
3661504d986fSmrg    If --enable-maintainer-mode got lost from config.status for any reason,
3662504d986fSmrg    builds would fail in mysterious ways after changing between different
3663504d986fSmrg    Git commits.
3664504d986fSmrg    
3665504d986fSmrg    There are more reasons for dropping it in the automake manual:
3666504d986fSmrg    
3667504d986fSmrg    https://www.gnu.org/software/automake/manual/html_node/maintainer_002dmode.html
3668504d986fSmrg    
3669504d986fSmrg    I'm not aware of any reason why --disable-maintainer-mode would ever be
3670504d986fSmrg    useful with this project.
3671504d986fSmrg    
3672504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3673504d986fSmrg    (Cherry picked from radeon commit 49cf3b5032a7ce40afe514b7092440e3e19e05aa)
3674504d986fSmrg
3675504d986fSmrgcommit c8d9ad0e188d3da3a35006a00536d61e23305830
3676504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3677504d986fSmrgDate:   Wed Oct 19 18:16:47 2016 +0900
3678504d986fSmrg
3679504d986fSmrg    Order unique chipsets according to first appearance in ati_pciids.csv
3680504d986fSmrg    
3681504d986fSmrg    Instead of lexically. This makes it more likely for similar generations
3682504d986fSmrg    to be close to each other in the list of unique chipsets.
3683504d986fSmrg    
3684504d986fSmrg    (Ported from radeon commit 1ce1b1656acc6211deb2091ff7f28d51b6daf86b,
3685504d986fSmrg     plus change $numunique++ => ++$numunique to fix OLAND getting listed
3686504d986fSmrg     twice)
3687504d986fSmrg    
3688504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3689504d986fSmrg
3690504d986fSmrgcommit 7cc04035c55788261cda89a915c433c2add6cad9
3691504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3692504d986fSmrgDate:   Wed Sep 28 15:59:22 2016 +0900
3693504d986fSmrg
3694504d986fSmrg    Enable HW cursor support with PRIME slave output & Xorg > 1.18.99.901
3695504d986fSmrg    
3696504d986fSmrg    Supported since Xorg 1.18.99.2, but buggy until 1.18.99.901.
3697504d986fSmrg    
3698504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3699504d986fSmrg
3700504d986fSmrgcommit d42773eb45baff5933730e26878a0b45fcf07b65
3701504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3702504d986fSmrgDate:   Wed Sep 28 18:17:53 2016 +0900
3703504d986fSmrg
3704504d986fSmrg    Rotate and reflect cursor hotspot position for drmModeSetCursor2
3705504d986fSmrg    
3706504d986fSmrg    We were always passing the hotspot position in the X screen coordinate
3707504d986fSmrg    space, but drmModeSetCursor2 needs it in the CRTC coordinate space. The
3708504d986fSmrg    wrong hotspot position would cause the kernel driver to adjust the
3709504d986fSmrg    HW cursor position incorrectly when the hotspot position changed.
3710504d986fSmrg    
3711504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3712504d986fSmrg
3713504d986fSmrgcommit bdee9f4dd4f21015e7696e06c4b485ab2b3a16dc
3714504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3715504d986fSmrgDate:   Wed Aug 31 16:46:56 2016 +0900
3716504d986fSmrg
3717504d986fSmrg    Add support for ScreenPtr::SyncSharedPixmap
3718504d986fSmrg    
3719504d986fSmrg    This allows deferring shared pixmap updates between different drivers.
3720504d986fSmrg    
3721504d986fSmrg    (Ported from radeon commit 53be26b00e83f871f0afd39caa5a7a1d6ec4aea1)
3722504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3723504d986fSmrg
3724504d986fSmrgcommit 97d7386caf7ba53d2cf398b8a9bb65d0a2a4770a
3725504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3726504d986fSmrgDate:   Fri Sep 16 16:36:23 2016 +0900
3727504d986fSmrg
3728504d986fSmrg    Untangle HAS_XORG_CONF_DIR / --with-xorg-conf-dir lines in configure.ac
3729504d986fSmrg    
3730504d986fSmrg    $sysconfigdir used to be part of the default --with-xorg-conf-dir value,
3731504d986fSmrg    but it no longer is.
3732504d986fSmrg    
3733504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3734504d986fSmrg
3735504d986fSmrgcommit aa8a3fa2468094cd37959179e8417ba7ba0a326c
3736504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3737504d986fSmrgDate:   Fri Sep 16 15:59:16 2016 +0900
3738504d986fSmrg
3739504d986fSmrg    Fix handling of configure option --with-xorg-conf-dir
3740504d986fSmrg    
3741504d986fSmrg    There were two problems:
3742504d986fSmrg    
3743504d986fSmrg    I accidentally changed the variable name in the AC_ARG_WITH stanza from
3744504d986fSmrg    configdir to xorgconfigdir, so specifying --with-xorg-conf-dir wouldn't
3745504d986fSmrg    work correctly. Fix this back to configdir.
3746504d986fSmrg    
3747504d986fSmrg    If neither --with-xorg-conf-dir nor --prefix is specified on the command
3748504d986fSmrg    line, the $prefix variable doesn't contain "/usr/local" (the default
3749504d986fSmrg    prefix) yet at this point but "NONE". So make install would attempt to
3750504d986fSmrg    install 10-amdgpu.conf in ${DESTDIR}NONE/share/X11/xorg.conf.d/ . Fix
3751504d986fSmrg    this by leaving ${prefix} verbatim in the default value, to be resolved
3752504d986fSmrg    by make.
3753504d986fSmrg    
3754504d986fSmrg    Also print the configdir value along with the values of other similar
3755504d986fSmrg    configuration variables.
3756504d986fSmrg    
3757504d986fSmrg    Reported-by: Timo Aaltonen <tjaalton@debian.org>
3758504d986fSmrg    Reviewed-by: Julien Cristau <jcristau@debian.org>
3759504d986fSmrg
3760504d986fSmrgcommit cd3acb75718dfd42dd25d58b4e7bd4db27b659d8
3761504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3762504d986fSmrgDate:   Wed Sep 14 18:33:42 2016 +0900
3763504d986fSmrg
3764504d986fSmrg    Use --with-xorg-conf-dir=$prefix/share/X11/xorg.conf.d by default
3765504d986fSmrg    
3766504d986fSmrg    We were using the result of `pkg-config --variable=sysconfigdir
3767504d986fSmrg    xorg-server` before, which may not be inside $prefix, so make install
3768504d986fSmrg    might fail for 10-amdgpu.conf .
3769504d986fSmrg    
3770504d986fSmrg    Fixes make distcheck in that case, and possibly also 10-amdgpu.conf
3771504d986fSmrg    seemingly missing from some distribution packages.
3772504d986fSmrg    
3773504d986fSmrg    This matches what some (though not all) input drivers are doing for their
3774504d986fSmrg    xorg.conf.d snippets.
3775504d986fSmrg
3776504d986fSmrgcommit 0f8df8584ad61a3e47fe303b34cd7b0c4ed08bb0
3777504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3778504d986fSmrgDate:   Thu Sep 8 18:14:49 2016 +0900
3779504d986fSmrg
3780504d986fSmrg    Make TearFree effective with PRIME slave scanout
3781504d986fSmrg    
3782504d986fSmrg    TearFree can now prevent tearing with any possible display
3783504d986fSmrg    configuration.
3784504d986fSmrg    
3785504d986fSmrg    Note that there may still be inter-GPU tearing if the primary GPU uses
3786504d986fSmrg    a different driver.
3787504d986fSmrg    
3788504d986fSmrg    (Ported from radeon commit 38797a33117222dadbc89e5f21ed8cd5deef9bea)
3789504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3790504d986fSmrg
3791504d986fSmrgcommit d6feed2cd78fe879aba4860a6d9bc2e388b9f135
3792504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3793504d986fSmrgDate:   Thu Sep 8 17:56:24 2016 +0900
3794504d986fSmrg
3795504d986fSmrg    Synchronize scanout pixmaps for TearFree
3796504d986fSmrg    
3797504d986fSmrg    Copy the damaged areas which are still valid in the other scanout pixmap
3798504d986fSmrg    from there, then only copy the remaining damaged area from the screen
3799504d986fSmrg    pixmap.
3800504d986fSmrg    
3801504d986fSmrg    This is slightly more efficient (only needs one Damage record instead of
3802504d986fSmrg    two, and only needs to copy each screen update across PCIe once with
3803504d986fSmrg    ShadowPrimary and a discrete GPU), and will be significantly more
3804504d986fSmrg    efficient for PRIME with the following change.
3805504d986fSmrg    
3806504d986fSmrg    (Ported from radeon commit eda1f3df6aaed683036369fe8820da4dac3c2ae2)
3807504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3808504d986fSmrg
3809504d986fSmrgcommit 4927b84ec84bc0cb5055686cca6be54390f82803
3810504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3811504d986fSmrgDate:   Thu Sep 8 17:52:25 2016 +0900
3812504d986fSmrg
3813504d986fSmrg    Move up amdgpu_scanout_extents_intersect
3814504d986fSmrg    
3815504d986fSmrg    Will be needed higher up by the following changes. No functional change.
3816504d986fSmrg    
3817504d986fSmrg    (Ported from radeon commit 2f6e5fb15f1a9ce523c85550e493f8bda9d0c00f)
3818504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3819504d986fSmrg
3820504d986fSmrgcommit 1c725f63961746258f6138b47037ec18bf508d78
3821504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3822504d986fSmrgDate:   Thu Sep 8 17:45:32 2016 +0900
3823504d986fSmrg
3824504d986fSmrg    Factor out transform_region helper
3825504d986fSmrg    
3826504d986fSmrg    (Ported from radeon commit 5a57005178fc13b6f7e513458ca6dae72a3e5783)
3827504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3828504d986fSmrg
3829504d986fSmrgcommit c92842764f95fa09e145d81f80e9fa39ea8c453c
3830504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3831504d986fSmrgDate:   Thu Sep 8 17:26:18 2016 +0900
3832504d986fSmrg
3833504d986fSmrg    Only copy from screen pixmap to shared pixmap on demand for slave scanout
3834504d986fSmrg    
3835504d986fSmrg    Only copy once for each time we update the corresponding scanout pixmap.
3836504d986fSmrg    This can significantly reduce the bandwidth usage when there are
3837504d986fSmrg    frequent updates to the screen pixmap.
3838504d986fSmrg    
3839504d986fSmrg    This initial implementation only works when both the master and slave
3840504d986fSmrg    screens use this driver.
3841504d986fSmrg    
3842504d986fSmrg    (Ported from radeon commit 99232f64db52812a843cd616d263d3a6b90eef3d)
3843504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3844504d986fSmrg
3845504d986fSmrgcommit 61ceefe17fe9e6ffbaaad0e216b2bd37fd39f47d
3846504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3847504d986fSmrgDate:   Thu Sep 8 17:15:03 2016 +0900
3848504d986fSmrg
3849504d986fSmrg    Track damage accurately for RandR 1.4 slave scanout
3850504d986fSmrg    
3851504d986fSmrg    This further reduces the PCIe bandwidth usage.
3852504d986fSmrg    
3853504d986fSmrg    (Ported from radeon commit b0867063abb197b9134166706d99fcbe5f204bb5,
3854504d986fSmrg     plus leak fix from 5a57005178fc13b6f7e513458ca6dae72a3e5783)
3855504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3856504d986fSmrg
3857504d986fSmrgcommit 6d31fb124d4418e64c949bde9ed1facf95967762
3858504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3859504d986fSmrgDate:   Thu Sep 8 17:04:05 2016 +0900
3860504d986fSmrg
3861504d986fSmrg    Handle RandR 1.4 slave dirty updates via amdgpu_drm_queue
3862504d986fSmrg    
3863504d986fSmrg    This reduces PCIe bandwidth usage and tearing.
3864504d986fSmrg    
3865504d986fSmrg    (Ported from radeon commit ad0a0656dd0e74683e6d7789decba827aa29c221)
3866504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3867504d986fSmrg
3868504d986fSmrgcommit b10ecdbd89b0a60a990c78c3e53bab6c4c96fe9f
3869504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3870504d986fSmrgDate:   Thu Sep 8 16:48:59 2016 +0900
3871504d986fSmrg
3872504d986fSmrg    Use drmmode_crtc_scanout_* helpers for RandR 1.4 scanout pixmaps
3873504d986fSmrg    
3874504d986fSmrg    This should allow using multiple CRTCs via RandR 1.4 even with xserver
3875504d986fSmrg    < 1.17. It also simplifies the code a little, and paves the way for
3876504d986fSmrg    following changes.
3877504d986fSmrg    
3878504d986fSmrg    (Ported from radeon commits 4cfa4615f79f64062e5e771cd45dd7048f48b4f6
3879504d986fSmrg     and a92c27484703abc7c410b6ae0e4b8d1efbbb8e6f)
3880504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3881504d986fSmrg
3882504d986fSmrgcommit 9565981f751b0884cbfa885b8f3af3d41a965a2b
3883504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3884504d986fSmrgDate:   Wed Sep 7 18:49:54 2016 +0900
3885504d986fSmrg
3886504d986fSmrg    Wait for pending flips to complete before turning off an output or CRTC
3887504d986fSmrg    
3888504d986fSmrg    At least with older kernels, the flip may never complete otherwise,
3889504d986fSmrg    which can result in us hanging in drmmode_set_mode_major.
3890504d986fSmrg    
3891504d986fSmrg    Fixes: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-ati/+bug/1577170
3892504d986fSmrg    
3893504d986fSmrg    (Ported from radeon commits 9090309e057dc703d1a5bffd88e6cae14108cfc3,
3894504d986fSmrg     e520ce0ec0adf91ddce5c932d4b3f9477fd49304,
3895504d986fSmrg     a36fdaff40d5b4795a1400c348a80eee94892212 and
3896504d986fSmrg     4bd2d01552f18153afa03a8947b22eebf3d67c6b)
3897504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3898504d986fSmrg
3899504d986fSmrgcommit c7d27c94cb656899746898c2e55407c3e3d7cdc8
3900504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3901504d986fSmrgDate:   Wed Sep 7 18:28:23 2016 +0900
3902504d986fSmrg
3903504d986fSmrg    Keep track of damage event related flushes per-client
3904504d986fSmrg    
3905504d986fSmrg    This further reduces the compositing slowdown due to flushing overhead,
3906504d986fSmrg    by only flushing when the X server actually sends XDamageNotify events
3907504d986fSmrg    to a client, and there hasn't been a flush yet in the meantime.
3908504d986fSmrg    
3909504d986fSmrg    (Ported from radeon commit 121a6de72da5fcf9a32408eff36b2235f3dfbcfe)
3910504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3911504d986fSmrg
3912504d986fSmrgcommit 58773d1945cfa8155d8a6c5eb3f95097535604ef
3913504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3914504d986fSmrgDate:   Wed Sep 7 18:14:10 2016 +0900
3915504d986fSmrg
3916504d986fSmrg    Use EventCallback to avoid flushing every time in the FlushCallback
3917504d986fSmrg    
3918504d986fSmrg    We only need to flush for XDamageNotify events.
3919504d986fSmrg    
3920504d986fSmrg    Significantly reduces compositing slowdown due to flushing overhead, in
3921504d986fSmrg    particular with glamor.
3922504d986fSmrg    
3923504d986fSmrg    (Ported from radeon commit 9a1afbf61fbb2827c86bd86d295fa0848980d60b)
3924504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3925504d986fSmrg
3926504d986fSmrgcommit d166d04f6951f6a48d7d5ce5d31bba857fe0cb06
3927504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3928504d986fSmrgDate:   Wed Sep 7 18:03:05 2016 +0900
3929504d986fSmrg
3930504d986fSmrg    Add explicit AMDGPU_DRM_QUEUE_ERROR define
3931504d986fSmrg    
3932504d986fSmrg    Should make the amdgpu_drm_queue_alloc error handling clearer, and gets
3933504d986fSmrg    rid of a compile warning about it returning NULL.
3934504d986fSmrg    
3935504d986fSmrg    (Ported from radeon commit a37af701768b12d86868a831a79f1e02ee4968cf)
3936504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3937504d986fSmrg
3938504d986fSmrgcommit 6a1ba044c2b71081e6060d0c096917d6238f2145
3939504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3940504d986fSmrgDate:   Mon Aug 29 16:43:59 2016 +0900
3941504d986fSmrg
3942504d986fSmrg    Only list each unique chipset family once in the log file
3943504d986fSmrg    
3944504d986fSmrg    Acked-by: Christian König <christian.koenig@amd.com>
3945504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3946504d986fSmrg
3947504d986fSmrgcommit 7d050d15d49ef25e86e7abe88dafb52370715640
3948504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3949504d986fSmrgDate:   Mon Aug 29 16:13:20 2016 +0900
3950504d986fSmrg
3951504d986fSmrg    Add missing Kaveri PCI ID (1318)
3952504d986fSmrg    
3953504d986fSmrg    Found by comparing src/pcidb/ati_pciids.csv with xf86-video-ati.
3954504d986fSmrg    
3955504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3956504d986fSmrg
3957504d986fSmrgcommit aa5492660958e359bdc2107cba9a211ff988c90e
3958504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3959504d986fSmrgDate:   Mon Aug 29 15:52:48 2016 +0900
3960504d986fSmrg
3961504d986fSmrg    Add Mullins PCI IDs
3962504d986fSmrg    
3963504d986fSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97472
3964504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3965504d986fSmrg
3966504d986fSmrgcommit 73c8dc000ad6b2b53ba3aa7155f5e8f6b55623b7
3967504d986fSmrgAuthor: Qiang Yu <Qiang.Yu@amd.com>
3968504d986fSmrgDate:   Mon Aug 22 19:13:26 2016 +0800
3969504d986fSmrg
3970504d986fSmrg    DRI2: Fix amdgpu_dri2_exchange_buffers width/height copy'n'paste error
3971504d986fSmrg    
3972504d986fSmrg    Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
3973504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3974504d986fSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
3975504d986fSmrg
3976504d986fSmrgcommit 5a4d3267ac3823fe58b51b0b9075b82375d7180c
3977504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
3978504d986fSmrgDate:   Wed Aug 17 18:57:01 2016 +0900
3979504d986fSmrg
3980504d986fSmrg    Remove unused lut_r/g/b arrays from drmmode_crtc_private_rec
3981504d986fSmrg    
3982504d986fSmrg    Fixes: 1091f28e1fa2 ("Remove drmmode_load_palette")
3983504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
3984504d986fSmrg
3985504d986fSmrgcommit c4364520691d18961f0a6b77071baeeffaa80a11
3986504d986fSmrgAuthor: Marek Olšák <marek.olsak@amd.com>
3987504d986fSmrgDate:   Fri Aug 19 12:42:38 2016 +0200
3988504d986fSmrg
3989504d986fSmrg    Fix cursor size for SI
3990504d986fSmrg    
3991504d986fSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
3992504d986fSmrg    Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
3993504d986fSmrg
3994504d986fSmrgcommit 2eb5d77b841e55e7328df4b95c0d41fec30ce10f
3995504d986fSmrgAuthor: Ronie Salgado <roniesalg@gmail.com>
3996504d986fSmrgDate:   Thu Feb 11 03:00:14 2016 -0300
3997504d986fSmrg
3998504d986fSmrg    Add SI PCI IDs
3999504d986fSmrg    
4000504d986fSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
4001504d986fSmrg
4002504d986fSmrgcommit abd1a7901c95e4bc78415cf1b7923623b9177152
4003504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4004504d986fSmrgDate:   Wed Jun 29 17:54:26 2016 +0900
4005504d986fSmrg
4006504d986fSmrg    DRI2: Add interpolated_vblanks in amdgpu_dri2_get_crtc_msc
4007504d986fSmrg    
4008504d986fSmrg    We need that in amdgpu_dri2_drawable_crtc as well for priv->vblank_delta
4009504d986fSmrg    to work as intended.
4010504d986fSmrg    
4011504d986fSmrg    amdgpu_dri2_get_msc was already doing this.
4012504d986fSmrg    
4013504d986fSmrg    Fixes hangs in some cases when using VDPAU via DRI2 and moving the
4014504d986fSmrg    window between CRTCs.
4015504d986fSmrg    
4016504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4017504d986fSmrg
4018504d986fSmrgcommit 978242977e5dc905e1d5a46b1b0d34b356c7af26
4019504d986fSmrgAuthor: Qiang Yu <Qiang.Yu@amd.com>
4020504d986fSmrgDate:   Wed Jul 13 19:25:12 2016 +0800
4021504d986fSmrg
4022504d986fSmrg    Fix amdgpu_mode_hotplug crash on multi GPU platform.
4023504d986fSmrg    
4024504d986fSmrg    On multi GPU platform, some screen is created by other GPU DDX.
4025504d986fSmrg    
4026504d986fSmrg    Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
4027504d986fSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
4028504d986fSmrg
4029504d986fSmrgcommit fdd1209e26128b3e894f2867fac3a1b08fe1f29e
4030504d986fSmrgAuthor: Keith Packard <keithp@keithp.com>
4031504d986fSmrgDate:   Tue Jul 19 09:16:32 2016 -0700
4032504d986fSmrg
4033504d986fSmrg    Use NotifyFd for drm fd
4034504d986fSmrg    
4035504d986fSmrg    NotifyFd is available after API 22, and must be used after API 23.
4036504d986fSmrg    
4037504d986fSmrg    Signed-off-by: Keith Packard <keithp@keithp.com>
4038504d986fSmrg
4039504d986fSmrgcommit 17c0cf49746a20fb25610c24a40c441f88c08365
4040504d986fSmrgAuthor: Adam Jackson <ajax@redhat.com>
4041504d986fSmrgDate:   Tue Jul 19 10:03:56 2016 -0400
4042504d986fSmrg
4043504d986fSmrg    Adapt Block/WakeupHandler signature for ABI 23
4044504d986fSmrg    
4045504d986fSmrg    Signed-off-by: Adam Jackson <ajax@redhat.com>
4046504d986fSmrg
4047504d986fSmrgcommit b5e2b964b7884c205a7c0fa578e05e867c176fcc
4048504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4049504d986fSmrgDate:   Wed Jul 6 17:46:56 2016 +0900
4050504d986fSmrg
4051504d986fSmrg    Only use RandR APIs if RandR is enabled
4052504d986fSmrg    
4053504d986fSmrg    Fixes crash with Xinerama enabled, which disables RandR.
4054504d986fSmrg    
4055504d986fSmrg    Fixes: https://bugs.debian.org/827984
4056504d986fSmrg    
4057504d986fSmrg    (Ported from radeon commit 3be841d0ae7d505cef325993205b12d15e98dba9)
4058504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4059504d986fSmrg
4060504d986fSmrgcommit 84496ebc89a9973347c774c13ff6f4667fcdbe69
4061504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4062504d986fSmrgDate:   Wed Jul 6 17:43:36 2016 +0900
4063504d986fSmrg
4064504d986fSmrg    Add .editorconfig file
4065504d986fSmrg    
4066504d986fSmrg    Basically a conversion from .dir-locals.el. EditorConfig supports many
4067504d986fSmrg    more editors and IDEs.
4068504d986fSmrg    
4069504d986fSmrg    (Ported from radeon commit aa07b365d7b0610411e118f105e49daff5f5a5cf)
4070504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4071504d986fSmrg
4072504d986fSmrgcommit a576430526cbc404de64b30e1377a356644e8024
4073504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4074504d986fSmrgDate:   Fri Jun 24 16:28:25 2016 +0900
4075504d986fSmrg
4076504d986fSmrg    Clear damage in amdgpu_scanout_update if it doesn't intersect the CRTC
4077504d986fSmrg    
4078504d986fSmrg    There's no need to test that same damage again.
4079504d986fSmrg    
4080504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4081504d986fSmrg
4082504d986fSmrgcommit ede7f2bcae63be65e05e3029bfe7c742e5978932
4083504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4084504d986fSmrgDate:   Fri Jun 24 16:19:15 2016 +0900
4085504d986fSmrg
4086504d986fSmrg    Remove w/h parameters from amdgpu_scanout_extents_intersect
4087504d986fSmrg    
4088504d986fSmrg    We can use the dimensions of the CRTC's mode instead.
4089504d986fSmrg    
4090504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4091504d986fSmrg
4092504d986fSmrgcommit bf000ea7ef91f5ecb59fc3c1ab8ed9eddcc0841d
4093504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4094504d986fSmrgDate:   Thu Jun 23 17:28:16 2016 +0900
4095504d986fSmrg
4096504d986fSmrg    Make the dedicated scanout mechanism work with arbitrary transforms v2
4097504d986fSmrg    
4098504d986fSmrg    This makes TearFree work with arbitrary transforms, and makes transforms
4099504d986fSmrg    work better even without TearFree, with xserver >= 1.12.
4100504d986fSmrg    
4101504d986fSmrg    v2: Preserve clamping of transformed damage extents to CRTC boundaries.
4102504d986fSmrg    
4103504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4104504d986fSmrg
4105504d986fSmrgcommit d96dabc71b1b32dc4b422a9633cdd4e0e95da052
4106504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4107504d986fSmrgDate:   Thu Jun 23 16:27:45 2016 +0900
4108504d986fSmrg
4109504d986fSmrg    Destroy all dedicated scanout buffers during CloseScreen
4110504d986fSmrg    
4111504d986fSmrg    Fixes leaking active scanout buffers across a server reset, which also
4112504d986fSmrg    fixes server reset with glamor and active scanout buffers.
4113504d986fSmrg    
4114504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4115504d986fSmrg
4116504d986fSmrgcommit 1091f28e1fa239ee1a973d84a8376fa4a95d7247
4117504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4118504d986fSmrgDate:   Thu Jun 23 12:47:04 2016 +0900
4119504d986fSmrg
4120504d986fSmrg    Remove drmmode_load_palette
4121504d986fSmrg    
4122504d986fSmrg    Not used by any supported version of xserver.
4123504d986fSmrg    
4124504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4125504d986fSmrg
4126504d986fSmrgcommit 4d506c23c9a628204fa23607931557b07ada3e31
4127504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4128504d986fSmrgDate:   Wed Jun 22 17:16:24 2016 +0900
4129504d986fSmrg
4130504d986fSmrg    present: Separate checks for flips vs unflips v2
4131504d986fSmrg    
4132504d986fSmrg    All unflip checks apply to flips as well, but not vice versa.
4133504d986fSmrg    
4134504d986fSmrg    v2: Add comment above amdgpu_present_check_unflip (Alex)
4135504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4136504d986fSmrg
4137504d986fSmrgcommit decabd574f90d3df397c80ec931b3fde8a4afb49
4138504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4139504d986fSmrgDate:   Wed Jun 22 17:43:41 2016 +0900
4140504d986fSmrg
4141504d986fSmrg    dri2: Don't allow flipping when using a dedicated scanout buffer
4142504d986fSmrg    
4143504d986fSmrg    Fixes issues when mixing rotation and page flipping with current xserver
4144504d986fSmrg    Git master.
4145504d986fSmrg    
4146504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4147504d986fSmrg
4148504d986fSmrgcommit 3ed28ce7cd26f89969617ba901ff253091d0d469
4149504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4150504d986fSmrgDate:   Wed Jun 22 16:54:01 2016 +0900
4151504d986fSmrg
4152504d986fSmrg    present: Don't allow flipping when using a dedicated scanout buffer
4153504d986fSmrg    
4154504d986fSmrg    Fixes issues when mixing rotation and page flipping with current xserver
4155504d986fSmrg    Git master.
4156504d986fSmrg    
4157504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4158504d986fSmrg
4159504d986fSmrgcommit 9c3324715fd395fd486ea341654d78f4f298b97f
4160504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4161504d986fSmrgDate:   Wed Jun 22 16:12:32 2016 +0900
4162504d986fSmrg
4163504d986fSmrg    Make sure drmmode_crtc->scanout[] are destroyed when not needed
4164504d986fSmrg    
4165504d986fSmrg    We failed to do this when going back to scanning out directly from the
4166504d986fSmrg    screen pixmap.
4167504d986fSmrg    
4168504d986fSmrg    As a bonus, since we now destroy drmmode_crtc->scanout[] after setting
4169504d986fSmrg    the new scanout buffer, we may avoid the CRTC turning off intermittently
4170504d986fSmrg    in this case.
4171504d986fSmrg    
4172504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4173504d986fSmrg
4174504d986fSmrgcommit 3bce0519a4008cf87c0e31a7a579e10f5dcdd2f3
4175504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4176504d986fSmrgDate:   Wed Jun 22 16:19:07 2016 +0900
4177504d986fSmrg
4178504d986fSmrg    Simplify drmmode_set_mode_major error handling
4179504d986fSmrg    
4180504d986fSmrg    Initialize ret = FALSE and only set it to TRUE when we've succeeded.
4181504d986fSmrg    
4182504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4183504d986fSmrg
4184504d986fSmrgcommit a3ca1500703837cbb8d49c554199a25dea7d5e1e
4185504d986fSmrgAuthor: Hans de Goede <hdegoede@redhat.com>
4186504d986fSmrgDate:   Wed Jun 1 15:14:32 2016 +0200
4187504d986fSmrg
4188504d986fSmrg    Only add main fb if necessary
4189504d986fSmrg    
4190504d986fSmrg    If we're doing reverse-prime; or doing rotation the main fb is not used,
4191504d986fSmrg    and there is no reason to add it in this case.
4192504d986fSmrg    
4193504d986fSmrg    Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4194504d986fSmrg    (Ported from xserver commit 4313122dea0df9affc280ee698e929489061ccc6)
4195504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4196504d986fSmrg
4197504d986fSmrgcommit 9ca1c24235ff5ab2e028333fc326e2eff008c574
4198504d986fSmrgAuthor: Hans de Goede <hdegoede@redhat.com>
4199504d986fSmrgDate:   Wed Jun 1 15:11:05 2016 +0200
4200504d986fSmrg
4201504d986fSmrg    Remove unnecessary fb addition from drmmode_xf86crtc_resize
4202504d986fSmrg    
4203504d986fSmrg    drmmode_set_mode_major() is the only user of drmmode->fb_id and will
4204504d986fSmrg    create it if necessary.
4205504d986fSmrg    
4206504d986fSmrg    Signed-off-by: Hans de Goede <hdegoede@redhat.com>
4207504d986fSmrg    (Ported from xserver commit 877453212166fdc912e0d687cdecee11aba563b5)
4208504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4209504d986fSmrg
4210504d986fSmrgcommit 0d42082108c264568e2aadd15ace70e72388bc65
4211504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4212504d986fSmrgDate:   Wed Jun 22 19:01:03 2016 +0900
4213504d986fSmrg
4214504d986fSmrg    Call amdgpu_glamor_create_screen_resources after ModifyPixmapHeader
4215504d986fSmrg    
4216504d986fSmrg    Otherwise, glamor doesn't pick up the new screen pixmap size and
4217504d986fSmrg    continues using the old size, leaving garbage in some areas after
4218504d986fSmrg    enlarging the screen.
4219504d986fSmrg    
4220504d986fSmrg    Fixes regression from commit c315c00e44afc91a7c8e2eab5af836d9643ebb88
4221504d986fSmrg    ("Propagate failure from amdgpu_set_pixmap_bo").
4222504d986fSmrg    
4223504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4224504d986fSmrg
4225504d986fSmrgcommit e7e71eabbbccdeabcae1bc6fffabc27c272090ab
4226504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4227504d986fSmrgDate:   Mon Mar 28 18:49:15 2016 +0900
4228504d986fSmrg
4229504d986fSmrg    Adapt to XF86_CRTC_VERSION 7
4230504d986fSmrg    
4231504d986fSmrg    Now the HW cursor can be used with TearFree rotation.
4232504d986fSmrg    
4233504d986fSmrg    This also allows always using the separate scanout pixmap mechanism for
4234504d986fSmrg    rotation, so that should be much smoother even without TearFree enabled.
4235504d986fSmrg    
4236504d986fSmrg    (Ported from radeon commit 7835558acdce318130ba4a09ef936fd675e3197d)
4237504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4238504d986fSmrg
4239504d986fSmrgcommit 7f7f9825caf3983902491da27c16d14cd8bf9b7d
4240504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4241504d986fSmrgDate:   Mon Jun 13 18:58:49 2016 +0900
4242504d986fSmrg
4243504d986fSmrg    Free priv in amdgpu_set_pixmap_bo also if priv->bo == NULL
4244504d986fSmrg    
4245504d986fSmrg    Fixes memory leak when destroying pixmaps with priv->bo == NULL.
4246504d986fSmrg    
4247504d986fSmrg    Reported-by: Qiang Yu <qiang.yu@amd.com>
4248504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4249504d986fSmrg
4250504d986fSmrgcommit 397aedafee437c125b8ac1feafb1c3b466842aeb
4251504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4252504d986fSmrgDate:   Mon Jun 13 18:34:11 2016 +0900
4253504d986fSmrg
4254504d986fSmrg    glamor: Fix leak of pixmap private when replacing BO
4255504d986fSmrg    
4256504d986fSmrg    Reported-by: Qiang Yu <qiang.yu@amd.com>
4257504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4258504d986fSmrg
4259504d986fSmrgcommit 5b4a8a7a6ed70a50be252fa9b34d3b3a17cdf91a
4260504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4261504d986fSmrgDate:   Tue Jun 14 19:00:18 2016 +0900
4262504d986fSmrg
4263504d986fSmrg    Use amdgpu_set_pixmap_bo in amdgpu_set_shared_pixmap_backing
4264504d986fSmrg    
4265504d986fSmrg    Fixes leaking any existing pixmap private.
4266504d986fSmrg    
4267504d986fSmrg    While we're at it, also fix leaking the GBM BO if
4268504d986fSmrg    amdgpu_glamor_create_textured_pixmap fails.
4269504d986fSmrg    
4270504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4271504d986fSmrg
4272504d986fSmrgcommit c315c00e44afc91a7c8e2eab5af836d9643ebb88
4273504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4274504d986fSmrgDate:   Wed Jun 15 17:20:36 2016 +0900
4275504d986fSmrg
4276504d986fSmrg    Propagate failure from amdgpu_set_pixmap_bo
4277504d986fSmrg    
4278504d986fSmrg    Preparation for the following fixes.
4279504d986fSmrg    
4280504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4281504d986fSmrg
4282504d986fSmrgcommit 74602c4221e3c84949fd69f690cbc66dcae384ea
4283504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4284504d986fSmrgDate:   Tue Jun 14 18:53:34 2016 +0900
4285504d986fSmrg
4286504d986fSmrg    glamor: Make amdgpu_glamor_create_textured_pixmap take amdgpu_buffer*
4287504d986fSmrg    
4288504d986fSmrg    Preparation for the following fixes.
4289504d986fSmrg    
4290504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4291504d986fSmrg
4292504d986fSmrgcommit 0007c2f018ba663303d91d847e7c085269a23062
4293504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4294504d986fSmrgDate:   Wed Jun 8 16:27:33 2016 +0900
4295504d986fSmrg
4296504d986fSmrg    glamor: Reallocate linear pixmap BO if necessary for DRI2 PRIME
4297504d986fSmrg    
4298504d986fSmrg    Fixes corruption when using DRI2 PRIME render offloading with the master
4299504d986fSmrg    screen using this driver.
4300504d986fSmrg    
4301504d986fSmrg    Reported-by: Qiang Yu <qiang.yu@amd.com>
4302504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4303504d986fSmrg    Tested-by: Qiang Yu <qiang.yu@amd.com>
4304504d986fSmrg
4305504d986fSmrgcommit 5518bf5d793439b5bab369e5fc18de9a4a3b9dd6
4306504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4307504d986fSmrgDate:   Wed Jun 8 16:44:26 2016 +0900
4308504d986fSmrg
4309504d986fSmrg    Move DRI2's local fixup_glamor helper to amdgpu_glamor_set_pixmap_bo v2
4310504d986fSmrg    
4311504d986fSmrg    So it can be used outside of the DRI2 code.
4312504d986fSmrg    
4313504d986fSmrg    v2: Keep pixmap refcnt increment in amdgpu_dri2_create_buffer2 (Qiang Yu)
4314504d986fSmrg    
4315504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4316504d986fSmrg    Tested-by: Qiang Yu <qiang.yu@amd.com> (v1)
4317504d986fSmrg
4318504d986fSmrgcommit 641f4647b7f51dfd2da330376cd10fa9702b6423
4319504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4320504d986fSmrgDate:   Wed Jun 8 16:39:10 2016 +0900
4321504d986fSmrg
4322504d986fSmrg    Consolidate get_drawable_pixmap helper
4323504d986fSmrg    
4324504d986fSmrg    There were two static helpers for the same purpose. Consolidate them
4325504d986fSmrg    into a single inline helper which can be used anywhere.
4326504d986fSmrg    
4327504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4328504d986fSmrg    Tested-by: Qiang Yu <qiang.yu@amd.com>
4329504d986fSmrg
4330504d986fSmrgcommit 8e40f190e4704c2802bf0f073f17e742786d0f18
4331504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4332504d986fSmrgDate:   Wed Jun 8 16:00:21 2016 +0900
4333504d986fSmrg
4334504d986fSmrg    Add amdgpu_pixmap_get_tiling_info
4335504d986fSmrg    
4336504d986fSmrg    Retrieves the tiling information about a pixmap BO from the kernel
4337504d986fSmrg    driver.
4338504d986fSmrg    
4339504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4340504d986fSmrg    Tested-by: Qiang Yu <qiang.yu@amd.com>
4341504d986fSmrg
4342504d986fSmrgcommit e7eeb6ad1133b6023d34b4489959ae330a8e15dd
4343504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4344504d986fSmrgDate:   Wed Jun 8 15:42:01 2016 +0900
4345504d986fSmrg
4346504d986fSmrg    Remove amdgpu_share_pixmap_backing
4347504d986fSmrg    
4348504d986fSmrg    Not used anymore.
4349504d986fSmrg    
4350504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4351504d986fSmrg    Tested-by: Qiang Yu <qiang.yu@amd.com>
4352504d986fSmrg
4353504d986fSmrgcommit b36c77695ba77b59a0ccd868454e3af4fc04d5ff
4354504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4355504d986fSmrgDate:   Wed Jun 8 15:38:57 2016 +0900
4356504d986fSmrg
4357504d986fSmrg    glamor: Fix amdgpu_glamor_share_pixmap_backing for priv->bo == NULL
4358504d986fSmrg    
4359504d986fSmrg    Fixes crash when running a compositor and DRI_PRIME client via DRI2.
4360504d986fSmrg    
4361504d986fSmrg    Reported-by: Qiang Yu <qiang.yu@amd.com>
4362504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4363504d986fSmrg    Tested-by: Qiang Yu <qiang.yu@amd.com>
4364504d986fSmrg
4365504d986fSmrgcommit 60ced5026ebc34d9f32c7618430b6a7ef7c8eb4b
4366504d986fSmrgAuthor: Alex Deucher <alexander.deucher@amd.com>
4367504d986fSmrgDate:   Tue May 17 16:59:41 2016 -0400
4368504d986fSmrg
4369504d986fSmrg    add missing bonaire pci id
4370504d986fSmrg    
4371504d986fSmrg    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4372504d986fSmrg
4373504d986fSmrgcommit 8e89448ee00da16e05e6777f34bb75d2dd6f7025
4374504d986fSmrgAuthor: Flora Cui <Flora.Cui@amd.com>
4375504d986fSmrgDate:   Tue May 17 11:02:09 2016 +0800
4376504d986fSmrg
4377504d986fSmrg    Add more Polaris 11 PCI IDs
4378504d986fSmrg    
4379504d986fSmrg    Signed-off-by: Flora Cui <Flora.Cui@amd.com>
4380504d986fSmrg    Reviewed-by: Christian König <christian.koenig@amd.com>
4381504d986fSmrg    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4382504d986fSmrg
4383504d986fSmrgcommit a59b23d64285741a7a25e314343f6261046d980f
4384504d986fSmrgAuthor: Flora Cui <Flora.Cui@amd.com>
4385504d986fSmrgDate:   Mon May 16 17:25:34 2016 +0800
4386504d986fSmrg
4387504d986fSmrg    Add more Polaris 10 PCI IDs
4388504d986fSmrg    
4389504d986fSmrg    Signed-off-by: Flora Cui <Flora.Cui@amd.com>
4390504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4391504d986fSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
4392504d986fSmrg    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4393504d986fSmrg
4394504d986fSmrgcommit 14606e127f4b6eb0b00fd42cec13d524a67e4c4a
4395504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4396504d986fSmrgDate:   Thu May 12 16:38:56 2016 +0900
4397504d986fSmrg
4398504d986fSmrg    Handle Zaphod mode correctly in amdgpu_mode_hotplug
4399504d986fSmrg    
4400504d986fSmrg    We need to scan both screens of the entity for existing connectors, and
4401504d986fSmrg    enumerate DVI & HDMI connectors consistently regardless of which screen
4402504d986fSmrg    they're assigned to.
4403504d986fSmrg    
4404504d986fSmrg    Fixes crash when hot-(un)plugging connectors in Zaphod mode.
4405504d986fSmrg    
4406504d986fSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93415
4407504d986fSmrg    (Ported from radeon commit c801f9f10a5d72d935faf21e72f7e7808fb4f05f)
4408504d986fSmrg    
4409504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4410504d986fSmrg
4411504d986fSmrgcommit 861da1d5c243f51d6c1f76e5b13e5184aa608776
4412504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4413504d986fSmrgDate:   Thu May 12 16:34:30 2016 +0900
4414504d986fSmrg
4415504d986fSmrg    Enable DRI3 by default when building for Xorg >= 1.18.3
4416504d986fSmrg    
4417504d986fSmrg    Seems to work well enough in general now.
4418504d986fSmrg    
4419504d986fSmrg    (Ported from radeon commit 1181b9c582f10b6c523e4b2988e2ce87ecf3d367)
4420504d986fSmrg    
4421504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4422504d986fSmrg
4423504d986fSmrgcommit 86f991838824494e68ac277fa27cbd88c23a5ee8
4424504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4425504d986fSmrgDate:   Tue May 10 15:57:04 2016 +0900
4426504d986fSmrg
4427504d986fSmrg    present: Support async flips
4428504d986fSmrg    
4429504d986fSmrg    The xserver Present code only calls radeon_present_flip with
4430504d986fSmrg    sync_flip=FALSE if radeon_present_screen_init sets
4431504d986fSmrg    PresentCapabilityAsync, and the latter only sets it if the kernel driver
4432504d986fSmrg    advertises support for async flips.
4433504d986fSmrg    
4434504d986fSmrg    (Ported from radeon commit 1ca677309720e2f6c953c9e76f5b34c22a4416c6)
4435504d986fSmrg    
4436504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4437504d986fSmrg
4438504d986fSmrgcommit 744ac5faff7f58e26fa76974b6bdc345ea4c7c79
4439504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4440504d986fSmrgDate:   Tue May 10 15:47:55 2016 +0900
4441504d986fSmrg
4442504d986fSmrg    Add support for async flips to radeon_do_pageflip
4443504d986fSmrg    
4444504d986fSmrg    Will be used by the next change. No functional change here.
4445504d986fSmrg    
4446504d986fSmrg    (Ported from radeon commit 90a915c62d012e99193833aecc93974e68880c60)
4447504d986fSmrg    
4448504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4449504d986fSmrg
4450504d986fSmrgcommit 4822ec7a23d2253c88bc403f17abb6d7a053528c
4451504d986fSmrgAuthor: Flora Cui <flora.cui@amd.com>
4452504d986fSmrgDate:   Tue May 10 17:14:00 2016 +0900
4453504d986fSmrg
4454504d986fSmrg    add strato pci id
4455504d986fSmrg    
4456504d986fSmrg    Signed-off-by: Flora Cui <flora.cui@amd.com>
4457504d986fSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
4458504d986fSmrg
4459504d986fSmrgcommit b93006714b8de972060492cfa311320921a73773
4460504d986fSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
4461504d986fSmrgDate:   Tue Apr 12 08:48:33 2016 -0400
4462504d986fSmrg
4463504d986fSmrg    dri3: Return NULL from amdgpu_dri3_pixmap_from_fd if calloc fails.
4464504d986fSmrg    
4465504d986fSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
4466504d986fSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
4467504d986fSmrg
4468504d986fSmrgcommit a0bbb373f902e0ffc14570c85faec7e44134f62e
4469504d986fSmrgAuthor: Qiang Yu <Qiang.Yu@amd.com>
4470504d986fSmrgDate:   Fri Apr 8 17:29:17 2016 +0800
4471504d986fSmrg
4472504d986fSmrg    Remove RR_Capability_SinkOutput for GPU without CRTC.
4473504d986fSmrg    
4474504d986fSmrg    Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
4475504d986fSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4476504d986fSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
4477504d986fSmrg
4478504d986fSmrgcommit 1a29c4bcc0a286b14f37ab942eb0cad47bc4f337
4479504d986fSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4480504d986fSmrgDate:   Mon Apr 11 16:27:40 2016 +0900
4481504d986fSmrg
4482504d986fSmrg    Post 1.1.0 release version bump
4483504d986fSmrg
4484d6c0b56eSmrgcommit a04f4015d6afef20c2b79e2779f6555836ee2b07
4485d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4486d6c0b56eSmrgDate:   Thu Apr 7 16:47:25 2016 +0900
4487d6c0b56eSmrg
4488d6c0b56eSmrg    Bump version for 1.1.0 release
4489d6c0b56eSmrg
4490d6c0b56eSmrgcommit aed1c17c43b2c0c983f6fc0973a5224d0faf32d9
4491d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4492d6c0b56eSmrgDate:   Mon Apr 4 18:28:02 2016 +0900
4493d6c0b56eSmrg
4494d6c0b56eSmrg    glamor: Force GPU rendering to/from pixmaps created via DRI3
4495d6c0b56eSmrg    
4496d6c0b56eSmrg    Fixes crash when running DRI3 clients with ShadowPrimary enabled.
4497d6c0b56eSmrg    
4498d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94799
4499d6c0b56eSmrg    
4500d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4501d6c0b56eSmrg
4502d6c0b56eSmrgcommit faf9d720b7d650f5f1ea657a874d08eac3972e60
4503d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4504d6c0b56eSmrgDate:   Fri Apr 1 16:09:51 2016 +0900
4505d6c0b56eSmrg
4506d6c0b56eSmrg    Update manpage entry for Option "TearFree"
4507d6c0b56eSmrg    
4508d6c0b56eSmrg    It's now effective for rotation as well.
4509d6c0b56eSmrg    
4510d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4511d6c0b56eSmrg
4512d6c0b56eSmrgcommit 5ba95c3abeb8df82aa8d33a47596eae6403ea7af
4513d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4514d6c0b56eSmrgDate:   Fri Apr 1 15:29:26 2016 +0900
4515d6c0b56eSmrg
4516d6c0b56eSmrg    Identify DRM event queue entries by sequence number instead of by pointer
4517d6c0b56eSmrg    
4518d6c0b56eSmrg    If the memory for an entry was allocated at the same address as that for
4519d6c0b56eSmrg    a previously cancelled entry, the handler could theoretically be called
4520d6c0b56eSmrg    prematurely, triggered by the DRM event which was submitted for the
4521d6c0b56eSmrg    cancelled entry.
4522d6c0b56eSmrg    
4523d6c0b56eSmrg    (Ported from radeon commit 4693b1bd5b5c381e8b7b68a6f7f0c6696d6a68df)
4524d6c0b56eSmrg    
4525d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4526d6c0b56eSmrg
4527d6c0b56eSmrgcommit 8ecfa69b5a833bd4c39e773a6acfd7eef9144d13
4528d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4529d6c0b56eSmrgDate:   Wed Mar 30 18:33:00 2016 +0900
4530d6c0b56eSmrg
4531d6c0b56eSmrg    DRI3: Refuse to open DRM file descriptor for ssh clients
4532d6c0b56eSmrg    
4533d6c0b56eSmrg    Fixes hangs when attempting to use DRI3 on display connections forwarded
4534d6c0b56eSmrg    via SSH.
4535d6c0b56eSmrg    
4536d6c0b56eSmrg    Don't do this for Xorg > 1.18.99.1 since the corresponding xserver
4537d6c0b56eSmrg    change has landed in Git master.
4538d6c0b56eSmrg    
4539d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93261
4540d6c0b56eSmrg    
4541d6c0b56eSmrg    (Ported from radeon commit 0b3aac1de9db42bfca545fa331e4985836682ec7)
4542d6c0b56eSmrg    
4543d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4544d6c0b56eSmrg
4545d6c0b56eSmrgcommit b2a2e114eec0967f7b67f030fbab8983cf980489
4546d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4547d6c0b56eSmrgDate:   Fri Mar 25 11:55:34 2016 +0900
4548d6c0b56eSmrg
4549d6c0b56eSmrg    Revert "Use render node for DRI3 if available"
4550d6c0b56eSmrg    
4551d6c0b56eSmrg    This reverts commit ea558e645786b08d75307716036045170e97b43e.
4552d6c0b56eSmrg    
4553d6c0b56eSmrg    It broke VDPAU<->GL interop with DRI3 enabled, because the Gallium VDPAU
4554d6c0b56eSmrg    code doesn't support DRI3 yet. We can consider re-enabling this once
4555d6c0b56eSmrg    there is a Mesa release where the Gallium VDPAU code supports DRI3.
4556d6c0b56eSmrg    
4557d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94675
4558d6c0b56eSmrg    
4559d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4560d6c0b56eSmrg
4561d6c0b56eSmrgcommit e31a2d668a1b5ebaf75d423c8123cbc8e0dcbae9
4562d6c0b56eSmrgAuthor: Flora Cui <Flora.Cui@amd.com>
4563d6c0b56eSmrgDate:   Wed Nov 18 16:44:13 2015 +0800
4564d6c0b56eSmrg
4565d6c0b56eSmrg    add polaris10 pci id
4566d6c0b56eSmrg    
4567d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
4568d6c0b56eSmrg    Signed-off-by: Flora Cui <Flora.Cui@amd.com>
4569d6c0b56eSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
4570d6c0b56eSmrg
4571d6c0b56eSmrgcommit 6e09b8deb77f76b9bb7d393cc1ad924ebba62eff
4572d6c0b56eSmrgAuthor: Flora Cui <Flora.Cui@amd.com>
4573d6c0b56eSmrgDate:   Thu Nov 5 14:16:39 2015 +0800
4574d6c0b56eSmrg
4575d6c0b56eSmrg    add polaris11 pci id
4576d6c0b56eSmrg    
4577d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
4578d6c0b56eSmrg    Signed-off-by: Flora Cui <Flora.Cui@amd.com>
4579d6c0b56eSmrg    Reviewed-By: Jammy Zhou <Jammy.Zhou@amd.com>
4580d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4581d6c0b56eSmrg
4582d6c0b56eSmrgcommit 7d32c43fff4c8df32cce150223094f793e036cf3
4583d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com>
4584d6c0b56eSmrgDate:   Wed Oct 28 17:28:23 2015 -0400
4585d6c0b56eSmrg
4586d6c0b56eSmrg    add Polaris chip families
4587d6c0b56eSmrg    
4588d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
4589d6c0b56eSmrg    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4590d6c0b56eSmrg
4591d6c0b56eSmrgcommit fbf9ae18cd241b8b78936aa30441e5fbfd9ba1c5
4592d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4593d6c0b56eSmrgDate:   Thu Mar 24 19:05:15 2016 +0900
4594d6c0b56eSmrg
4595d6c0b56eSmrg    Require xserver 1.9 or newer
4596d6c0b56eSmrg    
4597d6c0b56eSmrg    1.9.0 was released in August 2010.
4598d6c0b56eSmrg    
4599d6c0b56eSmrg    We were already unintentionally relying on things not available in 1.8
4600d6c0b56eSmrg    for at least a year, and nobody has complained.
4601d6c0b56eSmrg    
4602d6c0b56eSmrg    (Ported from radeon commit e592f32f8b5f5873fcc18b10a69dd5e4ccf11073)
4603d6c0b56eSmrg    
4604d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4605d6c0b56eSmrg
4606d6c0b56eSmrgcommit 912db5fbbc6b9b1121c8a03168cb4bd870474376
4607d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4608d6c0b56eSmrgDate:   Thu Mar 24 18:59:05 2016 +0900
4609d6c0b56eSmrg
4610d6c0b56eSmrg    Fix build against older versions of xserver
4611d6c0b56eSmrg    
4612d6c0b56eSmrg    Also slightly clean up the error handling in amdgpu_scanout_do_update.
4613d6c0b56eSmrg    
4614d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94614
4615d6c0b56eSmrg    
4616d6c0b56eSmrg    (Ported from radeon commit bde466e5d44cad64b4e4eceaa5de80fdbf86356e)
4617d6c0b56eSmrg    
4618d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4619d6c0b56eSmrg
4620d6c0b56eSmrgcommit 3fb6280ab3b104b02841c7cab8ed68c1d463c834
4621d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4622d6c0b56eSmrgDate:   Thu Mar 24 18:56:44 2016 +0900
4623d6c0b56eSmrg
4624d6c0b56eSmrg    DRI3 only works with acceleration
4625d6c0b56eSmrg    
4626d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94214
4627d6c0b56eSmrg    
4628d6c0b56eSmrg    (Ported from radeon commit d21ac4669a8b2cdd4eec5e5a94d1950b7423b8b5)
4629d6c0b56eSmrg    
4630d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4631d6c0b56eSmrg
4632d6c0b56eSmrgcommit 3177fe817a5f2de4ed10860866a0dd6d6c6ba816
4633d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4634d6c0b56eSmrgDate:   Thu Mar 24 18:51:59 2016 +0900
4635d6c0b56eSmrg
4636d6c0b56eSmrg    Check for xf86CursorResetCursor
4637d6c0b56eSmrg    
4638d6c0b56eSmrg    If it's available, Xorg calls it on each mode configuration change. It
4639d6c0b56eSmrg    does what xf86_reload_cursors does (and more), so we don't need to call
4640d6c0b56eSmrg    the latter anymore.
4641d6c0b56eSmrg    
4642d6c0b56eSmrg    (Ported from radeon commit d670c5c9851b4eff21c845d26c7d7e4eb5ee0fa9)
4643d6c0b56eSmrg    
4644d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4645d6c0b56eSmrg
4646d6c0b56eSmrgcommit a3dfce7b24e1ea01c1aa62926025a545312cbe13
4647d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4648d6c0b56eSmrgDate:   Thu Mar 24 18:45:46 2016 +0900
4649d6c0b56eSmrg
4650d6c0b56eSmrg    Don't try DRI2/Present flipping while the HW cursor can't be used
4651d6c0b56eSmrg    
4652d6c0b56eSmrg    Flipping doesn't interact correctly with SW cursor: A flip makes the SW
4653d6c0b56eSmrg    cursor disappear. It will only appear again when the cursor is moved,
4654d6c0b56eSmrg    but it will be surrounded by corruption, because the SW cursor code
4655d6c0b56eSmrg    will restore stale screen contents at the old cursor location before
4656d6c0b56eSmrg    drawing the cursor at the new location.
4657d6c0b56eSmrg    
4658d6c0b56eSmrg    (Ported from radeon commit 7f3d0780ca65a90117c2a61362dbc0899bd9c0b0)
4659d6c0b56eSmrg    
4660d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4661d6c0b56eSmrg
4662d6c0b56eSmrgcommit ba9be8f32f0321689133e17c1681809dec8c6cf1
4663d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4664d6c0b56eSmrgDate:   Thu Mar 24 18:44:30 2016 +0900
4665d6c0b56eSmrg
4666d6c0b56eSmrg    Factor out HW cursor checking code into drmmode_can_use_hw_cursor
4667d6c0b56eSmrg    
4668d6c0b56eSmrg    And add a check for RandR 1.4 multihead.
4669d6c0b56eSmrg    
4670d6c0b56eSmrg    (Ported from radeon commit 3de480e83c0a1824838d662d6d67c9fe85277298)
4671d6c0b56eSmrg    
4672d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4673d6c0b56eSmrg
4674d6c0b56eSmrgcommit 4a60b4b1851a3cbc2d8ad9048d68eeb6947cf132
4675d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4676d6c0b56eSmrgDate:   Thu Mar 24 12:03:38 2016 +0900
4677d6c0b56eSmrg
4678d6c0b56eSmrg    Call AMDGPUBlockHandler_KMS before setting initial modes
4679d6c0b56eSmrg    
4680d6c0b56eSmrg    Doing it the other way around meant that there was still a possibility
4681d6c0b56eSmrg    for the front buffer contents to be uninitialized when they start being
4682d6c0b56eSmrg    scanned out.
4683d6c0b56eSmrg    
4684d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4685d6c0b56eSmrg
4686d6c0b56eSmrgcommit 37bd79652a8ec612b94a1863e8c580b1cfaf3960
4687d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4688d6c0b56eSmrgDate:   Fri Mar 18 18:51:00 2016 +0900
4689d6c0b56eSmrg
4690d6c0b56eSmrg    present: Return rotated CRTCs from amdgpu_present_get_crtc
4691d6c0b56eSmrg    
4692d6c0b56eSmrg    Sync-to-vblank works fine with rotation. We're still checking for
4693d6c0b56eSmrg    rotation in amdgpu_present_check_flip.
4694d6c0b56eSmrg    
4695d6c0b56eSmrg    Returning NULL from here resulted in the xserver present code falling
4696d6c0b56eSmrg    back to the fake CRTC running at 1 fps.
4697d6c0b56eSmrg    
4698d6c0b56eSmrg    (Ported from radeon commit a03271de5ecdaa7790d1316e993c4450b91fe936)
4699d6c0b56eSmrg    
4700d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4701d6c0b56eSmrg
4702d6c0b56eSmrgcommit 6b930fb3285dea4a6440e31099c96f08da508d49
4703d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4704d6c0b56eSmrgDate:   Fri Mar 18 18:47:10 2016 +0900
4705d6c0b56eSmrg
4706d6c0b56eSmrg    present: Clear drmmode->fb_id before calling set_mode_major for unflip
4707d6c0b56eSmrg    
4708d6c0b56eSmrg    Without this, drmmode_set_mode_major may just re-set the FB for the
4709d6c0b56eSmrg    last flipped BO, in which case the display will probably freeze.
4710d6c0b56eSmrg    
4711d6c0b56eSmrg    Reproduction recipe: Enable rotation while a fullscreen client is
4712d6c0b56eSmrg    flipping.
4713d6c0b56eSmrg    
4714d6c0b56eSmrg    (Ported from radeon commit 40191d82370eb7e58bd34c44966cbf44c3703229)
4715d6c0b56eSmrg    
4716d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4717d6c0b56eSmrg
4718d6c0b56eSmrgcommit 6889e091442b6ba1b9351e72bd067425e87d96e9
4719d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4720d6c0b56eSmrgDate:   Fri Mar 18 18:18:04 2016 +0900
4721d6c0b56eSmrg
4722d6c0b56eSmrg    Make Option "TearFree" effective for rotated/reflected outputs as well
4723d6c0b56eSmrg    
4724d6c0b56eSmrg    Support varies by xserver version:
4725d6c0b56eSmrg    
4726d6c0b56eSmrg    < 1.12:    No support for the driver handling rotation/reflection
4727d6c0b56eSmrg    1.12-1.15: Support for driver handling rotation/reflection, but there's
4728d6c0b56eSmrg               a bug preventing the HW cursor from being visible everywhere
4729d6c0b56eSmrg               it should be on rotated outputs, so we can only support
4730d6c0b56eSmrg               TearFree for reflection.
4731d6c0b56eSmrg    >= 1.16:   While the bug above is still there (fixes pending review),
4732d6c0b56eSmrg               the driver can force SW cursor for rotated outputs, so we
4733d6c0b56eSmrg               can support TearFree for rotation as well.
4734d6c0b56eSmrg    
4735d6c0b56eSmrg    (Ported from radeon commit 798c4fd16d339b1ad5fd729cc884be084c60e38b)
4736d6c0b56eSmrg    
4737d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4738d6c0b56eSmrg
4739d6c0b56eSmrgcommit da4e0c66fcbcf63143372720e3d606a462332e3a
4740d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4741d6c0b56eSmrgDate:   Fri Mar 18 18:15:34 2016 +0900
4742d6c0b56eSmrg
4743d6c0b56eSmrg    Consolidate pScreen usage in drmmode_set_mode_major
4744d6c0b56eSmrg    
4745d6c0b56eSmrg    We were already relying on pScrn->pScreen being non-NULL in some cases,
4746d6c0b56eSmrg    which is supposedly always true ever since this function is no longer
4747d6c0b56eSmrg    getting called from ScreenInit.
4748d6c0b56eSmrg    
4749d6c0b56eSmrg    (Ported from radeon commit eb611a2e4ecce7a1ab85fd72b9b78e3269311dd5)
4750d6c0b56eSmrg    
4751d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4752d6c0b56eSmrg
4753d6c0b56eSmrgcommit 0bbf09dd7ef54133b3e534becb3ba15c0cf3eed2
4754d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4755d6c0b56eSmrgDate:   Fri Mar 18 18:14:28 2016 +0900
4756d6c0b56eSmrg
4757d6c0b56eSmrg    Remove check for XF86_CRTC_VERSION 3
4758d6c0b56eSmrg    
4759d6c0b56eSmrg    We require xserver >= 1.8, which was already at version 3.
4760d6c0b56eSmrg    
4761d6c0b56eSmrg    (Ported from radeon commit 06602171386e538081c298645fb7ca1a70fe80cc)
4762d6c0b56eSmrg    
4763d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4764d6c0b56eSmrg
4765d6c0b56eSmrgcommit 3485ca0051a224d00135d4024a97a6c4e85a9644
4766d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4767d6c0b56eSmrgDate:   Fri Mar 18 18:07:07 2016 +0900
4768d6c0b56eSmrg
4769d6c0b56eSmrg    Deal with modesets and page flips crossing on a CRTC
4770d6c0b56eSmrg    
4771d6c0b56eSmrg    If we set a mode while a flip is pending, the kernel driver may program
4772d6c0b56eSmrg    the flip to the hardware after the modeset. If that happens, the hardware
4773d6c0b56eSmrg    will display the BO from the flip, whereas we will assume it displays the
4774d6c0b56eSmrg    BO from the modeset. In other words, the display will most likely freeze,
4775d6c0b56eSmrg    at least until another modeset.
4776d6c0b56eSmrg    
4777d6c0b56eSmrg    Prevent this condition by waiting for a pending flip to finish before
4778d6c0b56eSmrg    setting a mode.
4779d6c0b56eSmrg    
4780d6c0b56eSmrg    Fixes display freezing when setting rotation or a transform with
4781d6c0b56eSmrg    TearFree enabled.
4782d6c0b56eSmrg    
4783d6c0b56eSmrg    (Ported from radeon commit a88985f5d1e39caca49ceb65678aaa9cb622a0d2)
4784d6c0b56eSmrg    
4785d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4786d6c0b56eSmrg
4787d6c0b56eSmrgcommit b9d00fa7aaf946d985897380bfa42faafbf1b3fb
4788d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4789d6c0b56eSmrgDate:   Fri Mar 18 17:18:00 2016 +0900
4790d6c0b56eSmrg
4791d6c0b56eSmrg    Make DRM event queue xf86CrtcPtr based instead of ScrnInfoPtr based
4792d6c0b56eSmrg    
4793d6c0b56eSmrg    This allows for a minor simplification of the code.
4794d6c0b56eSmrg    
4795d6c0b56eSmrg    (Ported from radeon commit f5d968cbba3c9b7ec202161f2157d8d64778c817)
4796d6c0b56eSmrg    
4797d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4798d6c0b56eSmrg
4799d6c0b56eSmrgcommit e0ed26151bfeadf309da53d001751c0a014dbd24
4800d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4801d6c0b56eSmrgDate:   Fri Mar 18 17:11:47 2016 +0900
4802d6c0b56eSmrg
4803d6c0b56eSmrg    Remove amdgpu_scanout_flip_handler
4804d6c0b56eSmrg    
4805d6c0b56eSmrg    No longer necessary now that amdgpu_drm_queue_handler can handle
4806d6c0b56eSmrg    e->handler == NULL.
4807d6c0b56eSmrg    
4808d6c0b56eSmrg    (Ported from radeon commit d5dbb07db22d5420c81dfebc060f0dd86e7b8a20)
4809d6c0b56eSmrg    
4810d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4811d6c0b56eSmrg
4812d6c0b56eSmrgcommit acd5da56f502d6ad115501e77bce06fe72b1895c
4813d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4814d6c0b56eSmrgDate:   Fri Mar 18 17:14:49 2016 +0900
4815d6c0b56eSmrg
4816d6c0b56eSmrg    DRI2: Also clear dri2_flipping when client disconnects before event
4817d6c0b56eSmrg    
4818d6c0b56eSmrg    Fixes the following problem:
4819d6c0b56eSmrg    
4820d6c0b56eSmrg    With DRI3 enabled, run glxgears with LIBGL_DRI3_DISABLE=1, make it
4821d6c0b56eSmrg    fullscreen and press Escape while it's still fullscreen. This could
4822d6c0b56eSmrg    result in dri2_flipping not getting cleared, spuriously preventing apps
4823d6c0b56eSmrg    using DRI3 from flipping.
4824d6c0b56eSmrg    
4825d6c0b56eSmrg    (Ported from radeon commit e87365117acbd80b7d80fbb5eb30890ef7153291)
4826d6c0b56eSmrg    
4827d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4828d6c0b56eSmrg
4829d6c0b56eSmrgcommit a58bfa98208cc092014d3f36a08714eb1e0d8814
4830d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4831d6c0b56eSmrgDate:   Fri Mar 18 17:07:47 2016 +0900
4832d6c0b56eSmrg
4833d6c0b56eSmrg    drm_queue: Don't abort events immediately from amdgpu_drm_abort_client
4834d6c0b56eSmrg    
4835d6c0b56eSmrg    Keep them around until the DRM event arrives, but then call the abort
4836d6c0b56eSmrg    functions instead of the handler functions.
4837d6c0b56eSmrg    
4838d6c0b56eSmrg    This is a prerequisite for the following fix.
4839d6c0b56eSmrg    
4840d6c0b56eSmrg    (Ported from radeon commit 3989766edde85d1abe7024577b98fc9b007bc02a)
4841d6c0b56eSmrg    
4842d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4843d6c0b56eSmrg
4844d6c0b56eSmrgcommit e4888df6e32bb817bf0d6166a22b19c14e189a84
4845d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4846d6c0b56eSmrgDate:   Fri Mar 18 17:04:10 2016 +0900
4847d6c0b56eSmrg
4848d6c0b56eSmrg    Fix RandR CRTC transforms
4849d6c0b56eSmrg    
4850d6c0b56eSmrg    Currently, Xorg will only transform the cursor as of the first time the
4851d6c0b56eSmrg    cursor image changes after a transform is set.
4852d6c0b56eSmrg    
4853d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80678
4854d6c0b56eSmrg    
4855d6c0b56eSmrg    (Ported from radeon commit 9483a3d777919b224f70c3b4d01e4b320a57db31)
4856d6c0b56eSmrg    
4857d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4858d6c0b56eSmrg
4859d6c0b56eSmrgcommit 43af92ede0968f2108f9562aa4c2c861ac703617
4860d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4861d6c0b56eSmrgDate:   Fri Mar 18 16:58:07 2016 +0900
4862d6c0b56eSmrg
4863d6c0b56eSmrg    Build RandR 1.4 provider name from chipset name and bus ID
4864d6c0b56eSmrg    
4865d6c0b56eSmrg    Instead of just "amdgpu", it's now e.g. "TONGA @ pci:0000:01:00.0".
4866d6c0b56eSmrg    
4867d6c0b56eSmrg    (Ported from radeon commit c7cf00487cd6d4a5d0f39d5b92ff04f6420d6a32)
4868d6c0b56eSmrg    
4869d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4870d6c0b56eSmrg
4871d6c0b56eSmrgcommit 5ec1797a2858d693d18d21326e2307d71555e1db
4872d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4873d6c0b56eSmrgDate:   Wed Feb 24 17:33:49 2016 +0900
4874d6c0b56eSmrg
4875d6c0b56eSmrg    DRI2: Use amdgpu_pixmap_get_handle
4876d6c0b56eSmrg    
4877d6c0b56eSmrg    Now we can share pixmaps with no struct amdgpu_buffer via DRI2.
4878d6c0b56eSmrg    
4879d6c0b56eSmrg    Fixes VDPAU video playback freezing when using an OpenGL compositor with
4880d6c0b56eSmrg    DRI3 enabled and mpv VAAPI hardware decoding with OpenGL output.
4881d6c0b56eSmrg    
4882d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89755
4883d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93804
4884d6c0b56eSmrg    
4885d6c0b56eSmrg    (ported from radeon commit f8b0f23e9f4af9f9097ee5e72d53b45173163c41)
4886d6c0b56eSmrg    
4887d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4888d6c0b56eSmrg
4889d6c0b56eSmrgcommit df60c635e1e632233de9dd4b01d63c2b963003f8
4890d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4891d6c0b56eSmrgDate:   Wed Feb 24 17:06:43 2016 +0900
4892d6c0b56eSmrg
4893d6c0b56eSmrg    glamor: Avoid generating GEM flink names for BOs shared via DRI3 (v2)
4894d6c0b56eSmrg    
4895d6c0b56eSmrg    We can't create our own struct amdgpu_buffer representation in this case
4896d6c0b56eSmrg    because destroying that would make the GEM handle inaccessible to glamor
4897d6c0b56eSmrg    as well. So just get the handle directly via dma-buf.
4898d6c0b56eSmrg    
4899d6c0b56eSmrg    (ported from radeon commit 391900a670addec39515f924265bfa9f8bfa9ec0,
4900d6c0b56eSmrg     extended to cache BO handles in the private for non-DRI3 pixmaps as
4901d6c0b56eSmrg     well)
4902d6c0b56eSmrg    
4903d6c0b56eSmrg    v2: Swap whole pixmap privates instead of just BOs in
4904d6c0b56eSmrg        amdgpu_dri2_exchange_buffers to avoid invalidating cached BO handles
4905d6c0b56eSmrg    
4906d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4907d6c0b56eSmrg
4908d6c0b56eSmrgcommit e463b849f3e9d7b69e64a65619a22e00e78d297b
4909d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4910d6c0b56eSmrgDate:   Tue Feb 23 18:10:29 2016 +0900
4911d6c0b56eSmrg
4912d6c0b56eSmrg    Make amdgpu_do_pageflip take a pixmap instead of a BO
4913d6c0b56eSmrg    
4914d6c0b56eSmrg    (inspired by radeon commit 7b4fc4a677d252d01c2bf80d162bc35814059eaa)
4915d6c0b56eSmrg    
4916d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4917d6c0b56eSmrg
4918d6c0b56eSmrgcommit 1ee341f9d909f3b7ba2984fc912dabdb98c34b19
4919d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4920d6c0b56eSmrgDate:   Tue Feb 23 18:42:19 2016 +0900
4921d6c0b56eSmrg
4922d6c0b56eSmrg    Add amdgpu_pixmap_get_handle helper
4923d6c0b56eSmrg    
4924d6c0b56eSmrg    (inspired by radeon commits dfad91fffb5bd013785223b42d78886df839eacf
4925d6c0b56eSmrg     and ccbda955ebae1d457d35293833f12791e0f9fb0b)
4926d6c0b56eSmrg    
4927d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4928d6c0b56eSmrg
4929d6c0b56eSmrgcommit a36bbfd98b96426bbe0be3923c64da7ec0e565d0
4930d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4931d6c0b56eSmrgDate:   Mon Feb 15 18:41:51 2016 +0900
4932d6c0b56eSmrg
4933d6c0b56eSmrg    HAS_DIRTYTRACKING_ROTATION also supports multiple CRTCs
4934d6c0b56eSmrg    
4935d6c0b56eSmrg    (ported from radeon commit ff9a6b6f079a8419f4e6fadfee778060618bf735)
4936d6c0b56eSmrg    
4937d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4938d6c0b56eSmrg
4939d6c0b56eSmrgcommit a37746ffceaed83e48e48fb05439be7e020dd2ea
4940d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4941d6c0b56eSmrgDate:   Mon Feb 15 18:35:54 2016 +0900
4942d6c0b56eSmrg
4943d6c0b56eSmrg    Load fb module before glamoregl/shadow modules
4944d6c0b56eSmrg    
4945d6c0b56eSmrg    Fixes unresolved symbols on some systems.
4946d6c0b56eSmrg    
4947d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93105
4948d6c0b56eSmrg    (ported from radeon commit 78fbca095ae9887a2d3de48bb07975e2d1126e68)
4949d6c0b56eSmrg    
4950d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4951d6c0b56eSmrg
4952d6c0b56eSmrgcommit 59c0a6807110eca829c6708e16585a38f39a5c17
4953d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4954d6c0b56eSmrgDate:   Mon Feb 15 18:28:13 2016 +0900
4955d6c0b56eSmrg
4956d6c0b56eSmrg    Don't advertise any PRIME offloading capabilities without acceleration
4957d6c0b56eSmrg    
4958d6c0b56eSmrg    Acceleration is required even for display offloading. Trying to enable
4959d6c0b56eSmrg    display offloading without acceleration resulted in a crash.
4960d6c0b56eSmrg    
4961d6c0b56eSmrg    (ported from radeon commit b19417e2fddf4df725951aea5ad5e9558338f59e)
4962d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4963d6c0b56eSmrg
4964d6c0b56eSmrgcommit a3eac85d812ecc605436e6bd5b9ee7ebf307e3d3
4965d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
4966d6c0b56eSmrgDate:   Tue Jan 26 16:12:28 2016 +0900
4967d6c0b56eSmrg
4968d6c0b56eSmrg    Only map front buffer if glamor acceleration is disabled (v2)
4969d6c0b56eSmrg    
4970d6c0b56eSmrg    Otherwise the front buffer may not be accessible by the CPU, because Mesa
4971d6c0b56eSmrg    sets the AMDGPU_GEM_CREATE_NO_CPU_ACCESS flag for tiled buffers, because
4972d6c0b56eSmrg    accessing tiled buffers with the CPU makes little sense.
4973d6c0b56eSmrg    
4974d6c0b56eSmrg    v2: Also handle Option "AccelMethod" "none"
4975d6c0b56eSmrg    
4976d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
4977d6c0b56eSmrg
4978d6c0b56eSmrgcommit 2fcb7dadd3c71cd405cbbaafc777697538ca9c29
4979d6c0b56eSmrgAuthor: jimqu <Jim.Qu@amd.com>
4980d6c0b56eSmrgDate:   Mon Jan 25 09:47:00 2016 +0800
4981d6c0b56eSmrg
4982d6c0b56eSmrg    glamor: Return NullPixmap on failure to create shareable pixmap
4983d6c0b56eSmrg    
4984d6c0b56eSmrg    If we were asked to create a shareable pixmap, it doesn't make sense
4985d6c0b56eSmrg    to return a pixmap which isn't shareable. Doing so caused trouble down
4986d6c0b56eSmrg    the line such as a crash with older versions of glamor when trying to
4987d6c0b56eSmrg    use GLX pixmaps of bpp < 32 via DRI2.
4988d6c0b56eSmrg    
4989d6c0b56eSmrg    Signed-off-by: JimQu <jim.qu@amd.com>
4990d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
4991d6c0b56eSmrg
4992d6c0b56eSmrgcommit 5269a2228bff6023c1a7f3e8534027e1d7addc25
4993d6c0b56eSmrgAuthor: jimqu <Jim.Qu@amd.com>
4994d6c0b56eSmrgDate:   Mon Jan 25 10:12:02 2016 +0800
4995d6c0b56eSmrg
4996d6c0b56eSmrg    Move amdgpu_glamor_destroy_pixmap before amdgpu_glamor_create_pixmap
4997d6c0b56eSmrg    
4998d6c0b56eSmrg    The next commit will call the former from the latter. No functional
4999d6c0b56eSmrg    change.
5000d6c0b56eSmrg    
5001d6c0b56eSmrg    Signed-off-by: JimQu <jim.qu@amd.com>
5002d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5003d6c0b56eSmrg
5004d6c0b56eSmrgcommit 54c959c163288caa87f612911b70df73f87d29d6
5005d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5006d6c0b56eSmrgDate:   Wed Jan 20 09:37:36 2016 -0500
5007d6c0b56eSmrg
5008d6c0b56eSmrg    Move memset() after variable declarations
5009d6c0b56eSmrg    
5010d6c0b56eSmrg    To make the code more "C" like move the function calls
5011d6c0b56eSmrg    after the variable declarations.
5012d6c0b56eSmrg    
5013d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5014d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5015d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5016d6c0b56eSmrg
5017d6c0b56eSmrgcommit 8853b07ae8169c409740c40d45cd335bd608f2a7
5018d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5019d6c0b56eSmrgDate:   Tue Jan 19 17:35:11 2016 +0900
5020d6c0b56eSmrg
5021d6c0b56eSmrg    Set the RandR primary output on startup if Xorg hasn't
5022d6c0b56eSmrg    
5023d6c0b56eSmrg    Fixes xrandr (XRRGetOutputPrimary) not reporting any output as primary
5024d6c0b56eSmrg    after startup.
5025d6c0b56eSmrg    
5026d6c0b56eSmrg    (Ported from radeon commit b16856b25086ffb27365ac2249b8da921066ce62)
5027d6c0b56eSmrg    
5028d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5029d6c0b56eSmrg
5030d6c0b56eSmrgcommit bd5c65daceaf633c36fcec86ff061df10c364bc0
5031d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5032d6c0b56eSmrgDate:   Thu Jan 7 15:53:41 2016 +0900
5033d6c0b56eSmrg
5034d6c0b56eSmrg    Only call amdgpu_bus_id once in each probe path (v2)
5035d6c0b56eSmrg    
5036d6c0b56eSmrg    Instead of up to twice as before.
5037d6c0b56eSmrg    
5038d6c0b56eSmrg    v2: Remove free(busIdString) call from amdgpu_kernel_mode_enabled, the
5039d6c0b56eSmrg        bus ID string is now managed by its callers.
5040d6c0b56eSmrg    
5041d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
5042d6c0b56eSmrg
5043d6c0b56eSmrgcommit 6e42c58375a4c3229da93c27bbd104af145c6163
5044d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5045d6c0b56eSmrgDate:   Thu Jan 7 15:57:38 2016 +0900
5046d6c0b56eSmrg
5047d6c0b56eSmrg    Remove pci_dev test from amdgpu_get_scrninfo
5048d6c0b56eSmrg    
5049d6c0b56eSmrg    The pci_dev parameter can never be NULL since we only support KMS.
5050d6c0b56eSmrg    
5051d6c0b56eSmrg    Reported-by: Tom St Denis <tom.stdenis@amd.com>
5052d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5053d6c0b56eSmrg
5054d6c0b56eSmrgcommit 8e09180798a06af5afa030d754938e4ca06e272f
5055d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5056d6c0b56eSmrgDate:   Thu Jan 7 15:35:35 2016 +0900
5057d6c0b56eSmrg
5058d6c0b56eSmrg    Re-use PCI bus ID code from kernel_open_fd in kernel_mode_enabled
5059d6c0b56eSmrg    
5060d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5061d6c0b56eSmrg
5062d6c0b56eSmrgcommit 4eb9cedca080b30c57ded349a397620ee7d0cd46
5063d6c0b56eSmrgAuthor: Mykola Lysenko <Mykola.Lysenko@amd.com>
5064d6c0b56eSmrgDate:   Wed Jan 13 14:03:55 2016 +0800
5065d6c0b56eSmrg
5066d6c0b56eSmrg    Initialize drmmode_crtc dpms_mode to DPMSModeOff
5067d6c0b56eSmrg    
5068d6c0b56eSmrg    This disables query of disabled pipes for drmWaitVBlank on X start
5069d6c0b56eSmrg    
5070d6c0b56eSmrg    Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
5071d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5072d6c0b56eSmrg
5073d6c0b56eSmrgcommit 1d0b0c1794e65e581a48aa9fb19679d928d82a5d
5074d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5075d6c0b56eSmrgDate:   Thu Dec 10 18:08:12 2015 +0900
5076d6c0b56eSmrg
5077d6c0b56eSmrg    sync: Check if miSyncShmScreenInit symbol is resolved at runtime
5078d6c0b56eSmrg    
5079d6c0b56eSmrg    It may be disabled in the Xorg build, either explicitly or because the
5080d6c0b56eSmrg    xshmfence library isn't available.
5081d6c0b56eSmrg    
5082d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5083d6c0b56eSmrg
5084d6c0b56eSmrgcommit f4107f67f147e2500582fc36cf0f0f76bc1ef098
5085d6c0b56eSmrgAuthor: Mykola Lysenko <Mykola.Lysenko@amd.com>
5086d6c0b56eSmrgDate:   Wed Dec 23 11:58:47 2015 -0500
5087d6c0b56eSmrg
5088d6c0b56eSmrg    Check for NULL koutput in drmmode_output_dpms
5089d6c0b56eSmrg    
5090d6c0b56eSmrg    This situation happens whit start of usage of DRM DP MST framework,
5091d6c0b56eSmrg    when connectors created and destroyed dynamically.
5092d6c0b56eSmrg    
5093d6c0b56eSmrg    Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
5094d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5095d6c0b56eSmrg
5096d6c0b56eSmrgcommit ea558e645786b08d75307716036045170e97b43e
5097d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com>
5098d6c0b56eSmrgDate:   Fri Nov 20 17:03:05 2015 +0800
5099d6c0b56eSmrg
5100d6c0b56eSmrg    Use render node for DRI3 if available
5101d6c0b56eSmrg    
5102d6c0b56eSmrg    Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
5103d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5104d6c0b56eSmrg
5105d6c0b56eSmrgcommit 43c2dc1aab682d5b6ad49d24983d6382c4f305bb
5106d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5107d6c0b56eSmrgDate:   Thu Nov 19 17:05:05 2015 +0900
5108d6c0b56eSmrg
5109d6c0b56eSmrg    glamor: Deal with glamor_egl_destroy_textured_pixmap being removed
5110d6c0b56eSmrg    
5111d6c0b56eSmrg    When it's not available, it's safe to call down to the glamor
5112d6c0b56eSmrg    DestroyPixmap hook instead.
5113d6c0b56eSmrg    
5114d6c0b56eSmrg    (ported from radeon commit 10b7c3def58bb34acc38f076bc230e25b454ab79)
5115d6c0b56eSmrg    
5116d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5117d6c0b56eSmrg
5118d6c0b56eSmrgcommit 84cab5738a315e9825bd0864c4f0fc5b03eb81a1
5119d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5120d6c0b56eSmrgDate:   Thu Nov 19 16:44:22 2015 +0900
5121d6c0b56eSmrg
5122d6c0b56eSmrg    glamor: Restore all ScreenRec hooks during CloseScreen
5123d6c0b56eSmrg    
5124d6c0b56eSmrg    (ported from radeon commit 535e5438b2c32f774b9c8c27ee0289b4749548ef)
5125d6c0b56eSmrg    
5126d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5127d6c0b56eSmrg
5128d6c0b56eSmrgcommit a00c050c2e5667ed815c51979a3cadb5146136ff
5129d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5130d6c0b56eSmrgDate:   Thu Nov 19 17:55:53 2015 +0900
5131d6c0b56eSmrg
5132d6c0b56eSmrg    Post 1.0.0 release version bump
5133d6c0b56eSmrg
5134d6c0b56eSmrgcommit 755e6ff2337cf615e3ba0854ccd533baec7144db
5135d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5136d6c0b56eSmrgDate:   Thu Nov 19 17:28:19 2015 +0900
5137d6c0b56eSmrg
5138d6c0b56eSmrg    Bump version for 1.0.0 release
5139d6c0b56eSmrg
5140d6c0b56eSmrgcommit 49c7d2be99aaf6d040e553065bdc461ce8d4769a
5141d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5142d6c0b56eSmrgDate:   Thu Nov 19 17:14:54 2015 +0900
5143d6c0b56eSmrg
5144d6c0b56eSmrg    Add amdgpu_pixmap.h to src/Makefile.am's EXTRA_DIST
5145d6c0b56eSmrg    
5146d6c0b56eSmrg    Fixes make distcheck.
5147d6c0b56eSmrg
5148d6c0b56eSmrgcommit d069ec5d27f5c8d2ab17b759b85293ef4113acf3
5149d6c0b56eSmrgAuthor: Stephen Chandler Paul <cpaul@redhat.com>
5150d6c0b56eSmrgDate:   Wed Nov 11 18:10:55 2015 +0900
5151d6c0b56eSmrg
5152d6c0b56eSmrg    Handle failures in setting a CRTC to a DRM mode properly
5153d6c0b56eSmrg    
5154d6c0b56eSmrg    This fixes a bug where running the card out of PPLL's when hotplugging
5155d6c0b56eSmrg    another monitor would result in all of the displays going blank and
5156d6c0b56eSmrg    failing to work properly until X was restarted or the user switched to
5157d6c0b56eSmrg    another VT.
5158d6c0b56eSmrg    
5159d6c0b56eSmrg    [Michel Dänzer: Pass errno instead of -ret to strerror()]
5160d6c0b56eSmrg    
5161d6c0b56eSmrg    Signed-off-by: Stephen Chandler Paul <cpaul@redhat.com>
5162d6c0b56eSmrg    (ported from radeon commit 7186a8713ba004de4991f21c1a9fc4abc62aeff4)
5163d6c0b56eSmrg    
5164d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5165d6c0b56eSmrg
5166d6c0b56eSmrgcommit c8bddcf6c97b1338be3715f1fc5e0b17ce71c195
5167d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5168d6c0b56eSmrgDate:   Wed Nov 11 18:09:59 2015 +0900
5169d6c0b56eSmrg
5170d6c0b56eSmrg    Call xf86CrtcRotate from initial drmmode_set_desired_modes call
5171d6c0b56eSmrg    
5172d6c0b56eSmrg    Fixes various problems when rotation is specified in xorg.conf.
5173d6c0b56eSmrg    
5174d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92475
5175d6c0b56eSmrg    
5176d6c0b56eSmrg    (ported from radeon commit 548e97b3b7d1e94075a54ca2bb4eb683025098a7)
5177d6c0b56eSmrg    
5178d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5179d6c0b56eSmrg
5180d6c0b56eSmrgcommit 12815156f38ce3357f03901a78402db834577d11
5181d6c0b56eSmrgAuthor: Emil Velikov <emil.l.velikov@gmail.com>
5182d6c0b56eSmrgDate:   Wed Nov 11 18:04:01 2015 +0900
5183d6c0b56eSmrg
5184d6c0b56eSmrg    Do not link amdgpu_drv.so against libpciaccess
5185d6c0b56eSmrg    
5186d6c0b56eSmrg    Not used directly.
5187d6c0b56eSmrg    
5188d6c0b56eSmrg    Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
5189d6c0b56eSmrg    (ported from radeon commit fcb32231a38f9461d12720cbf72f63502197a711)
5190d6c0b56eSmrg    
5191d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5192d6c0b56eSmrg
5193d6c0b56eSmrgcommit a02982b0ae0b79d2f183a1628edc05cafed8703a
5194d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5195d6c0b56eSmrgDate:   Wed Nov 11 17:59:14 2015 +0900
5196d6c0b56eSmrg
5197d6c0b56eSmrg    Skip disabled CRTCs in amdgpu_scanout_(do_)update
5198d6c0b56eSmrg    
5199d6c0b56eSmrg    The vblank / page flip ioctls don't work as expected for a disabled CRTC.
5200d6c0b56eSmrg    
5201d6c0b56eSmrg    (ported from radeon commit acc11877423ecd81a6e0a7f38466f80e43efee20)
5202d6c0b56eSmrg    
5203d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5204d6c0b56eSmrg
5205d6c0b56eSmrgcommit 0ddd20600d0046afd17aa47ffebe86dfd91a2215
5206d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5207d6c0b56eSmrgDate:   Wed Nov 11 17:44:16 2015 +0900
5208d6c0b56eSmrg
5209d6c0b56eSmrg    Prefer drmModeSetCursor2 over drmModeSetCursor
5210d6c0b56eSmrg    
5211d6c0b56eSmrg    The former includes information about the position of the hotspot within
5212d6c0b56eSmrg    the cursor image.
5213d6c0b56eSmrg    
5214d6c0b56eSmrg    Copied from xf86-video-modesetting.
5215d6c0b56eSmrg    
5216d6c0b56eSmrg    (ported from radeon commit c9f8f642fd495937400618a4fc25ecae3f8888fc)
5217d6c0b56eSmrg    
5218d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5219d6c0b56eSmrg
5220d6c0b56eSmrgcommit 83a47c0ebe17caa79d12a8b2f94b59cc945452f5
5221d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5222d6c0b56eSmrgDate:   Wed Nov 11 17:37:54 2015 +0900
5223d6c0b56eSmrg
5224d6c0b56eSmrg    PRIME: Don't advertise offload capabilities when acceleration is disabled
5225d6c0b56eSmrg    
5226d6c0b56eSmrg    Xorg tends to crash if the user tries to actually use the offload
5227d6c0b56eSmrg    capabilities with acceleration disabled.
5228d6c0b56eSmrg    
5229d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57200
5230d6c0b56eSmrg    (ported from radeon commit c74de9fec13fac2c836bb2a07ae6f90e1d61e667)
5231d6c0b56eSmrg    
5232d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5233d6c0b56eSmrg
5234d6c0b56eSmrgcommit 560b7fe6dc66405762020f00e9a05918a36f3a17
5235d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5236d6c0b56eSmrgDate:   Wed Nov 11 17:31:34 2015 +0900
5237d6c0b56eSmrg
5238d6c0b56eSmrg    Rename Option "NoAccel" to "Accel"
5239d6c0b56eSmrg    
5240d6c0b56eSmrg    Removes the need for a double negation when forcing acceleration on.
5241d6c0b56eSmrg    
5242d6c0b56eSmrg    Note that this change is backwards compatible, as the option parser
5243d6c0b56eSmrg    automagically handles the 'No' prefix.
5244d6c0b56eSmrg    
5245d6c0b56eSmrg    (ported from radeon commit cc615d06db0332fc6e673b55632bcc7bf957b44b)
5246d6c0b56eSmrg    
5247d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5248d6c0b56eSmrg
5249d6c0b56eSmrgcommit ad77ad32c4a723447d3191d527cfa6de9f54d7ce
5250d6c0b56eSmrgAuthor: Adam Jackson <ajax@redhat.com>
5251d6c0b56eSmrgDate:   Wed Nov 11 17:20:21 2015 +0900
5252d6c0b56eSmrg
5253d6c0b56eSmrg    Use own thunk function instead of shadowUpdatePackedWeak
5254d6c0b56eSmrg    
5255d6c0b56eSmrg    I plan to delete the Weak functions from a future server.
5256d6c0b56eSmrg    
5257d6c0b56eSmrg    Signed-off-by: Adam Jackson <ajax@redhat.com>
5258d6c0b56eSmrg    (ported from radeon commit 851b2cf8714618843725f6d067915375485ade9d)
5259d6c0b56eSmrg    
5260d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5261d6c0b56eSmrg
5262d6c0b56eSmrgcommit f5ccea99c03b62acf3a25984aba617c665d80b7c
5263d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5264d6c0b56eSmrgDate:   Wed Nov 11 17:16:58 2015 +0900
5265d6c0b56eSmrg
5266d6c0b56eSmrg    dri2: Handle PRIME for source buffer as well in amdgpu_dri2_copy_region2
5267d6c0b56eSmrg    
5268d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77810
5269d6c0b56eSmrg    
5270d6c0b56eSmrg    (ported from radeon commit c84230d686c078aac1dc98d82153f8b02521b2e1)
5271d6c0b56eSmrg    
5272d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5273d6c0b56eSmrg
5274d6c0b56eSmrgcommit 92e7c93d2f9c3036da1a17d7fccccb6f9e9eaa3d
5275d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5276d6c0b56eSmrgDate:   Mon Nov 2 18:29:24 2015 +0900
5277d6c0b56eSmrg
5278d6c0b56eSmrg    Move scrn/info declaration inside USE_GLAMOR in amdgpu_dri3_fd_from_pixmap
5279d6c0b56eSmrg    
5280d6c0b56eSmrg    Fixes warning when building with --disable-glamor:
5281d6c0b56eSmrg    
5282d6c0b56eSmrg    ../../src/amdgpu_dri3.c: In function 'amdgpu_dri3_fd_from_pixmap':
5283d6c0b56eSmrg    ../../src/amdgpu_dri3.c:135:16: warning: unused variable 'info' [-Wunused-variable]
5284d6c0b56eSmrg      AMDGPUInfoPtr info = AMDGPUPTR(scrn);
5285d6c0b56eSmrg                    ^
5286d6c0b56eSmrg    
5287d6c0b56eSmrg    Reported-by: Jammy Zhou <Jammy.Zhou@amd.com>
5288d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5289d6c0b56eSmrg
5290d6c0b56eSmrgcommit c9bd1399a13cea2e1331af2c826ca054b88db071
5291d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5292d6c0b56eSmrgDate:   Mon Nov 2 18:21:50 2015 +0900
5293d6c0b56eSmrg
5294d6c0b56eSmrg    Call AMDGPUFreeRec from AMDGPUFreeScreen_KMS even if info == NULL
5295d6c0b56eSmrg    
5296d6c0b56eSmrg    It's safe now.
5297d6c0b56eSmrg    
5298d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5299d6c0b56eSmrg
5300d6c0b56eSmrgcommit fb8444e731765588c0ff1e9053c1c7b73f5f0907
5301d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5302d6c0b56eSmrgDate:   Mon Nov 2 18:20:41 2015 +0900
5303d6c0b56eSmrg
5304d6c0b56eSmrg    Don't use AMDGPUEntPriv in AMDGPUFreeRec
5305d6c0b56eSmrg    
5306d6c0b56eSmrg    It crashes if info == NULL.
5307d6c0b56eSmrg    
5308d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5309d6c0b56eSmrg
5310d6c0b56eSmrgcommit 8e7ee03f55c2f3874f6e84daeb5700f8b8037a51
5311d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5312d6c0b56eSmrgDate:   Wed Oct 28 17:53:27 2015 +0900
5313d6c0b56eSmrg
5314d6c0b56eSmrg    Remove amdgpu_reference_drm_fd
5315d6c0b56eSmrg    
5316d6c0b56eSmrg    Increase pAMDGPUEnt->fd_ref in the probe code instead when we're reusing
5317d6c0b56eSmrg    the existing fd.
5318d6c0b56eSmrg    
5319d6c0b56eSmrg    The previous reference counting was imbalanced, so pAMDGPUEnt->fd_ref
5320d6c0b56eSmrg    could never go to 0.
5321d6c0b56eSmrg    
5322d6c0b56eSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
5323d6c0b56eSmrg
5324d6c0b56eSmrgcommit 6bab8fabb37eb131e131ce59446c214ded28f779
5325d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5326d6c0b56eSmrgDate:   Wed Oct 28 17:44:09 2015 +0900
5327d6c0b56eSmrg
5328d6c0b56eSmrg    Remove info->dri2.drm_fd and info->drmmode->fd
5329d6c0b56eSmrg    
5330d6c0b56eSmrg    Use pAMDGPUEnt->fd everywhere instead.
5331d6c0b56eSmrg    
5332d6c0b56eSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
5333d6c0b56eSmrg
5334d6c0b56eSmrgcommit 0530e39cc6b7340163e7f6bb6d82719d102ee6e9
5335d6c0b56eSmrgAuthor: Jammy Zhou <jammy.zhou@amd.com>
5336d6c0b56eSmrgDate:   Thu Oct 29 17:08:01 2015 +0900
5337d6c0b56eSmrg
5338d6c0b56eSmrg    Pass struct pci_device *pci_dev directly to amdgpu_get_scrninfo
5339d6c0b56eSmrg    
5340d6c0b56eSmrg    Instead of throwing away the type information by passing it as a void*.
5341d6c0b56eSmrg    
5342d6c0b56eSmrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
5343d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5344d6c0b56eSmrg
5345d6c0b56eSmrgcommit edf72afee3a25eae9827b4de3a013b541b78e213
5346d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com>
5347d6c0b56eSmrgDate:   Wed Oct 28 21:24:29 2015 +0800
5348d6c0b56eSmrg
5349d6c0b56eSmrg    Fix crash in PCI probe path (v4)
5350d6c0b56eSmrg    
5351d6c0b56eSmrg    The crash is caused by the NULL value returned by AMDGPUPTR(pScrn),
5352d6c0b56eSmrg    because the driverPrivate is not allocated yet in PciProbe phase,
5353d6c0b56eSmrg    and it is usually done in the PreInit phase.
5354d6c0b56eSmrg    
5355d6c0b56eSmrg    Use pAMDGPUEnt->fd instead of info->dri2.drm_fd to avoid AMDGPUInfoPtr
5356d6c0b56eSmrg    related code in amdgpu_open_drm_master, so that the crash can be fixed.
5357d6c0b56eSmrg    
5358d6c0b56eSmrg    v4: (md) Remove unused parameter entity_num, split out logically
5359d6c0b56eSmrg        separate changes
5360d6c0b56eSmrg    v3: some more cleanup
5361d6c0b56eSmrg    v2: switch to pAMDGPUEnt->fd, and update the commit message
5362d6c0b56eSmrg    
5363d6c0b56eSmrg    Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
5364d6c0b56eSmrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
5365d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v3)
5366d6c0b56eSmrg
5367d6c0b56eSmrgcommit cef725121eb0e56aa54d9c4665e36047373f4db7
5368d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5369d6c0b56eSmrgDate:   Wed Oct 28 17:56:13 2015 +0900
5370d6c0b56eSmrg
5371d6c0b56eSmrg    Remove dead code from probe paths
5372d6c0b56eSmrg    
5373d6c0b56eSmrg    amdgpu_get_scrninfo allocates the memory pointed to by pAMDGPUEnt just
5374d6c0b56eSmrg    before it calls amdgpu_open_drm_master, so pAMDGPUEnt->fd is always 0
5375d6c0b56eSmrg    in the latter.
5376d6c0b56eSmrg    
5377d6c0b56eSmrg    Also, no need to clear pAMDGPUEnt->fd just before freeing the memory
5378d6c0b56eSmrg    it's stored in.
5379d6c0b56eSmrg    
5380d6c0b56eSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
5381d6c0b56eSmrg
5382d6c0b56eSmrgcommit 3b0a3c89b53b3ebe21a9d703a4dbff6e57c65a57
5383d6c0b56eSmrgAuthor: Samuel Li <samuel.li@amd.com>
5384d6c0b56eSmrgDate:   Thu Oct 22 12:50:21 2015 -0400
5385d6c0b56eSmrg
5386d6c0b56eSmrg    Add Stoney support
5387d6c0b56eSmrg    
5388d6c0b56eSmrg    (agd): rebase
5389d6c0b56eSmrg    
5390d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5391d6c0b56eSmrg    Signed-off-by: Samuel Li <samuel.li@amd.com>
5392d6c0b56eSmrg
5393d6c0b56eSmrgcommit 9c8b7ebe15eec7abd5dc10ad6ccecbc57225494a
5394d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5395d6c0b56eSmrgDate:   Wed Oct 21 17:18:44 2015 +0900
5396d6c0b56eSmrg
5397d6c0b56eSmrg    Revert "Handle RandR CRTC transforms properly"
5398d6c0b56eSmrg    
5399d6c0b56eSmrg    This reverts commit 175251645fec1a3d19f498e1cd1e655374c67801.
5400d6c0b56eSmrg    
5401d6c0b56eSmrg    I accidentally pushed this patch.
5402d6c0b56eSmrg
5403d6c0b56eSmrgcommit 0a6ba4bf50128464a30951721b0c72e748fb89bc
5404d6c0b56eSmrgAuthor: Darren Powell <darren.powell@amd.com>
5405d6c0b56eSmrgDate:   Tue Oct 20 16:56:54 2015 -0400
5406d6c0b56eSmrg
5407d6c0b56eSmrg    Add Option "TearFree" to manpage
5408d6c0b56eSmrg    
5409d6c0b56eSmrg    This was missed in commit c57da33308a81fa575179238a0415abcb8b34908.
5410d6c0b56eSmrg    
5411d6c0b56eSmrg    Signed-off-by: Darren Powell <darren.powell@amd.com>
5412d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5413d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5414d6c0b56eSmrg
5415d6c0b56eSmrgcommit 175251645fec1a3d19f498e1cd1e655374c67801
5416d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5417d6c0b56eSmrgDate:   Thu Oct 15 16:35:51 2015 +0900
5418d6c0b56eSmrg
5419d6c0b56eSmrg    Handle RandR CRTC transforms properly
5420d6c0b56eSmrg
5421d6c0b56eSmrgcommit 6000aef4e2f0a121b94023484406fb6f04688f74
5422d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5423d6c0b56eSmrgDate:   Wed Oct 14 13:25:59 2015 -0400
5424d6c0b56eSmrg
5425d6c0b56eSmrg    Clean up amdgpu_dri2_create_buffer2()
5426d6c0b56eSmrg    
5427d6c0b56eSmrg    Remove the depth_pixmap variable from the function and clear
5428d6c0b56eSmrg    out any dead/odd behaviour that results.
5429d6c0b56eSmrg    
5430d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5431d6c0b56eSmrg
5432d6c0b56eSmrgcommit 21e72fb2418b5cc7fc849a9cf951186e209036b0
5433d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5434d6c0b56eSmrgDate:   Fri Oct 9 18:38:47 2015 +0900
5435d6c0b56eSmrg
5436d6c0b56eSmrg    Properly handle drmModeAddFB failure in drmmode_crtc_scanout_allocate
5437d6c0b56eSmrg    
5438d6c0b56eSmrg    We were printing an error message, but not propagating the failure. That
5439d6c0b56eSmrg    would probably lead to trouble down the road.
5440d6c0b56eSmrg    
5441d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5442d6c0b56eSmrg
5443d6c0b56eSmrgcommit 8da1d0c870e1081d77925807d6e3bbc61a23f54f
5444d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5445d6c0b56eSmrgDate:   Fri Oct 9 18:59:16 2015 +0900
5446d6c0b56eSmrg
5447d6c0b56eSmrg    Eliminate redundant data parameter from drmmode_crtc_scanout_create
5448d6c0b56eSmrg    
5449d6c0b56eSmrg    drmmode_crtc_scanout_create just needs to call
5450d6c0b56eSmrg    drmmode_crtc_scanout_allocate when scanout->bo is NULL.
5451d6c0b56eSmrg    
5452d6c0b56eSmrg    This makes it clearer to the reader / compiler that
5453d6c0b56eSmrg    drmmode_crtc_scanout_create doesn't dereference scanout->bo when it's
5454d6c0b56eSmrg    NULL.
5455d6c0b56eSmrg    
5456d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5457d6c0b56eSmrg
5458d6c0b56eSmrgcommit dc40582d5ff94d812cbc08f95cf14b80cd0f410d
5459d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5460d6c0b56eSmrgDate:   Wed Oct 7 16:19:22 2015 +0900
5461d6c0b56eSmrg
5462d6c0b56eSmrg    Don't advertise rotation support without hardware acceleration v2
5463d6c0b56eSmrg    
5464d6c0b56eSmrg    Rotation currently doesn't work without acceleration (doesn't actually
5465d6c0b56eSmrg    rotate with Option "NoAccel", crashes with Option "AccelMethod" "none"
5466d6c0b56eSmrg    or when glamor fails to initialize) and would probably be too slow
5467d6c0b56eSmrg    anyway.
5468d6c0b56eSmrg    
5469d6c0b56eSmrg    v2: Also remove now dead code checking for ShadowFB from
5470d6c0b56eSmrg        drmmode_crtc_scanout_allocate().
5471d6c0b56eSmrg    
5472d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5473d6c0b56eSmrg
5474d6c0b56eSmrgcommit 460560502a1bdf26d06f3c30df46fa9f28ffb9e5
5475d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5476d6c0b56eSmrgDate:   Tue Oct 6 08:49:54 2015 -0400
5477d6c0b56eSmrg
5478d6c0b56eSmrg    Simplify drmmode_set_mode_major() and avoid leaking memory.
5479d6c0b56eSmrg    
5480d6c0b56eSmrg    The function would leak the memory allocated for output_ids.  This
5481d6c0b56eSmrg    patch addresses that as well as simplifies the logic somewhat.
5482d6c0b56eSmrg    
5483d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5484d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5485d6c0b56eSmrg
5486d6c0b56eSmrgcommit 56398d6651dfc4935cbd117ad861e1800077c73c
5487d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5488d6c0b56eSmrgDate:   Tue Oct 6 08:43:12 2015 -0400
5489d6c0b56eSmrg
5490d6c0b56eSmrg    Avoid NULL dereference if drmmode_crtc_scanout_allocate fails
5491d6c0b56eSmrg    
5492d6c0b56eSmrg    This avoids a NULL dereference if the memory allocation fails.
5493d6c0b56eSmrg    
5494d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5495d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5496d6c0b56eSmrg
5497d6c0b56eSmrgcommit 4b92b960c7705be8b3a5dee17b2341864d7ca9bb
5498d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5499d6c0b56eSmrgDate:   Mon Oct 5 10:00:09 2015 -0400
5500d6c0b56eSmrg
5501d6c0b56eSmrg    cleanup the entity rec
5502d6c0b56eSmrg    
5503d6c0b56eSmrg    Based on radeon commit: b32a0a3de84a44b9af4f1ca8be19f10d7fa31b12
5504d6c0b56eSmrg    
5505d6c0b56eSmrg    Some of these were set, some of them were
5506d6c0b56eSmrg    always opposites, so clean things up.
5507d6c0b56eSmrg    
5508d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5509d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5510d6c0b56eSmrg
5511d6c0b56eSmrgcommit fe100fd6bf483228eaf64b959c56a68e8dac4447
5512d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5513d6c0b56eSmrgDate:   Mon Oct 5 10:45:33 2015 -0400
5514d6c0b56eSmrg
5515d6c0b56eSmrg    present: Handle DPMS off in radeon_present_get_ust_msc
5516d6c0b56eSmrg    
5517d6c0b56eSmrg    Based on radeon commit: 95f5d09e3667ded027ae648c97eb4737d8bf67c5
5518d6c0b56eSmrg    
5519d6c0b56eSmrg    The DRM_IOCTL_WAIT_VBLANK ioctl may return an error during DPMS off,
5520d6c0b56eSmrg    which would trigger an error message in drmmode_crtc_get_ust_msc.
5521d6c0b56eSmrg    
5522d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5523d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5524d6c0b56eSmrg
5525d6c0b56eSmrgcommit bfa925a04815cee5fd57b99447cb2ee0e158036c
5526d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5527d6c0b56eSmrgDate:   Mon Oct 5 10:10:51 2015 -0400
5528d6c0b56eSmrg
5529d6c0b56eSmrg    present: Look at all CRTCs to determine if we can flip
5530d6c0b56eSmrg    
5531d6c0b56eSmrg    Based on radeon commit 211862b777d0be251a4662f5dd24f2d400544c09
5532d6c0b56eSmrg    
5533d6c0b56eSmrg    Inspired by modesetting driver change by Kenneth Graunke.
5534d6c0b56eSmrg    
5535d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5536d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5537d6c0b56eSmrg
5538d6c0b56eSmrgcommit a1e47e76322619ed037ebce27974a4e3792940c2
5539d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5540d6c0b56eSmrgDate:   Mon Oct 5 10:41:22 2015 -0400
5541d6c0b56eSmrg
5542d6c0b56eSmrg    present: Fall back to modeset for unflip operation
5543d6c0b56eSmrg    
5544d6c0b56eSmrg    Based on radeon commit: 802d33e474a82262d9cdf11b03568b0c4929cd0d
5545d6c0b56eSmrg    
5546d6c0b56eSmrg    It's not always possible to use the page flip ioctl for this, e.g.
5547d6c0b56eSmrg    during DPMS off. We were previously just skipping the unflip in that
5548d6c0b56eSmrg    case, which could result in hangs when setting DPMS off while a
5549d6c0b56eSmrg    fullscreen Present app is running, e.g. at the GNOME3 lock screen.
5550d6c0b56eSmrg    
5551d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5552d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5553d6c0b56eSmrg
5554d6c0b56eSmrgcommit bac21dfc8e60a07f08158b13fab1f3a9b9d27d1b
5555d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5556d6c0b56eSmrgDate:   Mon Oct 5 10:37:50 2015 -0400
5557d6c0b56eSmrg
5558d6c0b56eSmrg    Don't attempt a DRI2/Present page flip while the other one is flipping
5559d6c0b56eSmrg    
5560d6c0b56eSmrg    Based on radeon commit 49f5b0bc301414df049e00d226034e3d6e56421b
5561d6c0b56eSmrg    
5562d6c0b56eSmrg    Fixes corrupted display and hangs when switching between DRI2 and DRI3
5563d6c0b56eSmrg    fullscreen apps, e.g. a compositor using DRI3 and a fullscreen app using
5564d6c0b56eSmrg    DRI2 or vice versa.
5565d6c0b56eSmrg    
5566d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5567d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5568d6c0b56eSmrg
5569d6c0b56eSmrgcommit a5f7f2e68bad1935f5ad52286033237467f77302
5570d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5571d6c0b56eSmrgDate:   Mon Oct 5 13:12:23 2015 -0400
5572d6c0b56eSmrg
5573d6c0b56eSmrg    Move amdgpu_drm_handler/abort_proc fields to drmmode_flipdata_re
5574d6c0b56eSmrg    
5575d6c0b56eSmrg    Based on radeon commit de5ddd09db82141b263338dcf0c28e01f58268ee
5576d6c0b56eSmrg    
5577d6c0b56eSmrg    Their values are the same for all DRM flip ioctl calls within a single
5578d6c0b56eSmrg    radeon_do_pageflip() call.
5579d6c0b56eSmrg    
5580d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5581d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5582d6c0b56eSmrg
5583d6c0b56eSmrgcommit e14e3560bff2537d3ad4c93d2b31442a122cde66
5584d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5585d6c0b56eSmrgDate:   Mon Oct 5 13:08:43 2015 -0400
5586d6c0b56eSmrg
5587d6c0b56eSmrg    Simplify amdgpu_do_pageflip() error handling slightly more
5588d6c0b56eSmrg    
5589d6c0b56eSmrg    Based on radeon commit e8c0f6319fbf4c3ea11e22ab1a68837031bdec8c
5590d6c0b56eSmrg    
5591d6c0b56eSmrg    We don't need the local variable old_fb_id.
5592d6c0b56eSmrg    
5593d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5594d6c0b56eSmrg    
5595d6c0b56eSmrg    [ Michel Dänzer: fix up slightly to better match radeon formatting ]
5596d6c0b56eSmrg    
5597d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5598d6c0b56eSmrg
5599d6c0b56eSmrgcommit e9621ec0e2400f62db320c560a739b29258edb87
5600d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5601d6c0b56eSmrgDate:   Mon Oct 5 09:34:47 2015 -0400
5602d6c0b56eSmrg
5603d6c0b56eSmrg    Increase robustness against DRM page flip ioctl failures
5604d6c0b56eSmrg    
5605d6c0b56eSmrg    Based on radeon commit 8fc22360d5520469c82092ccb0fcf2af330c573f
5606d6c0b56eSmrg    
5607d6c0b56eSmrg    Centralize cleanup, only clean up things that have been allocated for
5608d6c0b56eSmrg    the failed ioctl call.
5609d6c0b56eSmrg    
5610d6c0b56eSmrg    Fixes double-free after a flip ioctl failure.
5611d6c0b56eSmrg    
5612d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89681
5613d6c0b56eSmrg    
5614d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5615d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5616d6c0b56eSmrg
5617d6c0b56eSmrgcommit db3bb2061b9ac16b0922d9afae99874820356a04
5618d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5619d6c0b56eSmrgDate:   Tue Sep 29 13:07:04 2015 -0400
5620d6c0b56eSmrg
5621d6c0b56eSmrg    Clean up allocation in AMDGPUInitVideo()
5622d6c0b56eSmrg    
5623d6c0b56eSmrg    The allocation of the adapters should use the correct sizeof (even if
5624d6c0b56eSmrg    allocating an array of pointers).
5625d6c0b56eSmrg    
5626d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5627d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5628d6c0b56eSmrg
5629d6c0b56eSmrgcommit 94caf7ac777134b8396aa762a506053179bbb4c6
5630d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5631d6c0b56eSmrgDate:   Thu Oct 1 13:08:41 2015 -0400
5632d6c0b56eSmrg
5633d6c0b56eSmrg    Avoid leaking memory on output.
5634d6c0b56eSmrg    
5635d6c0b56eSmrg    Based on radeon commit 63dc36dc49f93cb00111b497ab6805194bc9d240
5636d6c0b56eSmrg    
5637d6c0b56eSmrg    and 2nd patch:
5638d6c0b56eSmrg    
5639d6c0b56eSmrg    Proper leak fix, previous leak fix was bogus.
5640d6c0b56eSmrg    
5641d6c0b56eSmrg    Based on radeon commit b8ec9ed4fe86952763b963c86f0af0dcae69aa6c
5642d6c0b56eSmrg    
5643d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5644d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5645d6c0b56eSmrg
5646d6c0b56eSmrgcommit f035faec041cb5df65c78effa58eb50197cedf88
5647d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5648d6c0b56eSmrgDate:   Thu Oct 1 12:56:05 2015 -0400
5649d6c0b56eSmrg
5650d6c0b56eSmrg    add support for DP 1.2 display hotplug
5651d6c0b56eSmrg    
5652d6c0b56eSmrg    Based on radeon commit 2f11dcd43966cf2ee26e61960fd72e6644f5e037
5653d6c0b56eSmrg    
5654d6c0b56eSmrg    > This allows for dynamic creation of conneectors when the
5655d6c0b56eSmrg    > kernel tells us.
5656d6c0b56eSmrg    >
5657d6c0b56eSmrg    > v2: fix dpms off crash
5658d6c0b56eSmrg    
5659d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5660d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5661d6c0b56eSmrg
5662d6c0b56eSmrgcommit aee72b29210d79dbf41bde6eef16d7fe817e6cf4
5663d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5664d6c0b56eSmrgDate:   Thu Oct 1 12:29:36 2015 -0400
5665d6c0b56eSmrg
5666d6c0b56eSmrg    move output name creation to its own function
5667d6c0b56eSmrg    
5668d6c0b56eSmrg    Based on radeon commit c88424d1f4aaa78b569e5d44f0b4a47de2f422f4
5669d6c0b56eSmrg    
5670d6c0b56eSmrg    > The secondary indent is deliberate to make the next patch more
5671d6c0b56eSmrg    > parseable for mst support.
5672d6c0b56eSmrg    
5673d6c0b56eSmrg    Signed-off-by:  Tom St Denis <tom.stdenis@amd.com>
5674d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5675d6c0b56eSmrg
5676d6c0b56eSmrgcommit 0846abeace649d27a5f2c17373e717f92d246797
5677d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5678d6c0b56eSmrgDate:   Thu Oct 1 12:13:21 2015 -0400
5679d6c0b56eSmrg
5680d6c0b56eSmrg    stop caching mode resources
5681d6c0b56eSmrg    
5682d6c0b56eSmrg    Based on radeon commit 32b003cb7657e07d5af6338ad44d768eda87fd33
5683d6c0b56eSmrg    
5684d6c0b56eSmrg    > This is step one towards MST connector hotplug support,
5685d6c0b56eSmrg    > it stop caching the mode resources structure, and
5686d6c0b56eSmrg    > just passes a pointer to it around.
5687d6c0b56eSmrg    
5688d6c0b56eSmrg    With a few tweaks to match the state of the AMDGPU tree.
5689d6c0b56eSmrg    
5690d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5691d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5692d6c0b56eSmrg
5693d6c0b56eSmrgcommit 4ca8f957e0b417b099f625470db98a54531a731d
5694d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5695d6c0b56eSmrgDate:   Thu Oct 1 13:16:15 2015 -0400
5696d6c0b56eSmrg
5697d6c0b56eSmrg    Silence type mismatch warning.
5698d6c0b56eSmrg    
5699d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5700d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5701d6c0b56eSmrg
5702d6c0b56eSmrgcommit a79735ab1499c1f7814036d1b19ff465705c5f45
5703d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5704d6c0b56eSmrgDate:   Thu Oct 1 10:51:07 2015 -0400
5705d6c0b56eSmrg
5706d6c0b56eSmrg    Add support for server managed fds
5707d6c0b56eSmrg    
5708d6c0b56eSmrg    Based on radeon commit ed0cfbb4fe77146b0b38f777bc28f3a4ea6da07f
5709d6c0b56eSmrg    
5710d6c0b56eSmrg    and 2nd patch:
5711d6c0b56eSmrg    
5712d6c0b56eSmrg    Fix building on older servers without xf86platformBus.h
5713d6c0b56eSmrg    
5714d6c0b56eSmrg    Based on radeon commit b50da3b96c212086cb58501dbe988d64f1f35b6d
5715d6c0b56eSmrg    
5716d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5717d6c0b56eSmrg    
5718d6c0b56eSmrg    [ Michel Dänzer: Fixed up amdgpu_kernel_open_fd() not to need
5719d6c0b56eSmrg      AMDGPUEntPriv(), which doesn't work yet at that point ]
5720d6c0b56eSmrg    
5721d6c0b56eSmrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
5722d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5723d6c0b56eSmrg
5724d6c0b56eSmrgcommit b93934a9ed5e92f3a6eac6554c5c4fa2967a6dd0
5725d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5726d6c0b56eSmrgDate:   Thu Oct 1 10:05:36 2015 -0400
5727d6c0b56eSmrg
5728d6c0b56eSmrg    Add amdgpu_open_drm_master helper function
5729d6c0b56eSmrg    
5730d6c0b56eSmrg    Based on radeon commit 3d7861fe112f25874319d4cdc12b745fbcd359cf
5731d6c0b56eSmrg    
5732d6c0b56eSmrg    > This is a preparation patch for adding server-managed-fd support without it
5733d6c0b56eSmrg    > turning into a goto fest.
5734d6c0b56eSmrg    
5735d6c0b56eSmrg    With appropriate modifications because the open call stack is different
5736d6c0b56eSmrg    in the amdgpu tree.
5737d6c0b56eSmrg    
5738d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5739d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5740d6c0b56eSmrg
5741d6c0b56eSmrgcommit f5c3fd0b57cf9e392bf591110568637937a1d338
5742d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5743d6c0b56eSmrgDate:   Thu Oct 1 09:13:57 2015 -0400
5744d6c0b56eSmrg
5745d6c0b56eSmrg    Cleaning up for server-fd support
5746d6c0b56eSmrg    
5747d6c0b56eSmrg    Based on radeon commit a63342ad15408071437c80b411d14196f3288aed
5748d6c0b56eSmrg    
5749d6c0b56eSmrg    > radeon_open_drm_master get rid of unnecessary goto
5750d6c0b56eSmrg    
5751d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5752d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5753d6c0b56eSmrg
5754d6c0b56eSmrgcommit 3055724aef76a624718f26d5f0f9e9d567ffbcfb
5755d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5756d6c0b56eSmrgDate:   Thu Sep 24 13:08:31 2015 -0400
5757d6c0b56eSmrg
5758d6c0b56eSmrg    Simplify pick best crtc to fold two loops into one
5759d6c0b56eSmrg    
5760d6c0b56eSmrg    This patch folds the two for loops from amdgpu_pick_best_crtc() into
5761d6c0b56eSmrg    one to reduce the LOC and make the routine easier to read.
5762d6c0b56eSmrg    
5763d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5764d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5765d6c0b56eSmrg
5766d6c0b56eSmrgcommit 9945b4ae1664ab815b39ff07e7b66cfa7f942dfa
5767d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5768d6c0b56eSmrgDate:   Wed Sep 9 09:38:02 2015 -0400
5769d6c0b56eSmrg
5770d6c0b56eSmrg    Avoid use-after-free in drmmode_output_destroy()
5771d6c0b56eSmrg    
5772d6c0b56eSmrg    The encoders array is freed before potentially all of the elements of
5773d6c0b56eSmrg    the array are individually freed.
5774d6c0b56eSmrg    
5775d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5776d6c0b56eSmrg    Reviewed-by: Christian König <christian.koenig@amd.com>
5777d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5778d6c0b56eSmrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> (cosmetic fixups)
5779d6c0b56eSmrg
5780d6c0b56eSmrgcommit 36b3faebdd1d2090a286616eeeb131d15e9a1386
5781d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5782d6c0b56eSmrgDate:   Wed Sep 9 09:36:59 2015 -0400
5783d6c0b56eSmrg
5784d6c0b56eSmrg    Avoid use-after-free in amdgpu_kernel_open_fd()
5785d6c0b56eSmrg    
5786d6c0b56eSmrg    If the device cannot be opened avoid re-using busid after it has been
5787d6c0b56eSmrg    freed.
5788d6c0b56eSmrg    
5789d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5790d6c0b56eSmrg    Reviewed-by: Christian König <christian.koenig@amd.com>
5791d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5792d6c0b56eSmrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> (cosmetic fixups)
5793d6c0b56eSmrg
5794d6c0b56eSmrgcommit 8823c3d4c6db70cff7699b31088f2d92db8faaf4
5795d6c0b56eSmrgAuthor: Tom St Denis <tom.stdenis@amd.com>
5796d6c0b56eSmrgDate:   Wed Sep 9 09:34:38 2015 -0400
5797d6c0b56eSmrg
5798d6c0b56eSmrg    dri2: Avoid calculation with undefined msc value
5799d6c0b56eSmrg    
5800d6c0b56eSmrg    If the get_msc() call fails for any reason we should avoid updating the
5801d6c0b56eSmrg    vblank counter delta with undefined data.
5802d6c0b56eSmrg    
5803d6c0b56eSmrg    Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
5804d6c0b56eSmrg    Reviewed-by: Christian König <christian.koenig@amd.com>
5805d6c0b56eSmrg    Acked-by: Alex Deucher <alexander.deucher@amd.com>
5806d6c0b56eSmrg    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> (minor fixups)
5807d6c0b56eSmrg
5808d6c0b56eSmrgcommit 63948ea091a9b324327ade7ec4fc5d67ca7e6f6f
5809d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5810d6c0b56eSmrgDate:   Fri Aug 14 18:41:57 2015 +0900
5811d6c0b56eSmrg
5812d6c0b56eSmrg    DRI2: Keep MSC monotonic when moving window between CRTCs
5813d6c0b56eSmrg    
5814d6c0b56eSmrg    This mirrors the DRI3 implementation in xserver. Fixes VDPAU video
5815d6c0b56eSmrg    playback hanging when moving the window between CRTCs.
5816d6c0b56eSmrg    
5817d6c0b56eSmrg    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66384
5818d6c0b56eSmrg    
5819d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5820d6c0b56eSmrg
5821d6c0b56eSmrgcommit 55a4461bd95698cb8d52f9f6c28583f8f81afb4e
5822d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5823d6c0b56eSmrgDate:   Fri Aug 7 11:46:31 2015 +0900
5824d6c0b56eSmrg
5825d6c0b56eSmrg    Wait for scanout BO initialization to finish before setting mode
5826d6c0b56eSmrg    
5827d6c0b56eSmrg    This should avoid intermittent artifacts which could sometimes be visible
5828d6c0b56eSmrg    when setting a new scanout pixmap, e.g. on server startup or when
5829d6c0b56eSmrg    changing resolutions.
5830d6c0b56eSmrg    
5831d6c0b56eSmrg    (Ported from radeon commit 3791fceabf2cb037467dc41c15364e9f9ec1e47e)
5832d6c0b56eSmrg    
5833d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5834d6c0b56eSmrg
5835d6c0b56eSmrgcommit 4c425e9c5c038504a0f0498dd800ab1fb40bf0c5
5836d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5837d6c0b56eSmrgDate:   Fri Aug 7 12:39:24 2015 +0900
5838d6c0b56eSmrg
5839d6c0b56eSmrg    glamor: Add amdgpu_glamor_finish to wait for glamor rendering to finish
5840d6c0b56eSmrg    
5841d6c0b56eSmrg    This is a bit sneaky, because it calls glFinish directly from the driver,
5842d6c0b56eSmrg    but it seems to work fine.
5843d6c0b56eSmrg    
5844d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5845d6c0b56eSmrg
5846d6c0b56eSmrgcommit bb989e173dc364a7d68e50d7e819d0e0ee133d2f
5847d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5848d6c0b56eSmrgDate:   Fri Aug 7 11:43:48 2015 +0900
5849d6c0b56eSmrg
5850d6c0b56eSmrg    Only call drmmode_copy_fb (at most) once on server startup
5851d6c0b56eSmrg    
5852d6c0b56eSmrg    It doesn't make sense to copy the screen contents from console when VT
5853d6c0b56eSmrg    switching back to Xorg or when Xorg resets.
5854d6c0b56eSmrg    
5855d6c0b56eSmrg    Fixes intermittent artifacts when VT switching back from console to the
5856d6c0b56eSmrg    gdm login screen.
5857d6c0b56eSmrg    
5858d6c0b56eSmrg    (Ported from radeon commit 4e3dfa69e4630df2e0ec0f5b81d61159757c4664)
5859d6c0b56eSmrg    
5860d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5861d6c0b56eSmrg
5862d6c0b56eSmrgcommit ebe2c020fbf2ef8de01fc50b201ab23ddb9fb13b
5863d6c0b56eSmrgAuthor: Mario Kleiner <mario.kleiner.de@gmail.com>
5864d6c0b56eSmrgDate:   Mon Aug 10 23:34:40 2015 +0200
5865d6c0b56eSmrg
5866d6c0b56eSmrg    Make selection between DRI2 and DRI3 consistent with other drivers. (v2)
5867d6c0b56eSmrg    
5868d6c0b56eSmrg    Add Option "DRI" to allow selection of maximum DRI level.
5869d6c0b56eSmrg    
5870d6c0b56eSmrg    This allows the user to select the maximum level of DRI
5871d6c0b56eSmrg    implementation to use, DRI2 or DRI3. It replaces the old
5872d6c0b56eSmrg    option "DRI3" which had exactly the same purpose, but
5873d6c0b56eSmrg    differs from the method used in both intel ddx and nouveau ddx.
5874d6c0b56eSmrg    Make this consistent before a new stable driver is released.
5875d6c0b56eSmrg    
5876d6c0b56eSmrg    v2: Retain handling of old Option "DRI3" for backwards
5877d6c0b56eSmrg        compatibility, but Option "DRI" will take precedence
5878d6c0b56eSmrg        over "DRI3" if both are provided.
5879d6c0b56eSmrg    
5880d6c0b56eSmrg    Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
5881d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5882d6c0b56eSmrg
5883d6c0b56eSmrgcommit c9611a2aa0f8d3bb55c552353740d60f6e4f63a0
5884d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com>
5885d6c0b56eSmrgDate:   Tue Jul 7 22:46:34 2015 -0400
5886d6c0b56eSmrg
5887d6c0b56eSmrg    add fiji pci id
5888d6c0b56eSmrg    
5889d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5890d6c0b56eSmrg    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5891d6c0b56eSmrg
5892d6c0b56eSmrgcommit 2622ac1554761b8824bfbbb2e3051a632ee38ce7
5893d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com>
5894d6c0b56eSmrgDate:   Tue Jul 7 22:46:08 2015 -0400
5895d6c0b56eSmrg
5896d6c0b56eSmrg    Add fiji support
5897d6c0b56eSmrg    
5898d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
5899d6c0b56eSmrg    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
5900d6c0b56eSmrg
5901d6c0b56eSmrgcommit 7a49d8728d17875206a84fd1023f62b37c4a9f51
5902d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5903d6c0b56eSmrgDate:   Thu Aug 6 18:21:30 2015 +0900
5904d6c0b56eSmrg
5905d6c0b56eSmrg    On screen resize, clear the new buffer before displaying it
5906d6c0b56eSmrg    
5907d6c0b56eSmrg    Fixes garbage being intermittently visible during a screen resize.
5908d6c0b56eSmrg    
5909d6c0b56eSmrg    (Ported from radeon commit 80f3d727f93cb6efedd2b39338d2301035965fe2)
5910d6c0b56eSmrg    
5911d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5912d6c0b56eSmrg
5913d6c0b56eSmrgcommit 9f988bf1dc9d4cb92926c051ed8f15e9ba58a016
5914d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5915d6c0b56eSmrgDate:   Thu Aug 6 17:50:11 2015 +0900
5916d6c0b56eSmrg
5917d6c0b56eSmrg    Make drmmode_copy_fb() work with glamor
5918d6c0b56eSmrg    
5919d6c0b56eSmrg    Needed for Xorg -background none.
5920d6c0b56eSmrg    
5921d6c0b56eSmrg    (Ported from radeon commit 3999bf88cdb192fe2f30b03bd2ed6f6a3f9f9057)
5922d6c0b56eSmrg    
5923d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5924d6c0b56eSmrg
5925d6c0b56eSmrgcommit 13cf61bd8d46b0059f26120a8902da6f86e6bd11
5926d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5927d6c0b56eSmrgDate:   Thu Aug 6 17:46:38 2015 +0900
5928d6c0b56eSmrg
5929d6c0b56eSmrg    Update scanout pixmap contents before setting a mode with it
5930d6c0b56eSmrg    
5931d6c0b56eSmrg    This ensures the scanout pixmaps used for Option "TearFree" and Option
5932d6c0b56eSmrg    "ShadowPrimary" have been initialized when their initial mode is set.
5933d6c0b56eSmrg    
5934d6c0b56eSmrg    (Ported from radeon commit a4a8cdbcc10c1c5f07485a2af9e9e81e490c3e1d)
5935d6c0b56eSmrg    
5936d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5937d6c0b56eSmrg
5938d6c0b56eSmrgcommit 15050aabf256c17250d1fca0bfac97fc6707b195
5939d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5940d6c0b56eSmrgDate:   Thu Aug 6 17:37:11 2015 +0900
5941d6c0b56eSmrg
5942d6c0b56eSmrg    Defer initial modeset until the first BlockHandler invocation
5943d6c0b56eSmrg    
5944d6c0b56eSmrg    This ensures that the screen pixmap contents have been initialized when
5945d6c0b56eSmrg    the initial modes are set.
5946d6c0b56eSmrg    
5947d6c0b56eSmrg    (Ported from radeon commits 673e1c7637687c74fc9bdeeeffb7ace0d04b734f and
5948d6c0b56eSmrg    1584dc545c78e0bce8d4b4b9f26b568e2c211453)
5949d6c0b56eSmrg    
5950d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5951d6c0b56eSmrg
5952d6c0b56eSmrgcommit 96b5364496222f1b3afb9caad458f16f156b6c47
5953d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5954d6c0b56eSmrgDate:   Thu Aug 6 17:32:45 2015 +0900
5955d6c0b56eSmrg
5956d6c0b56eSmrg    Defer initial drmmode_copy_fb call until root window creation
5957d6c0b56eSmrg    
5958d6c0b56eSmrg    That's late enough for acceleration to be fully initialized, but still
5959d6c0b56eSmrg    early enough to set pScreen->canDoBGNoneRoot.
5960d6c0b56eSmrg    
5961d6c0b56eSmrg    (Ported from radeon commit 37874a4eeace5df04b02c8fc28f67b824e3f0f5f)
5962d6c0b56eSmrg    
5963d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5964d6c0b56eSmrg
5965d6c0b56eSmrgcommit 0fb45f2bba89379ba25d4c863091937b6384bda9
5966d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5967d6c0b56eSmrgDate:   Thu Aug 6 17:25:53 2015 +0900
5968d6c0b56eSmrg
5969d6c0b56eSmrg    Only copy fbcon BO contents if bgNoneRoot is TRUE
5970d6c0b56eSmrg    
5971d6c0b56eSmrg    Otherwise, the X server will initialize the screen pixmap contents
5972d6c0b56eSmrg    anyway.
5973d6c0b56eSmrg    
5974d6c0b56eSmrg    (Ported from radeon commit 39c497f3efca5ca08343b884f44c93215dcdef31)
5975d6c0b56eSmrg    
5976d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5977d6c0b56eSmrg
5978d6c0b56eSmrgcommit cac553d3b691d26eaad24fbdcba06097b6728a6d
5979d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
5980d6c0b56eSmrgDate:   Thu Aug 6 17:20:22 2015 +0900
5981d6c0b56eSmrg
5982d6c0b56eSmrg    Add .dir-locals.el file with Emacs indentation settings
5983d6c0b56eSmrg    
5984d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
5985d6c0b56eSmrg
5986d6c0b56eSmrgcommit ea32253541959cc36a40fb0118200a8f493dc98a
5987d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com>
5988d6c0b56eSmrgDate:   Wed Jul 15 11:26:28 2015 +0800
5989d6c0b56eSmrg
5990d6c0b56eSmrg    Adapt to the interface change of amdgpu_bo_alloc v3
5991d6c0b56eSmrg    
5992d6c0b56eSmrg    The amdgpu_bo_alloc_result structure is removed from libdrm_amdgpu,
5993d6c0b56eSmrg    and the amdgpu_bo_handle is returned directly
5994d6c0b56eSmrg    
5995d6c0b56eSmrg    v2: remove the va_map/unmap
5996d6c0b56eSmrg    v3: simply the code a bit
5997d6c0b56eSmrg    
5998d6c0b56eSmrg    Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
5999d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6000d6c0b56eSmrg
6001d6c0b56eSmrgcommit 3010d3259d3bc74263d526e54e02bc169c8d4b4d
6002d6c0b56eSmrgAuthor: Mario Kleiner <mario.kleiner.de@gmail.com>
6003d6c0b56eSmrgDate:   Wed Jul 15 09:54:59 2015 +0200
6004d6c0b56eSmrg
6005d6c0b56eSmrg    Allow/Fix use of multiple ZaphodHead outputs per x-screen.
6006d6c0b56eSmrg    
6007d6c0b56eSmrg    Defining multiple ZaphodHead outputs per x-screen in a
6008d6c0b56eSmrg    multiple x-screen's per gpu configuration caused all
6009d6c0b56eSmrg    outputs except one per x-screen to go dark, because
6010d6c0b56eSmrg    there was a fixed mapping x-screen number -> crtc number,
6011d6c0b56eSmrg    limiting the number of crtc's per x-screen to one.
6012d6c0b56eSmrg    
6013d6c0b56eSmrg    On a ZaphodHead's setup, be more clever and assign
6014d6c0b56eSmrg    as many crtc's to a given x-screen as there are
6015d6c0b56eSmrg    ZaphodHeads defined for that screen, assuming
6016d6c0b56eSmrg    there are enough unused crtc's available.
6017d6c0b56eSmrg    
6018d6c0b56eSmrg    (Ported from radeon commit afab7839fc15722dbaa7203d00fe7f6ce5336b9d)
6019d6c0b56eSmrg    
6020d6c0b56eSmrg    Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
6021d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6022d6c0b56eSmrg
6023d6c0b56eSmrgcommit 159c5d460a330cf0a24678f3c6c3e2fbaf23c571
6024d6c0b56eSmrgAuthor: Dave Airlie <airlied@gmail.com>
6025d6c0b56eSmrgDate:   Tue Jul 14 17:04:14 2015 +0900
6026d6c0b56eSmrg
6027d6c0b56eSmrg    Adopt for new X server dirty tracking APIs.
6028d6c0b56eSmrg    
6029d6c0b56eSmrg    Signed-off-by: Dave Airlie <airlied@redhat.com>
6030d6c0b56eSmrg    
6031d6c0b56eSmrg    (Ported from radeon commit b6d871bf299c7d0f106c07ee4d8bd3b2337f53cc)
6032d6c0b56eSmrg    
6033d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6034d6c0b56eSmrg
6035d6c0b56eSmrgcommit 7b3212e33cd36fb6f122774df27b56ec4e1a22b8
6036d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6037d6c0b56eSmrgDate:   Thu Jul 9 17:57:29 2015 +0900
6038d6c0b56eSmrg
6039d6c0b56eSmrg    DRI2: Don't ignore rotated CRTCs in amdgpu_dri2_drawable_crtc
6040d6c0b56eSmrg    
6041d6c0b56eSmrg    Waiting for vblank interrupts works fine with rotated CRTCs. The only
6042d6c0b56eSmrg    case we can't handle with rotation is page flipping, which is handled
6043d6c0b56eSmrg    in can_exchange().
6044d6c0b56eSmrg    
6045d6c0b56eSmrg    This fixes gnome-shell hanging on rotation, probably because
6046d6c0b56eSmrg    amdgpu_dri2_get_msc returned MSC/UST 0 for rotated CRTCs.
6047d6c0b56eSmrg    
6048d6c0b56eSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
6049d6c0b56eSmrg
6050d6c0b56eSmrgcommit 5587a7b43d02d6371ed4675a6260427492ebad94
6051d6c0b56eSmrgAuthor: Piotr Redlewski <predlewski@gmail.com>
6052d6c0b56eSmrgDate:   Wed Jul 8 20:59:14 2015 +0200
6053d6c0b56eSmrg
6054d6c0b56eSmrg    Do not try to enable already enabled CRTCs in DPMS hook
6055d6c0b56eSmrg    
6056d6c0b56eSmrg    (Ported from radeon commit a8ed62010d5012dfb27773595c446b217f3c00c5)
6057d6c0b56eSmrg    
6058d6c0b56eSmrg    Signed-off-by: Piotr Redlewski <predlewski@gmail.com>
6059d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6060d6c0b56eSmrg
6061d6c0b56eSmrgcommit b176e63df20b345cb378fe962afd14eed43421d3
6062d6c0b56eSmrgAuthor: Piotr Redlewski <predlewski@gmail.com>
6063d6c0b56eSmrgDate:   Sun Jun 28 23:20:22 2015 +0200
6064d6c0b56eSmrg
6065d6c0b56eSmrg    Enable/disable CRTCs in DPMS hook
6066d6c0b56eSmrg    
6067d6c0b56eSmrg    The CRTC DPMS hook hasn't enabled or disabled hardware CRTCs.
6068d6c0b56eSmrg    
6069d6c0b56eSmrg    (Based on radeon commit 48e5be1d5a82c1e0ccf6b7d52924c92a630e52a8)
6070d6c0b56eSmrg    
6071d6c0b56eSmrg    Signed-off-by: Piotr Redlewski <predlewski@gmail.com>
6072d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6073d6c0b56eSmrg
6074d6c0b56eSmrgcommit d94d4a609c593b46ab718544ee24c25530732f22
6075d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6076d6c0b56eSmrgDate:   Thu Jun 11 17:49:33 2015 +0900
6077d6c0b56eSmrg
6078d6c0b56eSmrg    Handle CRTC DPMS from output DPMS hooks
6079d6c0b56eSmrg    
6080d6c0b56eSmrg    This fixes at least two issues:
6081d6c0b56eSmrg    
6082d6c0b56eSmrg    The CRTC DPMS hook isn't called after a modeset, so the vertical blank
6083d6c0b56eSmrg    interrupt emulation code considered the CRTC disabled after a modeset. As
6084d6c0b56eSmrg    a side effect, page flipping was no longer used after a modeset.
6085d6c0b56eSmrg    
6086d6c0b56eSmrg    This change also makes sure the vertical blank interrupt emulation code
6087d6c0b56eSmrg    runs before the hardware CRTC is disabled and after it's enabled from the
6088d6c0b56eSmrg    output DPMS hook. The wrong order could cause gnome-shell to hang after
6089d6c0b56eSmrg    a suspend/resume and/or DPMS off/on cycle.
6090d6c0b56eSmrg    
6091d6c0b56eSmrg    (Ported from radeon commit c4ae0e2cbcc0e2ebf9f13ee92d59b5120254a1dc)
6092d6c0b56eSmrg    
6093d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6094d6c0b56eSmrg
6095d6c0b56eSmrgcommit c57da33308a81fa575179238a0415abcb8b34908
6096d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6097d6c0b56eSmrgDate:   Tue Jun 9 12:39:21 2015 +0900
6098d6c0b56eSmrg
6099d6c0b56eSmrg    Add Option "TearFree"
6100d6c0b56eSmrg    
6101d6c0b56eSmrg    Avoids tearing by flipping between two scanout BOs per (non-rotated) CRTC
6102d6c0b56eSmrg    
6103d6c0b56eSmrg    (Cherry picked from radeon commit 43159ef400c3b18b9f4d3e6fa1c4aef2d60d38fe)
6104d6c0b56eSmrg    
6105d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6106d6c0b56eSmrg
6107d6c0b56eSmrgcommit bd0aca09770543fa77b934e1728a832c9c2dc90c
6108d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6109d6c0b56eSmrgDate:   Tue Jun 9 11:57:59 2015 +0900
6110d6c0b56eSmrg
6111d6c0b56eSmrg    glamor: Remove the stride member of struct radeon_pixmap
6112d6c0b56eSmrg    
6113d6c0b56eSmrg    Its value was always the same as that of the PixmapRec devKind member.
6114d6c0b56eSmrg    
6115d6c0b56eSmrg    (Cherry picked from radeon commit ed401f5b4f07375db17ff05e294907ec95fc946d)
6116d6c0b56eSmrg    
6117d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6118d6c0b56eSmrg
6119d6c0b56eSmrgcommit e5dfb6c2667994701ee451bf82c4142cbf343405
6120d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6121d6c0b56eSmrgDate:   Wed Mar 18 16:23:24 2015 +0900
6122d6c0b56eSmrg
6123d6c0b56eSmrg    glamor: Add Option "ShadowPrimary"
6124d6c0b56eSmrg    
6125d6c0b56eSmrg    When this option is enabled, most pixmaps (including the screen pixmap)
6126d6c0b56eSmrg    are allocated in system RAM and mostly accessed by the CPU. Changed areas
6127d6c0b56eSmrg    of the screen pixmap are copied to dedicated per-CRTC scanout pixmaps
6128d6c0b56eSmrg    regularly, triggered by the vblank interrupt.
6129d6c0b56eSmrg    
6130d6c0b56eSmrg    (Cherry picked from radeon commits ae92d1765fa370a8d94c2856ad6c45d273ec3c69
6131d6c0b56eSmrg    and 1af044d7eee211fd4b248c236280274a68334da5)
6132d6c0b56eSmrg    
6133d6c0b56eSmrg    [ Michel Dänzer: Additional adjustements for the amdgpu driver ]
6134d6c0b56eSmrg    
6135d6c0b56eSmrg    Signed-off-by: Darren Powell <darren.powell@amd.com>
6136d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6137d6c0b56eSmrg
6138d6c0b56eSmrgcommit 08da7b691d556735dcc22b1351c886a5079dfd3f
6139d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6140d6c0b56eSmrgDate:   Wed Jun 10 16:21:21 2015 +0900
6141d6c0b56eSmrg
6142d6c0b56eSmrg    Add AMDGPU_CREATE_PIXMAP_GTT flag
6143d6c0b56eSmrg    
6144d6c0b56eSmrg    When set, the pixmap memory is allocated in GTT instead of in VRAM.
6145d6c0b56eSmrg    
6146d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6147d6c0b56eSmrg
6148d6c0b56eSmrgcommit 59bdb578266a2637fda8d11168b9332f6845157c
6149d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6150d6c0b56eSmrgDate:   Wed Jun 10 12:04:29 2015 +0900
6151d6c0b56eSmrg
6152d6c0b56eSmrg    Factor out amdgpu_bo_get_handle helper
6153d6c0b56eSmrg    
6154d6c0b56eSmrg    The helper transparently handles BOs allocated from GBM and
6155d6c0b56eSmrg    libdrm_amdgpu.
6156d6c0b56eSmrg    
6157d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6158d6c0b56eSmrg
6159d6c0b56eSmrgcommit 9a6eff506b6804481a6e8139d362355fc5ffdbfb
6160d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6161d6c0b56eSmrgDate:   Wed Jun 10 12:10:24 2015 +0900
6162d6c0b56eSmrg
6163d6c0b56eSmrg    Set AMDGPU_BO_FLAGS_GBM for cursor buffers allocated from GBM
6164d6c0b56eSmrg    
6165d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6166d6c0b56eSmrg
6167d6c0b56eSmrgcommit d3ea8a69b02b308f8f23662be6e0c7bd81c1a2c9
6168d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6169d6c0b56eSmrgDate:   Fri May 29 18:53:50 2015 +0900
6170d6c0b56eSmrg
6171d6c0b56eSmrg    glamor: Add wrappers for the X server rendering hooks
6172d6c0b56eSmrg    
6173d6c0b56eSmrg    They can choose between using the GPU or CPU for the operation.
6174d6c0b56eSmrg    
6175d6c0b56eSmrg    (cherry picked from radeon commits eea79472a84672ee4dc7adc4487cec6a4037048a
6176d6c0b56eSmrg    and e58fc380ccf2a581d28f041fd74b963626ca5404)
6177d6c0b56eSmrg    
6178d6c0b56eSmrg    Signed-off-by: Darren Powell <darren.powell@amd.com>
6179d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6180d6c0b56eSmrg
6181d6c0b56eSmrgcommit 895e4d73d5f042afa13065b64a78f5625ecb5612
6182d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6183d6c0b56eSmrgDate:   Fri May 29 18:53:40 2015 +0900
6184d6c0b56eSmrg
6185d6c0b56eSmrg    glamor: Remove unused function radeon_glamor_pixmap_is_offscreen
6186d6c0b56eSmrg    
6187d6c0b56eSmrg    (cherry picked from radeon commit 2fa021f77372ca93375a3d13a0c43a9089674899)
6188d6c0b56eSmrg    
6189d6c0b56eSmrg    Signed-off-by: Darren Powell <darren.powell@amd.com>
6190d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6191d6c0b56eSmrg
6192d6c0b56eSmrgcommit cc5671c587d575b2a7d2802d17e8af0384a2cea5
6193d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6194d6c0b56eSmrgDate:   Fri May 29 18:53:36 2015 +0900
6195d6c0b56eSmrg
6196d6c0b56eSmrg    Add RADEON_CREATE_PIXMAP_SCANOUT flag
6197d6c0b56eSmrg    
6198d6c0b56eSmrg    It means that the pixmap is used for scanout exclusively.
6199d6c0b56eSmrg    
6200d6c0b56eSmrg    (cherry picked from radeon commit e96349ba6281fd18b8bf9c76629128276b065e6c)
6201d6c0b56eSmrg    
6202d6c0b56eSmrg    Signed-off-by: Darren Powell <darren.powell@amd.com>
6203d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6204d6c0b56eSmrg
6205d6c0b56eSmrgcommit 21834953ee64920438dee1c94f3a1e53dc58b82d
6206d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6207d6c0b56eSmrgDate:   Fri May 29 18:53:32 2015 +0900
6208d6c0b56eSmrg
6209d6c0b56eSmrg    Split out struct drmmode_scanout for rotation shadow buffer information
6210d6c0b56eSmrg    
6211d6c0b56eSmrg    Will be used for other kinds of dedicated scanout buffers as well.
6212d6c0b56eSmrg    
6213d6c0b56eSmrg    (cherry picked from radeon commit 9be7dd382e86d2b804de81d4e2af7431b2e16843)
6214d6c0b56eSmrg    
6215d6c0b56eSmrg    Signed-off-by: Darren Powell <darren.powell@amd.com>
6216d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6217d6c0b56eSmrg
6218d6c0b56eSmrgcommit e4e4f7b83e7d7e43993fa0793d666d6dec2980f8
6219d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6220d6c0b56eSmrgDate:   Fri May 29 18:53:21 2015 +0900
6221d6c0b56eSmrg
6222d6c0b56eSmrg    Rename scanout_pixmap_x field to prime_pixmap_x
6223d6c0b56eSmrg    
6224d6c0b56eSmrg    To avoid confusion with upcoming changes.
6225d6c0b56eSmrg    
6226d6c0b56eSmrg    (cherry picked from radeon commit c32b0530302739f6512755bccf281c2300617376)
6227d6c0b56eSmrg    
6228d6c0b56eSmrg    Signed-off-by: Darren Powell <darren.powell@amd.com>
6229d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6230d6c0b56eSmrg
6231d6c0b56eSmrgcommit edfff6b1a3a19953644b8052b30076f76f7dc337
6232d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6233d6c0b56eSmrgDate:   Tue Jun 2 17:04:21 2015 +0900
6234d6c0b56eSmrg
6235d6c0b56eSmrg    Add DRI3 support
6236d6c0b56eSmrg    
6237d6c0b56eSmrg    Must be enabled with
6238d6c0b56eSmrg    
6239504d986fSmrg            Option  "DRI3"
6240d6c0b56eSmrg    
6241d6c0b56eSmrg    in xorg.conf.
6242d6c0b56eSmrg    
6243d6c0b56eSmrg    (Cherry picked from radeon commits 64e1e4dbdd3caee6f5d8f6b6c094b4533fa94953,
6244d6c0b56eSmrg    694e04720b886060fe3eefdce59741f218c8269f,
6245d6c0b56eSmrg    f940fd741b15f03393037c5bb904cd74f012de9d,
6246d6c0b56eSmrg    fcd37f65f485291084c174666bd605e215bf1398,
6247d6c0b56eSmrg    4b0997e56dec0053cb2cb793e0f4ae35055ff7e6,
6248d6c0b56eSmrg    f68d9b5ba0c91a725b5eec9386c61bea8824c299 and
6249d6c0b56eSmrg    98fb4199e63fedd4607cddee64bf602d6398df81)
6250d6c0b56eSmrg    
6251d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6252d6c0b56eSmrg
6253d6c0b56eSmrgcommit d295b5b3310bc5c23d232c4be4170165a057c090
6254d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6255d6c0b56eSmrgDate:   Tue Jun 2 17:01:06 2015 +0900
6256d6c0b56eSmrg
6257d6c0b56eSmrg    amdgpu_set_shared_pixmap_backing: Add support for GBM / glamor v2
6258d6c0b56eSmrg    
6259d6c0b56eSmrg    v2: Initialize reference count of imported GBM BOs to 1, fixes leaking
6260d6c0b56eSmrg        them.
6261d6c0b56eSmrg    
6262d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com> [v1]
6263d6c0b56eSmrg
6264d6c0b56eSmrgcommit 03ad0fa0185d215f7d4234006e04406af1ab63ca
6265d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6266d6c0b56eSmrgDate:   Fri May 29 18:53:45 2015 +0900
6267d6c0b56eSmrg
6268d6c0b56eSmrg    glamor: Add radeon_pixmap parameter to radeon_glamor_create_textured_pixmap
6269d6c0b56eSmrg    
6270d6c0b56eSmrg    (cherry picked from radeon commit 051d46382656ffc3e6cac1aab3aee7efdf5b623a)
6271d6c0b56eSmrg    
6272d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6273d6c0b56eSmrg    Signed-off-by: Darren Powell <darren.powell@amd.com>
6274d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6275d6c0b56eSmrg
6276d6c0b56eSmrgcommit fafb8c6ac925ad16073e5a60dbf60d5add11bb25
6277d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6278d6c0b56eSmrgDate:   Tue Jun 2 17:00:46 2015 +0900
6279d6c0b56eSmrg
6280d6c0b56eSmrg    Add support for the Present extension
6281d6c0b56eSmrg    
6282d6c0b56eSmrg    (Cherry picked from radeon commits 3c65fb849e1ba9fb6454bcaa55b696548902f3fc,
6283d6c0b56eSmrg    694e04720b886060fe3eefdce59741f218c8269f,
6284d6c0b56eSmrg    e3be8b0a8cf484ff16597413a6172788178e80c8,
6285d6c0b56eSmrg    80eede245d1eda27eaba108b0761a24bfd69aff6 and
6286d6c0b56eSmrg    5f82a720374c9c1caebb42bfbeea1f0cf8847d28)
6287d6c0b56eSmrg    
6288d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6289d6c0b56eSmrg
6290d6c0b56eSmrgcommit 5b51f0e7e396ea946ef85429a8e9be5c1d5c39c3
6291d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6292d6c0b56eSmrgDate:   Tue Jun 2 16:58:27 2015 +0900
6293d6c0b56eSmrg
6294d6c0b56eSmrg    Add support for SYNC extension fences
6295d6c0b56eSmrg    
6296d6c0b56eSmrg    (Cherry picked from radeon commits 8fc9a241ab59ffbcdc178d6415332c88a54e85fe,
6297d6c0b56eSmrg    af1862a37570fa512a525ab47d72b30400d2e2d6,
6298d6c0b56eSmrg    aa7825eb29cdf6ac9d7b28ad18186807ff384687,
6299d6c0b56eSmrg    af6076241c0d322b295a4e898407ae2472bd8eb4 and
6300d6c0b56eSmrg    d64a13ebe0ecd241ee3260dbffd8f4a01e254183)
6301d6c0b56eSmrg    
6302d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6303d6c0b56eSmrg
6304d6c0b56eSmrgcommit a30060d22a42688371166a861e5050fdd5ce8f7b
6305d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6306d6c0b56eSmrgDate:   Mon Jun 1 18:33:33 2015 +0900
6307d6c0b56eSmrg
6308d6c0b56eSmrg    DRI2: Split out helper for getting UST and MSC of a specific CRTC
6309d6c0b56eSmrg    
6310d6c0b56eSmrg    (Cherry picked from radeon commits 76c2923ac5c7230a8b2f9f8329c308d28b44d9c0
6311d6c0b56eSmrg    and d7c82731a8bf3d381bc571b94d80d9bb2dd6e40d)
6312d6c0b56eSmrg    
6313d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6314d6c0b56eSmrg
6315d6c0b56eSmrgcommit 9a554a683b970660b467566cf05b921393705a20
6316d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6317d6c0b56eSmrgDate:   Mon Jun 1 17:32:56 2015 +0900
6318d6c0b56eSmrg
6319d6c0b56eSmrg    DRI2: Use helper functions for DRM event queue management
6320d6c0b56eSmrg    
6321d6c0b56eSmrg    This is mostly in preparation for Present support, but it also simplifies
6322d6c0b56eSmrg    the DRI2 specific code a little.
6323d6c0b56eSmrg    
6324d6c0b56eSmrg    (Cherry picked from radeon commit 6c3a721cde9317233072b573f9502348dcd21b16)
6325d6c0b56eSmrg    
6326d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6327d6c0b56eSmrg
6328d6c0b56eSmrgcommit e6164ad340f65ff8ee6f6a6934302591af875a43
6329d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6330d6c0b56eSmrgDate:   Mon Jun 1 17:29:30 2015 +0900
6331d6c0b56eSmrg
6332d6c0b56eSmrg    DRI2: Move amdgpu_dri2_flip_event_handler
6333d6c0b56eSmrg    
6334d6c0b56eSmrg    In preparation for the next change, which will modify it to a static
6335d6c0b56eSmrg    function which needs to be in the new place. No functional change.
6336d6c0b56eSmrg    
6337d6c0b56eSmrg    (Cherry picked from radeon commit c3fa22a479e61d1899fa9d327d9c4e2a7f64b0c1)
6338d6c0b56eSmrg    
6339d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6340d6c0b56eSmrg
6341d6c0b56eSmrgcommit 5419e13da7ec3cffd43510ac88106076ea81124c
6342d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6343d6c0b56eSmrgDate:   Mon Jun 1 17:25:23 2015 +0900
6344d6c0b56eSmrg
6345d6c0b56eSmrg    DRI2: Remove superfluous assignments to *_info->frame
6346d6c0b56eSmrg    
6347d6c0b56eSmrg    That field is only used for page flipping.
6348d6c0b56eSmrg    
6349d6c0b56eSmrg    (Cherry picked from radeon commit 65045112fdc8a9fa36e0e00f46739a6152b775ff)
6350d6c0b56eSmrg    
6351d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6352d6c0b56eSmrg
6353d6c0b56eSmrgcommit f4c2b640be17ab1f8694b35d4cb74ccfce3d1385
6354d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6355d6c0b56eSmrgDate:   Mon Jun 1 17:11:30 2015 +0900
6356d6c0b56eSmrg
6357d6c0b56eSmrg    DRI2: Simplify blit fallback handling for scheduled swaps
6358d6c0b56eSmrg    
6359d6c0b56eSmrg    Also use amdgpu_dri2_schedule_event when possible.
6360d6c0b56eSmrg    
6361d6c0b56eSmrg    (Cherry picked from radeon commit ad27f16f308079d06a2b1c788b3cb0947531253a)
6362d6c0b56eSmrg    
6363d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6364d6c0b56eSmrg
6365d6c0b56eSmrgcommit 13a7284e061081a12180b375d66f9b8394cf8753
6366d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6367d6c0b56eSmrgDate:   Mon Jun 1 16:58:00 2015 +0900
6368d6c0b56eSmrg
6369d6c0b56eSmrg    Add DRM event queue helpers
6370d6c0b56eSmrg    
6371d6c0b56eSmrg    (Cherry picked from radeon commit b4af8a327ed8420f0ff4ea0f113f4a59406ed4d3)
6372d6c0b56eSmrg    
6373d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6374d6c0b56eSmrg
6375d6c0b56eSmrgcommit eb7c6958dff5cb8b0aad02d1d5673483dae4e3d4
6376d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6377d6c0b56eSmrgDate:   Mon Jun 1 16:52:40 2015 +0900
6378d6c0b56eSmrg
6379d6c0b56eSmrg    Move xorg_list backwards compatibility to new amdgpu_list.h header
6380d6c0b56eSmrg    
6381d6c0b56eSmrg    (Cherry picked from radeon commits 7c3470f4b659206ed23f761948936ede3a2dba3d
6382d6c0b56eSmrg    and 4a98f60117c387a228d5cbaadb6e298fb4e865df)
6383d6c0b56eSmrg    
6384d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6385d6c0b56eSmrg
6386d6c0b56eSmrgcommit 69d161a54b4ea0d8033a0873210f2857c91ceae8
6387d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6388d6c0b56eSmrgDate:   Mon Jun 1 16:46:30 2015 +0900
6389d6c0b56eSmrg
6390d6c0b56eSmrg    Require at least xserver 1.8
6391d6c0b56eSmrg    
6392d6c0b56eSmrg    So we can rely on the list.h header.
6393d6c0b56eSmrg    
6394d6c0b56eSmrg    xserver 1.8 was released in April 2010.
6395d6c0b56eSmrg    
6396d6c0b56eSmrg    (Cherry picked from radeon commit 7388d0b6c54b9d536fdb161e3aa61b326627b939)
6397d6c0b56eSmrg    
6398d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6399d6c0b56eSmrg
6400d6c0b56eSmrgcommit 7363156b7c077def2aaf9a4573410817f5e92610
6401d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com>
6402d6c0b56eSmrgDate:   Sat May 30 00:31:44 2015 +0800
6403d6c0b56eSmrg
6404d6c0b56eSmrg    Check GBM_BO_USE_LINEAR correctly v2
6405d6c0b56eSmrg    
6406d6c0b56eSmrg    v2: remove the check for gbm.h
6407d6c0b56eSmrg    
6408d6c0b56eSmrg    Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
6409d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6410d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com> [v1]
6411d6c0b56eSmrg
6412d6c0b56eSmrgcommit e75e9f39c95b8b563885882bf29d776861cd6ca3
6413d6c0b56eSmrgAuthor: Brian Paterni <bpaterni@gmail.com>
6414d6c0b56eSmrgDate:   Sat May 16 15:00:14 2015 -0500
6415d6c0b56eSmrg
6416d6c0b56eSmrg    extend conditional group GBM_BO_USE_LINEAR
6417d6c0b56eSmrg over both usages
6418d6c0b56eSmrg    
6419d6c0b56eSmrg    Fixes 'GBM_BO_USE_LINEAR' undeclared error when compiling against older
6420d6c0b56eSmrg    libgbm
6421d6c0b56eSmrg    
6422d6c0b56eSmrg    Signed-off-by: Brian Paterni <bpaterni@gmail.com>
6423d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6424d6c0b56eSmrg
6425d6c0b56eSmrgcommit 37b389ee9e13f065fb080d1269f9a6aed616c210
6426d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6427d6c0b56eSmrgDate:   Fri May 15 10:24:24 2015 +0900
6428d6c0b56eSmrg
6429d6c0b56eSmrg    glamor: Deal with glamor_glyphs_init being removed from xserver
6430d6c0b56eSmrg    
6431d6c0b56eSmrg    Port of radeon commit 818c180c8932233b214a35ba0647af82f7bcec3d.
6432d6c0b56eSmrg
6433d6c0b56eSmrgcommit 22917044e419023d487f816e0d4f094695b55fa6
6434d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com>
6435d6c0b56eSmrgDate:   Tue May 12 13:29:00 2015 -0400
6436d6c0b56eSmrg
6437d6c0b56eSmrg    add some new tonga pci ids
6438d6c0b56eSmrg    
6439d6c0b56eSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
6440d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6441d6c0b56eSmrg    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6442d6c0b56eSmrg
6443d6c0b56eSmrgcommit e71be4a22799ec4c02051b75c5fed16a3a953c7b
6444d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com>
6445d6c0b56eSmrgDate:   Tue May 12 13:25:02 2015 -0400
6446d6c0b56eSmrg
6447d6c0b56eSmrg    add new bonaire pci id
6448d6c0b56eSmrg    
6449d6c0b56eSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
6450d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6451d6c0b56eSmrg    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6452d6c0b56eSmrg
6453d6c0b56eSmrgcommit b795d1e137b34a314b4b41d025d96ca9251d6bbe
6454d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6455d6c0b56eSmrgDate:   Thu May 7 18:05:32 2015 +0900
6456d6c0b56eSmrg
6457d6c0b56eSmrg    Link against libgbm
6458d6c0b56eSmrg    
6459d6c0b56eSmrg    Fixes unresolved symbol "gbm_create_device".
6460d6c0b56eSmrg    
6461d6c0b56eSmrg    Reported-and-Tested-by: Brian Paterni <bpaterni@gmail.com>
6462d6c0b56eSmrg
6463d6c0b56eSmrgcommit 7e3b27390a03e423772717fca3c757cf5cc4d7b4
6464d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com>
6465d6c0b56eSmrgDate:   Tue May 12 05:34:49 2015 +0800
6466d6c0b56eSmrg
6467d6c0b56eSmrg    Disable tiling for PRIME shared pixmap
6468d6c0b56eSmrg    
6469d6c0b56eSmrg    Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
6470d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6471d6c0b56eSmrg
6472d6c0b56eSmrgcommit 4840f918ab7d61b4f55bcdff3afdac7b34e45d88
6473d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com>
6474d6c0b56eSmrgDate:   Tue May 12 00:09:42 2015 +0800
6475d6c0b56eSmrg
6476d6c0b56eSmrg    Use gbm_bo_get_fd to get DMA_BUF fd
6477d6c0b56eSmrg    
6478d6c0b56eSmrg    When GBM is used for buffer allocation, gbm_bo_get_fd should be
6479d6c0b56eSmrg    used to get the DMA_BUF fd.
6480d6c0b56eSmrg    
6481d6c0b56eSmrg    Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
6482d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6483d6c0b56eSmrg
6484d6c0b56eSmrgcommit b69c5b3cc2d7da3bb85acd687db9b5a021258914
6485d6c0b56eSmrgAuthor: Marek Olšák <marek.olsak@amd.com>
6486d6c0b56eSmrgDate:   Fri Mar 27 22:56:37 2015 +0100
6487d6c0b56eSmrg
6488d6c0b56eSmrg    ddx: use amdgpu_query_crtc_from_id
6489d6c0b56eSmrg    
6490d6c0b56eSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
6491d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6492d6c0b56eSmrg
6493d6c0b56eSmrgcommit 91aa694a7da7b690a3e5d59a1a8fa42cbb3ebda4
6494d6c0b56eSmrgAuthor: Marek Olšák <marek.olsak@amd.com>
6495d6c0b56eSmrgDate:   Fri Mar 27 22:22:35 2015 +0100
6496d6c0b56eSmrg
6497d6c0b56eSmrg    ddx: remove AMDGPUIsAccelWorking
6498d6c0b56eSmrg    
6499d6c0b56eSmrg    libdrm fails to initialize without acceleration, so this always returns true.
6500d6c0b56eSmrg    
6501d6c0b56eSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
6502d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6503d6c0b56eSmrg
6504d6c0b56eSmrgcommit afc33040f862e2e13ba7f132bb363cf16fb6a1d7
6505d6c0b56eSmrgAuthor: Marek Olšák <marek.olsak@amd.com>
6506d6c0b56eSmrgDate:   Fri Mar 27 22:14:37 2015 +0100
6507d6c0b56eSmrg
6508d6c0b56eSmrg    ddx: enable acceleration by default on Hawaii
6509d6c0b56eSmrg    
6510d6c0b56eSmrg    Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
6511d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6512d6c0b56eSmrg
6513d6c0b56eSmrgcommit 8a34a8149860ac15e83ccdbd8d9a527d8d3e5997
6514d6c0b56eSmrgAuthor: Jammy Zhou <Jammy.Zhou@amd.com>
6515d6c0b56eSmrgDate:   Mon Apr 27 14:27:34 2015 +0800
6516d6c0b56eSmrg
6517d6c0b56eSmrg    Remove throttling from amdgpu_dri2_copy_region2
6518d6c0b56eSmrg    
6519d6c0b56eSmrg    Throttling should be handled by the client-side drivers.
6520d6c0b56eSmrg    
6521d6c0b56eSmrg    Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
6522d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6523d6c0b56eSmrg
6524d6c0b56eSmrgcommit 9f61a5506b1028d30c99cb5866abcec35d5c9cb8
6525d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com>
6526d6c0b56eSmrgDate:   Fri Apr 24 11:47:32 2015 -0400
6527d6c0b56eSmrg
6528d6c0b56eSmrg    fixup README
6529d6c0b56eSmrg    
6530d6c0b56eSmrg    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
6531d6c0b56eSmrg    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6532d6c0b56eSmrg
6533d6c0b56eSmrgcommit a49ad11af18dad74506c2f69d7bbda07b67529d2
6534d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6535d6c0b56eSmrgDate:   Fri Apr 24 09:57:27 2015 +0900
6536d6c0b56eSmrg
6537d6c0b56eSmrg    Add 10-amdgpu.conf xorg.conf.d snippet
6538d6c0b56eSmrg    
6539d6c0b56eSmrg    This instructs Xorg >= 1.16 to try loading the amdgpu driver for devices
6540d6c0b56eSmrg    managed by the amdgpu kernel driver.
6541d6c0b56eSmrg    
6542d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6543d6c0b56eSmrg
6544d6c0b56eSmrgcommit fa4aed6cf56048a6520eac57514e38db3685cd15
6545d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6546d6c0b56eSmrgDate:   Fri Apr 24 09:53:33 2015 +0900
6547d6c0b56eSmrg
6548d6c0b56eSmrg    Document Option "AccelMethod" in the manpage
6549d6c0b56eSmrg    
6550d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6551d6c0b56eSmrg
6552d6c0b56eSmrgcommit fe4a4b6836252cc8caa642a32fb3910c8590076b
6553d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6554d6c0b56eSmrgDate:   Fri Apr 24 09:52:04 2015 +0900
6555d6c0b56eSmrg
6556d6c0b56eSmrg    Fix build when gbm.h doesn't define GBM_BO_USE_LINEAR
6557d6c0b56eSmrg    
6558d6c0b56eSmrg    Option "AccelMethod" "none" is ignored in that case.
6559d6c0b56eSmrg    
6560d6c0b56eSmrg    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
6561d6c0b56eSmrg
6562d6c0b56eSmrgcommit 84df3e7114fb71b5e10c1a6f7869ab1505fef5b0
6563d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6564d6c0b56eSmrgDate:   Fri Apr 24 09:51:22 2015 +0900
6565d6c0b56eSmrg
6566d6c0b56eSmrg    glamor: Handle GLAMOR_* flags removed from xserver
6567d6c0b56eSmrg    
6568d6c0b56eSmrg    The behaviour is the same as when the removed flags were passed in.
6569d6c0b56eSmrg    
6570d6c0b56eSmrg    (cherry picked from radeon commit b16609b453bb1a181198cf27778f205dc23fb642)
6571d6c0b56eSmrg    
6572d6c0b56eSmrg    Reviewed-by: Christian König <christian.koenig@amd.com>
6573d6c0b56eSmrg
6574d6c0b56eSmrgcommit b947f4bf4efa8841bea4d306d0b0d21c7511c724
6575d6c0b56eSmrgAuthor: Michel Dänzer <michel.daenzer@amd.com>
6576d6c0b56eSmrgDate:   Fri Apr 24 09:50:51 2015 +0900
6577d6c0b56eSmrg
6578d6c0b56eSmrg    Move #include "radeon_glamor.h" from amdgpu_drv.h to where it's needed
6579d6c0b56eSmrg    
6580d6c0b56eSmrg    (cherry picked from radeon commit 4b8adebb80158bcf81ada83bb88517febe931b12)
6581d6c0b56eSmrg    
6582d6c0b56eSmrg    Reviewed-by: Christian König <christian.koenig@amd.com>
6583d6c0b56eSmrg
6584d6c0b56eSmrgcommit ff62bf6e9dce55dbde92baf4fa30193c7344ee8a
6585d6c0b56eSmrgAuthor: Alex Deucher <alexander.deucher@amd.com>
6586d6c0b56eSmrgDate:   Mon Apr 20 11:57:52 2015 -0400
6587d6c0b56eSmrg
6588d6c0b56eSmrg    amdgpu: add the xf86-video-amdgpu driver
6589d6c0b56eSmrg    
6590d6c0b56eSmrg    This adds the new xf86-video-amdgpu driver for
6591d6c0b56eSmrg    newer AMD GPUs.
6592d6c0b56eSmrg    
6593    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6594