amdgpu_drm_queue.h revision 504d986f
1d6c0b56eSmrg/* 2d6c0b56eSmrg * Copyright © 2007 Red Hat, Inc. 3d6c0b56eSmrg * Copyright © 2015 Advanced Micro Devices, Inc. 4d6c0b56eSmrg * 5d6c0b56eSmrg * Permission is hereby granted, free of charge, to any person obtaining a 6d6c0b56eSmrg * copy of this software and associated documentation files (the "Software"), 7d6c0b56eSmrg * to deal in the Software without restriction, including without limitation 8d6c0b56eSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9d6c0b56eSmrg * and/or sell copies of the Software, and to permit persons to whom the 10d6c0b56eSmrg * Software is furnished to do so, subject to the following conditions: 11d6c0b56eSmrg * 12d6c0b56eSmrg * The above copyright notice and this permission notice (including the next 13d6c0b56eSmrg * paragraph) shall be included in all copies or substantial portions of the 14d6c0b56eSmrg * Software. 15d6c0b56eSmrg * 16d6c0b56eSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17d6c0b56eSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18d6c0b56eSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19d6c0b56eSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20d6c0b56eSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21d6c0b56eSmrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22d6c0b56eSmrg * SOFTWARE. 23d6c0b56eSmrg * 24d6c0b56eSmrg * Authors: 25d6c0b56eSmrg * Dave Airlie <airlied@redhat.com> 26d6c0b56eSmrg * 27d6c0b56eSmrg */ 28d6c0b56eSmrg 29d6c0b56eSmrg#ifndef _AMDGPU_DRM_QUEUE_H_ 30d6c0b56eSmrg#define _AMDGPU_DRM_QUEUE_H_ 31d6c0b56eSmrg 32d6c0b56eSmrg#include <xf86Crtc.h> 33d6c0b56eSmrg 34504d986fSmrg#define AMDGPU_DRM_QUEUE_ERROR 0 35504d986fSmrg 36d6c0b56eSmrg#define AMDGPU_DRM_QUEUE_CLIENT_DEFAULT serverClient 37d6c0b56eSmrg#define AMDGPU_DRM_QUEUE_ID_DEFAULT ~0ULL 38d6c0b56eSmrg 39d6c0b56eSmrgstruct amdgpu_drm_queue_entry; 40d6c0b56eSmrg 41d6c0b56eSmrgtypedef void (*amdgpu_drm_handler_proc)(xf86CrtcPtr crtc, uint32_t seq, 42d6c0b56eSmrg uint64_t usec, void *data); 43d6c0b56eSmrgtypedef void (*amdgpu_drm_abort_proc)(xf86CrtcPtr crtc, void *data); 44d6c0b56eSmrg 45d6c0b56eSmrgvoid amdgpu_drm_queue_handler(int fd, unsigned int frame, 46d6c0b56eSmrg unsigned int tv_sec, unsigned int tv_usec, 47d6c0b56eSmrg void *user_ptr); 48d6c0b56eSmrguintptr_t amdgpu_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client, 49d6c0b56eSmrg uint64_t id, void *data, 50d6c0b56eSmrg amdgpu_drm_handler_proc handler, 51d6c0b56eSmrg amdgpu_drm_abort_proc abort); 52d6c0b56eSmrgvoid amdgpu_drm_abort_client(ClientPtr client); 53d6c0b56eSmrgvoid amdgpu_drm_abort_entry(uintptr_t seq); 54d6c0b56eSmrgvoid amdgpu_drm_abort_id(uint64_t id); 55d6c0b56eSmrgvoid amdgpu_drm_queue_init(); 56d6c0b56eSmrgvoid amdgpu_drm_queue_close(ScrnInfoPtr scrn); 57d6c0b56eSmrg 58d6c0b56eSmrg#endif /* _AMDGPU_DRM_QUEUE_H_ */ 59