amdgpu_drm_queue.h revision 35d5b7c7 
1/*
2 * Copyright © 2007 Red Hat, Inc.
3 * Copyright © 2015 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 *    Dave Airlie <airlied@redhat.com>
26 *
27 */
28
29#ifndef _AMDGPU_DRM_QUEUE_H_
30#define _AMDGPU_DRM_QUEUE_H_
31
32#include <xf86Crtc.h>
33
34#define AMDGPU_DRM_QUEUE_ERROR 0
35
36#define AMDGPU_DRM_QUEUE_CLIENT_DEFAULT serverClient
37#define AMDGPU_DRM_QUEUE_ID_DEFAULT ~0ULL
38
39struct amdgpu_drm_queue_entry;
40
41typedef void (*amdgpu_drm_handler_proc)(xf86CrtcPtr crtc, uint32_t seq,
42					uint64_t usec, void *data);
43typedef void (*amdgpu_drm_abort_proc)(xf86CrtcPtr crtc, void *data);
44
45void amdgpu_drm_queue_handle_deferred(xf86CrtcPtr crtc);
46uintptr_t amdgpu_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client,
47				 uint64_t id, void *data,
48				 amdgpu_drm_handler_proc handler,
49				 amdgpu_drm_abort_proc abort);
50void amdgpu_drm_abort_client(ClientPtr client);
51void amdgpu_drm_abort_entry(uintptr_t seq);
52void amdgpu_drm_abort_id(uint64_t id);
53int amdgpu_drm_handle_event(int fd, drmEventContext *event_context);
54void amdgpu_drm_wait_pending_flip(xf86CrtcPtr crtc);
55void amdgpu_drm_queue_init(ScrnInfoPtr scrn);
56void amdgpu_drm_queue_close(ScrnInfoPtr scrn);
57
58#endif /* _AMDGPU_DRM_QUEUE_H_ */
59