amdgpu_drv.h revision d6c0b56e
1d6c0b56eSmrg/*
2d6c0b56eSmrg * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3d6c0b56eSmrg *                VA Linux Systems Inc., Fremont, California.
4d6c0b56eSmrg *
5d6c0b56eSmrg * All Rights Reserved.
6d6c0b56eSmrg *
7d6c0b56eSmrg * Permission is hereby granted, free of charge, to any person obtaining
8d6c0b56eSmrg * a copy of this software and associated documentation files (the
9d6c0b56eSmrg * "Software"), to deal in the Software without restriction, including
10d6c0b56eSmrg * without limitation on the rights to use, copy, modify, merge,
11d6c0b56eSmrg * publish, distribute, sublicense, and/or sell copies of the Software,
12d6c0b56eSmrg * and to permit persons to whom the Software is furnished to do so,
13d6c0b56eSmrg * subject to the following conditions:
14d6c0b56eSmrg *
15d6c0b56eSmrg * The above copyright notice and this permission notice (including the
16d6c0b56eSmrg * next paragraph) shall be included in all copies or substantial
17d6c0b56eSmrg * portions of the Software.
18d6c0b56eSmrg *
19d6c0b56eSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20d6c0b56eSmrg * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21d6c0b56eSmrg * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22d6c0b56eSmrg * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23d6c0b56eSmrg * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24d6c0b56eSmrg * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25d6c0b56eSmrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26d6c0b56eSmrg * DEALINGS IN THE SOFTWARE.
27d6c0b56eSmrg */
28d6c0b56eSmrg
29d6c0b56eSmrg/*
30d6c0b56eSmrg * Authors:
31d6c0b56eSmrg *   Kevin E. Martin <martin@xfree86.org>
32d6c0b56eSmrg *   Rickard E. Faith <faith@valinux.com>
33d6c0b56eSmrg *   Alan Hourihane <alanh@fairlite.demon.co.uk>
34d6c0b56eSmrg *
35d6c0b56eSmrg */
36d6c0b56eSmrg
37d6c0b56eSmrg#ifndef _AMDGPU_DRV_H_
38d6c0b56eSmrg#define _AMDGPU_DRV_H_
39d6c0b56eSmrg
40d6c0b56eSmrg#include <stdlib.h>		/* For abs() */
41d6c0b56eSmrg#include <unistd.h>		/* For usleep() */
42d6c0b56eSmrg#include <sys/time.h>		/* For gettimeofday() */
43d6c0b56eSmrg
44d6c0b56eSmrg#include "config.h"
45d6c0b56eSmrg
46d6c0b56eSmrg#include "xf86str.h"
47d6c0b56eSmrg#include "compiler.h"
48d6c0b56eSmrg
49d6c0b56eSmrg/* PCI support */
50d6c0b56eSmrg#include "xf86Pci.h"
51d6c0b56eSmrg
52d6c0b56eSmrg#include "fb.h"
53d6c0b56eSmrg
54d6c0b56eSmrg/* Cursor Support */
55d6c0b56eSmrg#include "xf86Cursor.h"
56d6c0b56eSmrg
57d6c0b56eSmrg/* DDC support */
58d6c0b56eSmrg#include "xf86DDC.h"
59d6c0b56eSmrg
60d6c0b56eSmrg/* Xv support */
61d6c0b56eSmrg#include "xf86xv.h"
62d6c0b56eSmrg
63d6c0b56eSmrg#include "amdgpu_probe.h"
64d6c0b56eSmrg
65d6c0b56eSmrg/* DRI support */
66d6c0b56eSmrg#include "xf86drm.h"
67d6c0b56eSmrg#include "amdgpu_drm.h"
68d6c0b56eSmrg
69d6c0b56eSmrg#ifdef DAMAGE
70d6c0b56eSmrg#include "damage.h"
71d6c0b56eSmrg#include "globals.h"
72d6c0b56eSmrg#endif
73d6c0b56eSmrg
74d6c0b56eSmrg#include "xf86Crtc.h"
75d6c0b56eSmrg#include "X11/Xatom.h"
76d6c0b56eSmrg
77d6c0b56eSmrg#include "amdgpu_dri2.h"
78d6c0b56eSmrg#include "drmmode_display.h"
79d6c0b56eSmrg#include "amdgpu_bo_helper.h"
80d6c0b56eSmrg
81d6c0b56eSmrg/* Render support */
82d6c0b56eSmrg#ifdef RENDER
83d6c0b56eSmrg#include "picturestr.h"
84d6c0b56eSmrg#endif
85d6c0b56eSmrg
86d6c0b56eSmrg#include "compat-api.h"
87d6c0b56eSmrg
88d6c0b56eSmrg#include "simple_list.h"
89d6c0b56eSmrg#include "amdpciids.h"
90d6c0b56eSmrg
91d6c0b56eSmrgstruct _SyncFence;
92d6c0b56eSmrg
93d6c0b56eSmrg#ifndef MAX
94d6c0b56eSmrg#define MAX(a,b) ((a)>(b)?(a):(b))
95d6c0b56eSmrg#endif
96d6c0b56eSmrg#ifndef MIN
97d6c0b56eSmrg#define MIN(a,b) ((a)>(b)?(b):(a))
98d6c0b56eSmrg#endif
99d6c0b56eSmrg
100d6c0b56eSmrg#if HAVE_BYTESWAP_H
101d6c0b56eSmrg#include <byteswap.h>
102d6c0b56eSmrg#elif defined(USE_SYS_ENDIAN_H)
103d6c0b56eSmrg#include <sys/endian.h>
104d6c0b56eSmrg#else
105d6c0b56eSmrg#define bswap_16(value)  \
106d6c0b56eSmrg        ((((value) & 0xff) << 8) | ((value) >> 8))
107d6c0b56eSmrg
108d6c0b56eSmrg#define bswap_32(value) \
109d6c0b56eSmrg        (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \
110d6c0b56eSmrg        (uint32_t)bswap_16((uint16_t)((value) >> 16)))
111d6c0b56eSmrg
112d6c0b56eSmrg#define bswap_64(value) \
113d6c0b56eSmrg        (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \
114d6c0b56eSmrg            << 32) | \
115d6c0b56eSmrg        (uint64_t)bswap_32((uint32_t)((value) >> 32)))
116d6c0b56eSmrg#endif
117d6c0b56eSmrg
118d6c0b56eSmrg#if X_BYTE_ORDER == X_BIG_ENDIAN
119d6c0b56eSmrg#define le32_to_cpu(x) bswap_32(x)
120d6c0b56eSmrg#define le16_to_cpu(x) bswap_16(x)
121d6c0b56eSmrg#define cpu_to_le32(x) bswap_32(x)
122d6c0b56eSmrg#define cpu_to_le16(x) bswap_16(x)
123d6c0b56eSmrg#else
124d6c0b56eSmrg#define le32_to_cpu(x) (x)
125d6c0b56eSmrg#define le16_to_cpu(x) (x)
126d6c0b56eSmrg#define cpu_to_le32(x) (x)
127d6c0b56eSmrg#define cpu_to_le16(x) (x)
128d6c0b56eSmrg#endif
129d6c0b56eSmrg
130d6c0b56eSmrg/* Provide substitutes for gcc's __FUNCTION__ on other compilers */
131d6c0b56eSmrg#if !defined(__GNUC__) && !defined(__FUNCTION__)
132d6c0b56eSmrg#define __FUNCTION__ __func__	/* C99 */
133d6c0b56eSmrg#endif
134d6c0b56eSmrg
135d6c0b56eSmrgtypedef enum {
136d6c0b56eSmrg	OPTION_ACCEL,
137d6c0b56eSmrg	OPTION_SW_CURSOR,
138d6c0b56eSmrg	OPTION_PAGE_FLIP,
139d6c0b56eSmrg#ifdef RENDER
140d6c0b56eSmrg	OPTION_SUBPIXEL_ORDER,
141d6c0b56eSmrg#endif
142d6c0b56eSmrg	OPTION_ZAPHOD_HEADS,
143d6c0b56eSmrg	OPTION_ACCEL_METHOD,
144d6c0b56eSmrg	OPTION_DRI3,
145d6c0b56eSmrg	OPTION_DRI,
146d6c0b56eSmrg	OPTION_SHADOW_PRIMARY,
147d6c0b56eSmrg	OPTION_TEAR_FREE,
148d6c0b56eSmrg	OPTION_DELETE_DP12,
149d6c0b56eSmrg} AMDGPUOpts;
150d6c0b56eSmrg
151d6c0b56eSmrg#if XF86_CRTC_VERSION >= 5
152d6c0b56eSmrg#define AMDGPU_PIXMAP_SHARING 1
153d6c0b56eSmrg#endif
154d6c0b56eSmrg
155d6c0b56eSmrg#define AMDGPU_VSYNC_TIMEOUT	20000	/* Maximum wait for VSYNC (in usecs) */
156d6c0b56eSmrg
157d6c0b56eSmrg/* Buffer are aligned on 4096 byte boundaries */
158d6c0b56eSmrg#define AMDGPU_GPU_PAGE_SIZE 4096
159d6c0b56eSmrg#define AMDGPU_BUFFER_ALIGN (AMDGPU_GPU_PAGE_SIZE - 1)
160d6c0b56eSmrg
161d6c0b56eSmrg#define xFixedToFloat(f) (((float) (f)) / 65536)
162d6c0b56eSmrg
163d6c0b56eSmrg#define AMDGPU_LOGLEVEL_DEBUG 4
164d6c0b56eSmrg
165d6c0b56eSmrg/* Other macros */
166d6c0b56eSmrg#define AMDGPU_ARRAY_SIZE(x)  (sizeof(x)/sizeof(x[0]))
167d6c0b56eSmrg#define AMDGPU_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
168d6c0b56eSmrg#define AMDGPUPTR(pScrn)      ((AMDGPUInfoPtr)(pScrn)->driverPrivate)
169d6c0b56eSmrg
170d6c0b56eSmrg#define CURSOR_WIDTH	64
171d6c0b56eSmrg#define CURSOR_HEIGHT	64
172d6c0b56eSmrg
173d6c0b56eSmrg#define CURSOR_WIDTH_CIK	128
174d6c0b56eSmrg#define CURSOR_HEIGHT_CIK	128
175d6c0b56eSmrg
176d6c0b56eSmrg#define AMDGPU_BO_FLAGS_GBM	0x1
177d6c0b56eSmrg
178d6c0b56eSmrgstruct amdgpu_buffer {
179d6c0b56eSmrg	union {
180d6c0b56eSmrg		struct gbm_bo *gbm;
181d6c0b56eSmrg		amdgpu_bo_handle amdgpu;
182d6c0b56eSmrg	} bo;
183d6c0b56eSmrg	void *cpu_ptr;
184d6c0b56eSmrg	uint32_t ref_count;
185d6c0b56eSmrg	uint32_t flags;
186d6c0b56eSmrg};
187d6c0b56eSmrg
188d6c0b56eSmrgtypedef struct {
189d6c0b56eSmrg	EntityInfoPtr pEnt;
190d6c0b56eSmrg	pciVideoPtr PciInfo;
191d6c0b56eSmrg	int Chipset;
192d6c0b56eSmrg	AMDGPUChipFamily ChipFamily;
193d6c0b56eSmrg	struct gbm_device *gbm;
194d6c0b56eSmrg
195d6c0b56eSmrg	 Bool(*CloseScreen) (CLOSE_SCREEN_ARGS_DECL);
196d6c0b56eSmrg
197d6c0b56eSmrg	void (*BlockHandler) (BLOCKHANDLER_ARGS_DECL);
198d6c0b56eSmrg
199d6c0b56eSmrg	void (*CreateFence) (ScreenPtr pScreen, struct _SyncFence *pFence,
200d6c0b56eSmrg			     Bool initially_triggered);
201d6c0b56eSmrg
202d6c0b56eSmrg	int pix24bpp;		/* Depth of pixmap for 24bpp fb      */
203d6c0b56eSmrg	Bool dac6bits;		/* Use 6 bit DAC?                    */
204d6c0b56eSmrg
205d6c0b56eSmrg	int pixel_bytes;
206d6c0b56eSmrg
207d6c0b56eSmrg	Bool directRenderingEnabled;
208d6c0b56eSmrg	struct amdgpu_dri2 dri2;
209d6c0b56eSmrg
210d6c0b56eSmrg	/* accel */
211d6c0b56eSmrg	PixmapPtr fbcon_pixmap;
212d6c0b56eSmrg	uint_fast32_t gpu_flushed;
213d6c0b56eSmrg	uint_fast32_t gpu_synced;
214d6c0b56eSmrg	Bool use_glamor;
215d6c0b56eSmrg	Bool force_accel;
216d6c0b56eSmrg	Bool shadow_primary;
217d6c0b56eSmrg	Bool tear_free;
218d6c0b56eSmrg
219d6c0b56eSmrg	/* general */
220d6c0b56eSmrg	OptionInfoPtr Options;
221d6c0b56eSmrg
222d6c0b56eSmrg	DisplayModePtr currentMode;
223d6c0b56eSmrg
224d6c0b56eSmrg	CreateScreenResourcesProcPtr CreateScreenResources;
225d6c0b56eSmrg#if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 10
226d6c0b56eSmrg	CreateWindowProcPtr CreateWindow;
227d6c0b56eSmrg#endif
228d6c0b56eSmrg
229d6c0b56eSmrg	Bool IsSecondary;
230d6c0b56eSmrg
231d6c0b56eSmrg	Bool shadow_fb;
232d6c0b56eSmrg	void *fb_shadow;
233d6c0b56eSmrg	struct amdgpu_buffer *front_buffer;
234d6c0b56eSmrg	struct amdgpu_buffer *cursor_buffer[32];
235d6c0b56eSmrg
236d6c0b56eSmrg	uint64_t vram_size;
237d6c0b56eSmrg	uint64_t gart_size;
238d6c0b56eSmrg	drmmode_rec drmmode;
239d6c0b56eSmrg	Bool drmmode_inited;
240d6c0b56eSmrg	/* r6xx+ tile config */
241d6c0b56eSmrg	Bool have_tiling_info;
242d6c0b56eSmrg	int group_bytes;
243d6c0b56eSmrg
244d6c0b56eSmrg	/* kms pageflipping */
245d6c0b56eSmrg	Bool allowPageFlip;
246d6c0b56eSmrg
247d6c0b56eSmrg	/* cursor size */
248d6c0b56eSmrg	int cursor_w;
249d6c0b56eSmrg	int cursor_h;
250d6c0b56eSmrg
251d6c0b56eSmrg	/* If bit n of this field is set, xf86_config->crtc[n] currently can't
252d6c0b56eSmrg	 * use the HW cursor
253d6c0b56eSmrg	 */
254d6c0b56eSmrg	unsigned hwcursor_disabled;
255d6c0b56eSmrg
256d6c0b56eSmrg	struct {
257d6c0b56eSmrg		CreateGCProcPtr SavedCreateGC;
258d6c0b56eSmrg		RegionPtr (*SavedCopyArea)(DrawablePtr, DrawablePtr, GCPtr,
259d6c0b56eSmrg					   int, int, int, int, int, int);
260d6c0b56eSmrg		void (*SavedPolyFillRect)(DrawablePtr, GCPtr, int, xRectangle*);
261d6c0b56eSmrg		CloseScreenProcPtr SavedCloseScreen;
262d6c0b56eSmrg		GetImageProcPtr SavedGetImage;
263d6c0b56eSmrg		GetSpansProcPtr SavedGetSpans;
264d6c0b56eSmrg		CreatePixmapProcPtr SavedCreatePixmap;
265d6c0b56eSmrg		DestroyPixmapProcPtr SavedDestroyPixmap;
266d6c0b56eSmrg		CopyWindowProcPtr SavedCopyWindow;
267d6c0b56eSmrg		ChangeWindowAttributesProcPtr SavedChangeWindowAttributes;
268d6c0b56eSmrg		BitmapToRegionProcPtr SavedBitmapToRegion;
269d6c0b56eSmrg#ifdef RENDER
270d6c0b56eSmrg		CompositeProcPtr SavedComposite;
271d6c0b56eSmrg		TrianglesProcPtr SavedTriangles;
272d6c0b56eSmrg		GlyphsProcPtr SavedGlyphs;
273d6c0b56eSmrg		TrapezoidsProcPtr SavedTrapezoids;
274d6c0b56eSmrg		AddTrapsProcPtr SavedAddTraps;
275d6c0b56eSmrg		UnrealizeGlyphProcPtr SavedUnrealizeGlyph;
276d6c0b56eSmrg#endif
277d6c0b56eSmrg#ifdef AMDGPU_PIXMAP_SHARING
278d6c0b56eSmrg		SharePixmapBackingProcPtr SavedSharePixmapBacking;
279d6c0b56eSmrg		SetSharedPixmapBackingProcPtr SavedSetSharedPixmapBacking;
280d6c0b56eSmrg#endif
281d6c0b56eSmrg	} glamor;
282d6c0b56eSmrg
283d6c0b56eSmrg} AMDGPUInfoRec, *AMDGPUInfoPtr;
284d6c0b56eSmrg
285d6c0b56eSmrg
286d6c0b56eSmrg/* amdgpu_dri3.c */
287d6c0b56eSmrgBool amdgpu_dri3_screen_init(ScreenPtr screen);
288d6c0b56eSmrg
289d6c0b56eSmrg/* amdgpu_kms.c */
290d6c0b56eSmrgvoid amdgpu_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame,
291d6c0b56eSmrg				   uint64_t usec, void *event_data);
292d6c0b56eSmrg
293d6c0b56eSmrg/* amdgpu_present.c */
294d6c0b56eSmrgBool amdgpu_present_screen_init(ScreenPtr screen);
295d6c0b56eSmrg
296d6c0b56eSmrg/* amdgpu_sync.c */
297d6c0b56eSmrgextern Bool amdgpu_sync_init(ScreenPtr screen);
298d6c0b56eSmrgextern void amdgpu_sync_close(ScreenPtr screen);
299d6c0b56eSmrg
300d6c0b56eSmrg/* amdgpu_video.c */
301d6c0b56eSmrgextern void AMDGPUInitVideo(ScreenPtr pScreen);
302d6c0b56eSmrgextern void AMDGPUResetVideo(ScrnInfoPtr pScrn);
303d6c0b56eSmrgextern xf86CrtcPtr amdgpu_pick_best_crtc(ScrnInfoPtr pScrn,
304d6c0b56eSmrg					 Bool consider_disabled,
305d6c0b56eSmrg					 int x1, int x2, int y1, int y2);
306d6c0b56eSmrg
307d6c0b56eSmrgextern AMDGPUEntPtr AMDGPUEntPriv(ScrnInfoPtr pScrn);
308d6c0b56eSmrg
309d6c0b56eSmrgdrmVBlankSeqType amdgpu_populate_vbl_request_type(xf86CrtcPtr crtc);
310d6c0b56eSmrg
311d6c0b56eSmrg#endif /* _AMDGPU_DRV_H_ */
312