ast_mode.c revision 58e54220
1/* 2 * Copyright (c) 2005 ASPEED Technology Inc. 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that 7 * copyright notice and this permission notice appear in supporting 8 * documentation, and that the name of the authors not be used in 9 * advertising or publicity pertaining to distribution of the software without 10 * specific, written prior permission. The authors makes no representations 11 * about the suitability of this software for any purpose. It is provided 12 * "as is" without express or implied warranty. 13 * 14 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#ifdef HAVE_CONFIG_H 24#include <config.h> 25#endif 26#include "xf86.h" 27#include "xf86_OSproc.h" 28#include "xf86cmap.h" 29#include "compiler.h" 30#include "vgaHW.h" 31#include "mipointer.h" 32#include "micmap.h" 33 34#include "fb.h" 35#include "regionstr.h" 36#include "xf86xv.h" 37#include <X11/extensions/Xv.h> 38 39#include "xf86Pci.h" 40 41/* framebuffer offscreen manager */ 42#include "xf86fbman.h" 43 44/* include xaa includes */ 45#include "xaarop.h" 46 47/* H/W cursor support */ 48#include "xf86Cursor.h" 49 50/* usleep() */ 51#include <unistd.h> 52 53/* Driver specific headers */ 54#include "ast.h" 55#include "ast_mode.h" 56#include "ast_vgatool.h" 57 58static VBIOS_STDTABLE_STRUCT StdTable[] = { 59 /* MD_2_3_400 */ 60 { 61 0x67, 62 {0x00,0x03,0x00,0x02}, 63 {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, 64 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, 65 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, 66 0xff}, 67 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 68 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 69 0x0c,0x00,0x0f,0x08}, 70 {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, 71 0xff} 72 }, 73 /* Mode12/ExtEGATable */ 74 { 75 0xe3, 76 {0x01,0x0f,0x00,0x06}, 77 {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, 78 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 79 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, 80 0xff}, 81 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 82 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 83 0x01,0x00,0x0f,0x00}, 84 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 85 0xff} 86 }, 87 /* ExtVGATable */ 88 { 89 0x2f, 90 {0x01,0x0f,0x00,0x0e}, 91 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 92 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 93 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 94 0xff}, 95 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 96 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 97 0x01,0x00,0x00,0x00}, 98 {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, 99 0xff} 100 }, 101 /* ExtHiCTable */ 102 { 103 0x2f, 104 {0x01,0x0f,0x00,0x0e}, 105 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 106 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 107 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 108 0xff}, 109 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 110 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 111 0x01,0x00,0x00,0x00}, 112 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 113 0xff} 114 }, 115 /* ExtTrueCTable */ 116 { 117 0x2f, 118 {0x01,0x0f,0x00,0x0e}, 119 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 120 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 121 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 122 0xff}, 123 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 124 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 125 0x01,0x00,0x00,0x00}, 126 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 127 0xff} 128 }, 129}; 130 131static VBIOS_ENHTABLE_STRUCT Res640x480Table[] = { 132 { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ 133 (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, 134 { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ 135 (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, 136 { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ 137 (SyncNN | Charx8Dot) , 75, 3, 0x2E }, 138 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ 139 (SyncNN | Charx8Dot) , 85, 4, 0x2E }, 140 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ 141 (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, 142}; 143 144 145static VBIOS_ENHTABLE_STRUCT Res800x600Table[] = { 146 {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ 147 (SyncPP | Charx8Dot), 56, 1, 0x30 }, 148 {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ 149 (SyncPP | Charx8Dot), 60, 2, 0x30 }, 150 {1040, 800, 56, 120, 666, 600, 37, 6, VCLK50, /* 72Hz */ 151 (SyncPP | Charx8Dot), 72, 3, 0x30 }, 152 {1056, 800, 16, 80, 625, 600, 1, 3, VCLK49_5, /* 75Hz */ 153 (SyncPP | Charx8Dot), 75, 4, 0x30 }, 154 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* 85Hz */ 155 (SyncPP | Charx8Dot), 84, 5, 0x30 }, 156 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* end */ 157 (SyncPP | Charx8Dot), 0xFF, 5, 0x30 }, 158}; 159 160static VBIOS_ENHTABLE_STRUCT Res1024x768Table[] = { 161 {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ 162 (SyncNN | Charx8Dot), 60, 1, 0x31 }, 163 {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ 164 (SyncNN | Charx8Dot), 70, 2, 0x31 }, 165 {1312, 1024, 16, 96, 800, 768, 1, 3, VCLK78_75, /* 75Hz */ 166 (SyncPP | Charx8Dot), 75, 3, 0x31 }, 167 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* 85Hz */ 168 (SyncPP | Charx8Dot), 84, 4, 0x31 }, 169 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* end */ 170 (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, 171}; 172 173static VBIOS_ENHTABLE_STRUCT Res1280x1024Table[] = { 174 {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ 175 (SyncPP | Charx8Dot), 60, 1, 0x32 }, 176 {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ 177 (SyncPP | Charx8Dot), 75, 2, 0x32 }, 178 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* 85Hz */ 179 (SyncPP | Charx8Dot), 85, 3, 0x32 }, 180 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* end */ 181 (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, 182}; 183 184static VBIOS_ENHTABLE_STRUCT Res1600x1200Table[] = { 185 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ 186 (SyncPP | Charx8Dot), 60, 1, 0x33 }, 187 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ 188 (SyncPP | Charx8Dot), 0xFF, 1, 0x33 }, 189}; 190 191/* 16:9 */ 192static VBIOS_ENHTABLE_STRUCT Res1360x768Table[] = { 193 {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ 194 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, 195 {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ 196 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, 197}; 198 199static VBIOS_ENHTABLE_STRUCT Res1600x900Table[] = { 200 {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ 201 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 2, 0x3A }, 202 {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ 203 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, 204 {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* end */ 205 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x3A }, 206}; 207 208static VBIOS_ENHTABLE_STRUCT Res1920x1080Table[] = { 209 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* HDTV 60Hz */ 210 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 1, 0x38 }, 211 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* end */ 212 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 0xFF, 1, 0x38 }, 213}; 214 215/* 16:10 */ 216static VBIOS_ENHTABLE_STRUCT Res1280x800Table[] = { 217 {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz CVT RB */ 218 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 2, 35 }, 219 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz CVT */ 220 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, 221 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* end */ 222 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x35 }, 223}; 224 225static VBIOS_ENHTABLE_STRUCT Res1440x900Table[] = { 226 {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz CVT RB */ 227 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 2, 0x36 }, 228 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz CVT */ 229 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, 230 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* end */ 231 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x36 }, 232}; 233 234static VBIOS_ENHTABLE_STRUCT Res1680x1050Table[] = { 235 {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz CVT RB */ 236 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 2, 0x37 }, 237 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz CVT */ 238 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, 239 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* end */ 240 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x37 }, 241}; 242 243static VBIOS_ENHTABLE_STRUCT Res1920x1200Table[] = { 244 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz CVT RB */ 245 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 1, 0x34 }, 246 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* end */ 247 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 }, 248}; 249 250static VBIOS_DCLK_INFO DCLKTable [] = { 251 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 252 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 253 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 254 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 255 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 256 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 257 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 258 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 259 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 260 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 261 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 262 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 263 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 264 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 265 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 266 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 267 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 268 {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */ 269 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 270 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 271 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 272 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 273 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 274 {0x77, 0x58, 0x80}, /* 17: VCLK119 */ 275 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ 276 {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ 277 {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ 278}; 279 280static VBIOS_DCLK_INFO DCLKTable_AST2100 [] = { 281 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 282 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 283 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 284 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 285 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 286 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 287 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 288 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 289 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 290 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 291 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 292 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 293 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 294 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 295 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 296 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 297 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 298 {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ 299 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 300 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 301 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 302 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 303 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 304 {0x77, 0x58, 0x80}, /* 17: VCLK119 */ 305 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ 306 {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ 307 {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ 308}; 309 310static VBIOS_DCLK_INFO DCLKTable_AST2500 [] = { 311 {0x40, 0x38, 0x73}, /* 00: VCLK25_175 */ 312 {0x3A, 0x38, 0x43}, /* 01: VCLK28_322 */ 313 {0x3E, 0x70, 0x73}, /* 02: VCLK31_5 */ 314 {0x35, 0x70, 0x43}, /* 03: VCLK36 */ 315 {0x31, 0x28, 0x73}, /* 04: VCLK40 */ 316 {0x41, 0x68, 0x73}, /* 05: VCLK49_5 */ 317 {0x31, 0x68, 0x53}, /* 06: VCLK50 */ 318 {0x4A, 0x68, 0x73}, /* 07: VCLK56_25 */ 319 {0x40, 0x68, 0x53}, /* 08: VCLK65 */ 320 {0x31, 0x60, 0x73}, /* 09: VCLK75 */ 321 {0x3A, 0x28, 0x43}, /* 0A: VCLK78_75 */ 322 {0x3E, 0x60, 0x73}, /* 0B: VCLK94_5 */ 323 {0x35, 0x60, 0x63}, /* 0C: VCLK108 */ 324 {0x3D, 0x40, 0x63}, /* 0D: VCLK135 */ 325 {0x4E, 0x60, 0x63}, /* 0E: VCLK157_5 */ 326 {0x35, 0x60, 0x53}, /* 0F: VCLK162 */ 327 {0x4C, 0x60, 0x63}, /* 10: VCLK154 */ 328 {0x4F, 0x48, 0x53}, /* 11: VCLK83.5 */ 329 {0x46, 0x60, 0x73}, /* 12: VCLK106.5 */ 330 {0x3C, 0x20, 0x63}, /* 13: VCLK146.25 */ 331 {0x3D, 0x20, 0x63}, /* 14: VCLK148.5 */ 332 {0x46, 0x68, 0x53}, /* 15: VCLK71 */ 333 {0x49, 0x68, 0x43}, /* 16: VCLK88.75 */ 334 {0x4e, 0x60, 0x73}, /* 17: VCLK119 */ 335 {0x38, 0x60, 0x73}, /* 18: VCLK85_5 */ 336 {0x38, 0x20, 0x73}, /* 19: VCLK97_75 */ 337 {0x4e, 0x60, 0x73}, /* 1A: VCLK118_25 */ 338}; 339 340static VBIOS_DCLK_INFO DCLKTable_AST2500A1 [] = { 341 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 342 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 343 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 344 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 345 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 346 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 347 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 348 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 349 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 350 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 351 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 352 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 353 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 354 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 355 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 356 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 357 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 358 {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ 359 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 360 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 361 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 362 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 363 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 364 {0x58, 0x01, 0x42}, /* 17: VCLK119 */ 365 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ 366 {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ 367 {0x44, 0x20, 0x43}, /* 1A: VCLK118_25 */ 368}; 369 370static VBIOS_DAC_INFO DAC_TEXT[] = { 371 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 372 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 373 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 374 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 375 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 376 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 377 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 378 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 379 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 380 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 381 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 382 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 383 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 384 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 385 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 386 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 387}; 388 389static VBIOS_DAC_INFO DAC_EGA[] = { 390 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 391 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 392 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 393 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 394 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 395 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 396 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 397 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 398 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 399 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 400 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 401 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 402 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 403 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 404 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 405 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 406}; 407 408static VBIOS_DAC_INFO DAC_VGA[] = { 409 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 410 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x15, 0x00 }, { 0x2a, 0x2a, 0x2a }, 411 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 412 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 413 { 0x00, 0x00, 0x00 }, { 0x05, 0x05, 0x05 }, { 0x08, 0x08, 0x08 }, { 0x0b, 0x0b, 0x0b }, 414 { 0x0e, 0x0e, 0x0e }, { 0x11, 0x11, 0x11 }, { 0x14, 0x14, 0x14 }, { 0x18, 0x18, 0x18 }, 415 { 0x1c, 0x1c, 0x1c }, { 0x20, 0x20, 0x20 }, { 0x24, 0x24, 0x24 }, { 0x28, 0x28, 0x28 }, 416 { 0x2d, 0x2d, 0x2d }, { 0x32, 0x32, 0x32 }, { 0x38, 0x38, 0x38 }, { 0x3f, 0x3f, 0x3f }, 417 { 0x00, 0x00, 0x3f }, { 0x10, 0x00, 0x3f }, { 0x1f, 0x00, 0x3f }, { 0x2f, 0x00, 0x3f }, 418 { 0x3f, 0x00, 0x3f }, { 0x3f, 0x00, 0x2f }, { 0x3f, 0x00, 0x1f }, { 0x3f, 0x00, 0x10 }, 419 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x10, 0x00 }, { 0x3f, 0x1f, 0x00 }, { 0x3f, 0x2f, 0x00 }, 420 { 0x3f, 0x3f, 0x00 }, { 0x2f, 0x3f, 0x00 }, { 0x1f, 0x3f, 0x00 }, { 0x10, 0x3f, 0x00 }, 421 { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x10 }, { 0x00, 0x3f, 0x1f }, { 0x00, 0x3f, 0x2f }, 422 { 0x00, 0x3f, 0x3f }, { 0x00, 0x2f, 0x3f }, { 0x00, 0x1f, 0x3f }, { 0x00, 0x10, 0x3f }, 423 { 0x1f, 0x1f, 0x3f }, { 0x27, 0x1f, 0x3f }, { 0x2f, 0x1f, 0x3f }, { 0x37, 0x1f, 0x3f }, 424 { 0x3f, 0x1f, 0x3f }, { 0x3f, 0x1f, 0x37 }, { 0x3f, 0x1f, 0x2f }, { 0x3f, 0x1f, 0x27 }, 425 { 0x3f, 0x1f, 0x1f }, { 0x3f, 0x27, 0x1f }, { 0x3f, 0x2f, 0x1f }, { 0x3f, 0x37, 0x1f }, 426 { 0x3f, 0x3f, 0x1f }, { 0x37, 0x3f, 0x1f }, { 0x2f, 0x3f, 0x1f }, { 0x27, 0x3f, 0x1f }, 427 { 0x1f, 0x3f, 0x1f }, { 0x1f, 0x3f, 0x27 }, { 0x1f, 0x3f, 0x2f }, { 0x1f, 0x3f, 0x37 }, 428 { 0x1f, 0x3f, 0x3f }, { 0x1f, 0x37, 0x3f }, { 0x1f, 0x2f, 0x3f }, { 0x1f, 0x27, 0x3f }, 429 { 0x2d, 0x2d, 0x3f }, { 0x31, 0x2d, 0x3f }, { 0x36, 0x2d, 0x3f }, { 0x3a, 0x2d, 0x3f }, 430 { 0x3f, 0x2d, 0x3f }, { 0x3f, 0x2d, 0x3a }, { 0x3f, 0x2d, 0x36 }, { 0x3f, 0x2d, 0x31 }, 431 { 0x3f, 0x2d, 0x2d }, { 0x3f, 0x31, 0x2d }, { 0x3f, 0x36, 0x2d }, { 0x3f, 0x3a, 0x2d }, 432 { 0x3f, 0x3f, 0x2d }, { 0x3a, 0x3f, 0x2d }, { 0x36, 0x3f, 0x2d }, { 0x31, 0x3f, 0x2d }, 433 { 0x2d, 0x3f, 0x2d }, { 0x2d, 0x3f, 0x31 }, { 0x2d, 0x3f, 0x36 }, { 0x2d, 0x3f, 0x3a }, 434 { 0x2d, 0x3f, 0x3f }, { 0x2d, 0x3a, 0x3f }, { 0x2d, 0x36, 0x3f }, { 0x2d, 0x31, 0x3f }, 435 { 0x00, 0x00, 0x1c }, { 0x07, 0x00, 0x1c }, { 0x0e, 0x00, 0x1c }, { 0x15, 0x00, 0x1c }, 436 { 0x1c, 0x00, 0x1c }, { 0x1c, 0x00, 0x15 }, { 0x1c, 0x00, 0x0e }, { 0x1c, 0x00, 0x07 }, 437 { 0x1c, 0x00, 0x00 }, { 0x1c, 0x07, 0x00 }, { 0x1c, 0x0e, 0x00 }, { 0x1c, 0x15, 0x00 }, 438 { 0x1c, 0x1c, 0x00 }, { 0x15, 0x1c, 0x00 }, { 0x0e, 0x1c, 0x00 }, { 0x07, 0x1c, 0x00 }, 439 { 0x00, 0x1c, 0x00 }, { 0x00, 0x1c, 0x07 }, { 0x00, 0x1c, 0x0e }, { 0x00, 0x1c, 0x15 }, 440 { 0x00, 0x1c, 0x1c }, { 0x00, 0x15, 0x1c }, { 0x00, 0x0e, 0x1c }, { 0x00, 0x07, 0x1c }, 441 { 0x0e, 0x0e, 0x1c }, { 0x11, 0x0e, 0x1c }, { 0x15, 0x0e, 0x1c }, { 0x18, 0x0e, 0x1c }, 442 { 0x1c, 0x0e, 0x1c }, { 0x1c, 0x0e, 0x18 }, { 0x1c, 0x0e, 0x15 }, { 0x1c, 0x0e, 0x11 }, 443 { 0x1c, 0x0e, 0x0e }, { 0x1c, 0x11, 0x0e }, { 0x1c, 0x15, 0x0e }, { 0x1c, 0x18, 0x0e }, 444 { 0x1c, 0x1c, 0x0e }, { 0x18, 0x1c, 0x0e }, { 0x15, 0x1c, 0x0e }, { 0x11, 0x1c, 0x0e }, 445 { 0x0e, 0x1c, 0x0e }, { 0x0e, 0x1c, 0x11 }, { 0x0e, 0x1c, 0x15 }, { 0x0e, 0x1c, 0x18 }, 446 { 0x0e, 0x1c, 0x1c }, { 0x0e, 0x18, 0x1c }, { 0x0e, 0x15, 0x1c }, { 0x0e, 0x11, 0x1c }, 447 { 0x14, 0x14, 0x1c }, { 0x16, 0x14, 0x1c }, { 0x18, 0x14, 0x1c }, { 0x1a, 0x14, 0x1c }, 448 { 0x1c, 0x14, 0x1c }, { 0x1c, 0x14, 0x1a }, { 0x1c, 0x14, 0x18 }, { 0x1c, 0x14, 0x16 }, 449 { 0x1c, 0x14, 0x14 }, { 0x1c, 0x16, 0x14 }, { 0x1c, 0x18, 0x14 }, { 0x1c, 0x1a, 0x14 }, 450 { 0x1c, 0x1c, 0x14 }, { 0x1a, 0x1c, 0x14 }, { 0x18, 0x1c, 0x14 }, { 0x16, 0x1c, 0x14 }, 451 { 0x14, 0x1c, 0x14 }, { 0x14, 0x1c, 0x16 }, { 0x14, 0x1c, 0x18 }, { 0x14, 0x1c, 0x1a }, 452 { 0x14, 0x1c, 0x1c }, { 0x14, 0x1a, 0x1c }, { 0x14, 0x18, 0x1c }, { 0x14, 0x16, 0x1c }, 453 { 0x00, 0x00, 0x10 }, { 0x04, 0x00, 0x10 }, { 0x08, 0x00, 0x10 }, { 0x0c, 0x00, 0x10 }, 454 { 0x10, 0x00, 0x10 }, { 0x10, 0x00, 0x0c }, { 0x10, 0x00, 0x08 }, { 0x10, 0x00, 0x04 }, 455 { 0x10, 0x00, 0x00 }, { 0x10, 0x04, 0x00 }, { 0x10, 0x08, 0x00 }, { 0x10, 0x0c, 0x00 }, 456 { 0x10, 0x10, 0x00 }, { 0x0c, 0x10, 0x00 }, { 0x08, 0x10, 0x00 }, { 0x04, 0x10, 0x00 }, 457 { 0x00, 0x10, 0x00 }, { 0x00, 0x10, 0x04 }, { 0x00, 0x10, 0x08 }, { 0x00, 0x10, 0x0c }, 458 { 0x00, 0x10, 0x10 }, { 0x00, 0x0c, 0x10 }, { 0x00, 0x08, 0x10 }, { 0x00, 0x04, 0x10 }, 459 { 0x08, 0x08, 0x10 }, { 0x0a, 0x08, 0x10 }, { 0x0c, 0x08, 0x10 }, { 0x0e, 0x08, 0x10 }, 460 { 0x10, 0x08, 0x10 }, { 0x10, 0x08, 0x0e }, { 0x10, 0x08, 0x0c }, { 0x10, 0x08, 0x0a }, 461 { 0x10, 0x08, 0x08 }, { 0x10, 0x0a, 0x08 }, { 0x10, 0x0c, 0x08 }, { 0x10, 0x0e, 0x08 }, 462 { 0x10, 0x10, 0x08 }, { 0x0e, 0x10, 0x08 }, { 0x0c, 0x10, 0x08 }, { 0x0a, 0x10, 0x08 }, 463 { 0x08, 0x10, 0x08 }, { 0x08, 0x10, 0x0a }, { 0x08, 0x10, 0x0c }, { 0x08, 0x10, 0x0e }, 464 { 0x08, 0x10, 0x10 }, { 0x08, 0x0e, 0x10 }, { 0x08, 0x0c, 0x10 }, { 0x08, 0x0a, 0x10 }, 465 { 0x0b, 0x0b, 0x10 }, { 0x0c, 0x0b, 0x10 }, { 0x0d, 0x0b, 0x10 }, { 0x0f, 0x0b, 0x10 }, 466 { 0x10, 0x0b, 0x10 }, { 0x10, 0x0b, 0x0f }, { 0x10, 0x0b, 0x0d }, { 0x10, 0x0b, 0x0c }, 467 { 0x10, 0x0b, 0x0b }, { 0x10, 0x0c, 0x0b }, { 0x10, 0x0d, 0x0b }, { 0x10, 0x0f, 0x0b }, 468 { 0x10, 0x10, 0x0b }, { 0x0f, 0x10, 0x0b }, { 0x0d, 0x10, 0x0b }, { 0x0c, 0x10, 0x0b }, 469 { 0x0b, 0x10, 0x0b }, { 0x0b, 0x10, 0x0c }, { 0x0b, 0x10, 0x0d }, { 0x0b, 0x10, 0x0f }, 470 { 0x0b, 0x10, 0x10 }, { 0x0b, 0x0f, 0x10 }, { 0x0b, 0x0d, 0x10 }, { 0x0b, 0x0c, 0x10 }, 471 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 472 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 473}; 474 475/* Prototype type declaration*/ 476static Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 477static void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 478static void vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 479static void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 480static void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 481static void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 482static void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 483static Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 484static BOOL bSetAST1180CRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 485static BOOL bSetAST1180OffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 486static BOOL bSetAST1180DCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 487static BOOL bSetAST1180ExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 488static void vInitChrontelReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 489 490Bool 491ASTSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode) 492{ 493 ASTRecPtr pAST; 494 VBIOS_MODE_INFO vgamodeinfo; 495 496 pAST = ASTPTR(pScrn); 497 498 /* pre set mode */ 499 bGetAST1000VGAModeInfo(pScrn, mode, &vgamodeinfo); 500 501 /* set mode */ 502 if (pAST->jChipType == AST1180) 503 { 504 bASTInitAST1180(pScrn); 505 506 bSetAST1180CRTCReg(pScrn, mode, &vgamodeinfo); 507 bSetAST1180OffsetReg(pScrn, mode, &vgamodeinfo); 508 bSetAST1180DCLKReg(pScrn, mode, &vgamodeinfo); 509 bSetAST1180ExtReg(pScrn, mode, &vgamodeinfo); 510 511 vInitChrontelReg(pScrn, mode, &vgamodeinfo); 512 } 513 else 514 { 515 vASTOpenKey(pScrn); 516 bASTRegInit(pScrn); 517 518 vAST1000DisplayOff(pScrn); 519 520 vSetStdReg(pScrn, mode, &vgamodeinfo); 521 vSetCRTCReg(pScrn, mode, &vgamodeinfo); 522 vSetOffsetReg(pScrn, mode, &vgamodeinfo); 523 vSetDCLKReg(pScrn, mode, &vgamodeinfo); 524 vSetExtReg(pScrn, mode, &vgamodeinfo); 525 vSetSyncReg(pScrn, mode, &vgamodeinfo); 526 bSetDACReg(pScrn, mode, &vgamodeinfo); 527 528 /* clear video buffer to avoid display noise */ 529 memset(pAST->FBVirtualAddr, 0x00, pAST->VideoModeInfo.ScreenPitch*pAST->VideoModeInfo.ScreenHeight); 530 531 vAST1000DisplayOn(pScrn); 532 } 533 534 /* post set mode */ 535#ifdef Accel_2D 536 if (!pAST->noAccel) { 537 if (!bASTEnable2D(pScrn, pAST)) { 538 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Enable 2D failed\n"); 539 pAST->noAccel = TRUE; 540 } 541 } 542#endif 543#ifdef HWC 544 if (!pAST->noHWC) { 545 if (!bASTInitHWC(pScrn, pAST)) { 546 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Init HWC failed\n"); 547 pAST->noHWC = TRUE; 548 } 549 } 550#endif 551 552 return (TRUE); 553} 554 555 556static Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 557{ 558 ASTRecPtr pAST; 559 ULONG ulModeID, ulColorIndex, ulRefreshRate, ulRefreshRateIndex = 0; 560 ULONG ulHBorder, ulVBorder; 561 Bool check_sync; 562 PVBIOS_ENHTABLE_STRUCT loop, best = NULL; 563 564 pAST = ASTPTR(pScrn); 565 566 switch (pScrn->bitsPerPixel) 567 { 568 case 8: 569 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[VGAModeIndex]; 570 ulColorIndex = VGAModeIndex-1; 571 break; 572 case 16: 573 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[HiCModeIndex]; 574 ulColorIndex = HiCModeIndex; 575 break; 576 case 24: 577 case 32: 578 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[TrueCModeIndex]; 579 ulColorIndex = TrueCModeIndex; 580 break; 581 default: 582 return (FALSE); 583 } 584 585 switch (mode->CrtcHDisplay) 586 { 587 case 640: 588 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res640x480Table[ulRefreshRateIndex]; 589 break; 590 case 800: 591 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res800x600Table[ulRefreshRateIndex]; 592 break; 593 case 1024: 594 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1024x768Table[ulRefreshRateIndex]; 595 break; 596 case 1280: 597 if (mode->CrtcVDisplay == 800) 598 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x800Table[ulRefreshRateIndex]; 599 else 600 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x1024Table[ulRefreshRateIndex]; 601 break; 602 case 1360: 603 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1360x768Table[ulRefreshRateIndex]; 604 break; 605 case 1440: 606 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1440x900Table[ulRefreshRateIndex]; 607 break; 608 case 1600: 609 if (mode->CrtcVDisplay == 900) 610 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1600x900Table[ulRefreshRateIndex]; 611 else 612 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1600x1200Table[ulRefreshRateIndex]; 613 break; 614 case 1680: 615 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1680x1050Table[ulRefreshRateIndex]; 616 break; 617 case 1920: 618 if (mode->CrtcVDisplay == 1080) 619 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1080Table[ulRefreshRateIndex]; 620 else 621 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1200Table[ulRefreshRateIndex]; 622 break; 623 default: 624 return (FALSE); 625 } 626 627 /* Get Proper Mode Index */ 628 ulRefreshRate = (mode->Clock * 1000) / (mode->HTotal * mode->VTotal) + 1; 629 loop = pVGAModeInfo->pEnhTableEntry; 630 check_sync = loop->Flags & WideScreenMode; 631 do { 632 while (loop->ulRefreshRate != 0xff) { 633 if ((check_sync) && 634 (((mode->Flags & V_NVSYNC) && 635 (loop->Flags & PVSync)) || 636 ((mode->Flags & V_PVSYNC) && 637 (loop->Flags & NVSync)) || 638 ((mode->Flags & V_NHSYNC) && 639 (loop->Flags & PHSync)) || 640 ((mode->Flags & V_PHSYNC) && 641 (loop->Flags & NHSync)))) { 642 loop++; 643 continue; 644 } 645 if (loop->ulRefreshRate <= ulRefreshRate 646 && (!best || loop->ulRefreshRate > best->ulRefreshRate)) 647 best = loop; 648 loop++; 649 } 650 if (best || !check_sync) 651 break; 652 check_sync = 0; 653 } while (1); 654 if (best) 655 pVGAModeInfo->pEnhTableEntry = best; 656 657 /* Update mode CRTC info */ 658 ulHBorder = (pVGAModeInfo->pEnhTableEntry->Flags & HBorder) ? 8:0; 659 ulVBorder = (pVGAModeInfo->pEnhTableEntry->Flags & VBorder) ? 8:0; 660 661 mode->CrtcHTotal = (int) pVGAModeInfo->pEnhTableEntry->HT; 662 mode->CrtcHBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder); 663 mode->CrtcHBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->HT - ulHBorder); 664 mode->CrtcHSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 665 + pVGAModeInfo->pEnhTableEntry->HFP); 666 mode->CrtcHSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 667 + pVGAModeInfo->pEnhTableEntry->HFP 668 + pVGAModeInfo->pEnhTableEntry->HSYNC); 669 670 mode->CrtcVTotal = (int) pVGAModeInfo->pEnhTableEntry->VT; 671 mode->CrtcVBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder); 672 mode->CrtcVBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->VT - ulVBorder); 673 mode->CrtcVSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 674 + pVGAModeInfo->pEnhTableEntry->VFP); 675 mode->CrtcVSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 676 + pVGAModeInfo->pEnhTableEntry->VFP 677 + pVGAModeInfo->pEnhTableEntry->VSYNC); 678 679 /* Write mode info to scratch */ 680 ulRefreshRateIndex = pVGAModeInfo->pEnhTableEntry->ulRefreshRateIndex; 681 ulModeID = pVGAModeInfo->pEnhTableEntry->ulModeID; 682 683 if (pAST->jChipType == AST1180) 684 { 685 /* TODO */ 686 } 687 else 688 { 689 SetIndexReg(CRTC_PORT, 0x8C, (UCHAR) ((ulColorIndex & 0x0F) << 4)); 690 SetIndexReg(CRTC_PORT, 0x8D, (UCHAR) (ulRefreshRateIndex & 0xFF)); 691 SetIndexReg(CRTC_PORT, 0x8E, (UCHAR) (ulModeID & 0xFF)); 692 693 /* NewModeInfo */ 694 SetIndexReg(CRTC_PORT, 0x91, 0x00); /* clear signature */ 695 if (pVGAModeInfo->pEnhTableEntry->Flags & NewModeInfo) 696 { 697 SetIndexReg(CRTC_PORT, 0x91, 0xA8); /* signature */ 698 SetIndexReg(CRTC_PORT, 0x92, (UCHAR) (pScrn->bitsPerPixel) ); 699 SetIndexReg(CRTC_PORT, 0x93, (UCHAR) (mode->Clock / 1000) ); 700 SetIndexReg(CRTC_PORT, 0x94, (UCHAR) (mode->CrtcHDisplay) ); 701 SetIndexReg(CRTC_PORT, 0x95, (UCHAR) (mode->CrtcHDisplay >> 8) ); /* color depth */ 702 SetIndexReg(CRTC_PORT, 0x96, (UCHAR) (mode->CrtcVDisplay) ); 703 SetIndexReg(CRTC_PORT, 0x97, (UCHAR) (mode->CrtcVDisplay >> 8) ); /* color depth */ 704 } 705 } 706 707 return (TRUE); 708} 709 710static void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 711{ 712 713 PVBIOS_STDTABLE_STRUCT pStdModePtr; 714 ASTRecPtr pAST; 715 ULONG i; 716 UCHAR jReg; 717 718 pStdModePtr = pVGAModeInfo->pStdTableEntry; 719 pAST = ASTPTR(pScrn); 720 721 /* Set Misc */ 722 jReg = pStdModePtr->MISC; 723 SetReg(MISC_PORT_WRITE,jReg); 724 725 /* Set Seq */ 726 SetIndexReg(SEQ_PORT,0x00, 0x03); 727 for (i=0; i<4; i++) 728 { 729 jReg = pStdModePtr->SEQ[i]; 730 if (!i) (jReg |= 0x20); /* display off */ 731 SetIndexReg(SEQ_PORT,(UCHAR) (i+1), jReg); 732 } 733 734 /* Set CRTC */ 735 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 736 for (i=0; i<25; i++) 737 { 738 jReg = pStdModePtr->CRTC[i]; 739 SetIndexReg(CRTC_PORT,(UCHAR) i, jReg); 740 } 741 742 /* Set AR */ 743 jReg = GetReg(INPUT_STATUS1_READ); 744 for (i=0; i<20; i++) 745 { 746 jReg = pStdModePtr->AR[i]; 747 SetReg(AR_PORT_WRITE, (UCHAR) i); 748 SetReg(AR_PORT_WRITE, jReg); 749 } 750 SetReg(AR_PORT_WRITE, 0x14); 751 SetReg(AR_PORT_WRITE, 0x00); 752 753 jReg = GetReg(INPUT_STATUS1_READ); 754 SetReg (AR_PORT_WRITE, 0x20); /* set POS */ 755 756 /* Set GR */ 757 for (i=0; i<9; i++) 758 { 759 jReg = pStdModePtr->GR[i]; 760 SetIndexReg(GR_PORT,(UCHAR) i, jReg); 761 762 } 763 764 765} 766 767static void 768vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 769{ 770 ASTRecPtr pAST; 771 USHORT usTemp, ulPreCache = 0; 772 UCHAR jReg05, jReg07, jReg09, jRegAC, jRegAD, jRegAE; 773 774 pAST = ASTPTR(pScrn); 775 jReg05 = jReg07 = jReg09 = jRegAC = jRegAD = jRegAE = 0; 776 777 /* init value */ 778 if ((pAST->jChipType == AST2500) && (pVGAModeInfo->pEnhTableEntry->Flags & AST2500PreCatchCRT)) 779 ulPreCache = 40; 780 781 /* unlock CRTC */ 782 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 783 784 /* Horizontal Timing Programming */ 785 usTemp = (mode->CrtcHTotal >> 3) - 5; 786 if (usTemp & 0x100) jRegAC |= 0x01; /* HT D[8] */ 787 SetIndexRegMask(CRTC_PORT,0x00, 0x00, (UCHAR) usTemp); 788 usTemp = (mode->CrtcHDisplay >> 3) - 1; 789 if (usTemp & 0x100) jRegAC |= 0x04; /* HDE D[8] */ 790 SetIndexRegMask(CRTC_PORT,0x01, 0x00, (UCHAR) usTemp); 791 usTemp = (mode->CrtcHBlankStart >> 3) - 1; 792 if (usTemp & 0x100) jRegAC |= 0x10; /* HBS D[8] */ 793 SetIndexRegMask(CRTC_PORT,0x02, 0x00, (UCHAR) usTemp); 794 usTemp = ((mode->CrtcHBlankEnd >> 3) - 1) & 0x7F; 795 if (usTemp & 0x20) jReg05 |= 0x80; /* HBE D[5] */ 796 if (usTemp & 0x40) jRegAD |= 0x01; /* HBE D[6] */ 797 SetIndexRegMask(CRTC_PORT,0x03, 0xE0, (UCHAR) (usTemp & 0x1F)); 798 usTemp = ((mode->CrtcHSyncStart - ulPreCache) >> 3 ) - 1; 799 if (usTemp & 0x100) jRegAC |= 0x40; /* HRS D[5] */ 800 SetIndexRegMask(CRTC_PORT,0x04, 0x00, (UCHAR) (usTemp)); 801 usTemp = (((mode->CrtcHSyncEnd - ulPreCache) >> 3 ) - 1) & 0x3F; 802 if (usTemp & 0x20) jRegAD |= 0x04; /* HRE D[5] */ 803 SetIndexRegMask(CRTC_PORT,0x05, 0x60, (UCHAR) ((usTemp & 0x1F) | jReg05)); 804 805 SetIndexRegMask(CRTC_PORT,0xAC, 0x00, (UCHAR) jRegAC); 806 SetIndexRegMask(CRTC_PORT,0xAD, 0x00, (UCHAR) jRegAD); 807 808 /* Vetical Timing Programming */ 809 usTemp = (mode->CrtcVTotal) - 2; 810 if (usTemp & 0x100) jReg07 |= 0x01; /* VT D[8] */ 811 if (usTemp & 0x200) jReg07 |= 0x20; 812 if (usTemp & 0x400) jRegAE |= 0x01; /* VT D[10] */ 813 SetIndexRegMask(CRTC_PORT,0x06, 0x00, (UCHAR) usTemp); 814 usTemp = (mode->CrtcVSyncStart) - 1; 815 if (usTemp & 0x100) jReg07 |= 0x04; /* VRS D[8] */ 816 if (usTemp & 0x200) jReg07 |= 0x80; /* VRS D[9] */ 817 if (usTemp & 0x400) jRegAE |= 0x08; /* VRS D[10] */ 818 SetIndexRegMask(CRTC_PORT,0x10, 0x00, (UCHAR) usTemp); 819 usTemp = ((mode->CrtcVSyncEnd) - 1) & 0x3F; 820 if (usTemp & 0x10) jRegAE |= 0x20; /* VRE D[4] */ 821 if (usTemp & 0x20) jRegAE |= 0x40; /* VRE D[5] */ 822 SetIndexRegMask(CRTC_PORT,0x11, 0x70, (UCHAR) (usTemp & 0x0F)); 823 usTemp = (mode->CrtcVDisplay) - 1; 824 if (usTemp & 0x100) jReg07 |= 0x02; /* VDE D[8] */ 825 if (usTemp & 0x200) jReg07 |= 0x40; /* VDE D[9] */ 826 if (usTemp & 0x400) jRegAE |= 0x02; /* VDE D[10] */ 827 SetIndexRegMask(CRTC_PORT,0x12, 0x00, (UCHAR) usTemp); 828 usTemp = (mode->CrtcVBlankStart) - 1; 829 if (usTemp & 0x100) jReg07 |= 0x08; /* VBS D[8] */ 830 if (usTemp & 0x200) jReg09 |= 0x20; /* VBS D[9] */ 831 if (usTemp & 0x400) jRegAE |= 0x04; /* VBS D[10] */ 832 SetIndexRegMask(CRTC_PORT,0x15, 0x00, (UCHAR) usTemp); 833 usTemp = (mode->CrtcVBlankEnd) - 1 ; 834 if (usTemp & 0x100) jRegAE |= 0x10; /* VBE D[8] */ 835 SetIndexRegMask(CRTC_PORT,0x16, 0x00, (UCHAR) usTemp); 836 837 SetIndexRegMask(CRTC_PORT,0x07, 0x00, (UCHAR) jReg07); 838 SetIndexRegMask(CRTC_PORT,0x09, 0xDF, (UCHAR) jReg09); 839 SetIndexRegMask(CRTC_PORT,0xAE, 0x00, (UCHAR) (jRegAE | 0x80)); /* disable line compare */ 840 841 if ((pAST->jChipType == AST2500) && (pVGAModeInfo->pEnhTableEntry->Flags & AST2500PreCatchCRT)) 842 { 843 SetIndexRegMask(CRTC_PORT,0xB6, 0x3F, 0x80); 844 } 845 else 846 { 847 SetIndexRegMask(CRTC_PORT,0xB6, 0x3F, 0x00); 848 } 849 850 /* lock CRTC */ 851 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x80); 852 853} 854 855static void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 856{ 857 ASTRecPtr pAST; 858 USHORT usOffset; 859 860 pAST = ASTPTR(pScrn); 861 862 usOffset = pAST->VideoModeInfo.ScreenPitch >> 3; /* Unit: char */ 863 864 SetIndexReg(CRTC_PORT,0x13, (UCHAR) (usOffset & 0xFF)); 865 SetIndexReg(CRTC_PORT,0xB0, (UCHAR) ((usOffset >> 8) & 0x3F)); 866 867} 868 869static void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 870{ 871 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 872 PVBIOS_DCLK_INFO pDCLKPtr; 873 ASTRecPtr pAST; 874 875 pAST = ASTPTR(pScrn); 876 877 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 878 if ((pAST->jChipType == AST2500) && (PCI_DEV_REVISION(pAST->PciInfo) > 0x40)) 879 pDCLKPtr = &DCLKTable_AST2500A1[pEnhModePtr->DCLKIndex]; 880 else if ((pAST->jChipType == AST2500) && (PCI_DEV_REVISION(pAST->PciInfo) == 0x40)) 881 pDCLKPtr = &DCLKTable_AST2500[pEnhModePtr->DCLKIndex]; 882 else if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) 883 pDCLKPtr = &DCLKTable_AST2100[pEnhModePtr->DCLKIndex]; 884 else 885 pDCLKPtr = &DCLKTable[pEnhModePtr->DCLKIndex]; 886 887 SetIndexRegMask(CRTC_PORT,0xC0, 0x00, pDCLKPtr->Param1); 888 SetIndexRegMask(CRTC_PORT,0xC1, 0x00, pDCLKPtr->Param2); 889 if ((pAST->jChipType == AST2500) && (PCI_DEV_REVISION(pAST->PciInfo) == 0x40)) 890 { 891 SetIndexRegMask(CRTC_PORT,0xBB, 0x0F, (pDCLKPtr->Param3 & 0xF0)); 892 } 893 else 894 { 895 SetIndexRegMask(CRTC_PORT,0xBB, 0x0F, (pDCLKPtr->Param3 & 0xC0) | ((pDCLKPtr->Param3 & 0x03) << 4) ); 896 } 897 898} 899 900 901static void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 902{ 903 904 ASTRecPtr pAST; 905 UCHAR jRegA0, jRegA3, jRegA8; 906 907 pAST = ASTPTR(pScrn); 908 909 jRegA0=jRegA3=jRegA8=0; 910 /* Mode Type Setting */ 911 switch (pScrn->bitsPerPixel) { 912 case 8: 913 jRegA0 = 0x70; 914 jRegA3 = 0x01; 915 jRegA8 = 0x00; 916 break; 917 case 15: 918 case 16: 919 jRegA0 = 0x70; 920 jRegA3 = 0x04; 921 jRegA8 = 0x02; 922 break; 923 case 32: 924 jRegA0 = 0x70; 925 jRegA3 = 0x08; 926 jRegA8 = 0x02; 927 break; 928 } 929 SetIndexRegMask(CRTC_PORT,0xA0, 0x8F, (UCHAR) jRegA0); 930 SetIndexRegMask(CRTC_PORT,0xA3, 0xF0, (UCHAR) jRegA3); 931 SetIndexRegMask(CRTC_PORT,0xA8, 0xFD, (UCHAR) jRegA8); 932 933#if defined(__sparc__) 934 UCHAR jRegA2 = 0x80; 935 if ((pScrn->bitsPerPixel == 15) || (pScrn->bitsPerPixel == 16) ) 936 jRegA2 |= 0x40; 937 SetIndexRegMask(CRTC_PORT,0xA2, 0x3F, (UCHAR) jRegA2); 938#endif 939 940 /* Set Threshold */ 941 if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500)) 942 { 943 SetIndexReg(CRTC_PORT,0xA7, 0x78); 944 SetIndexReg(CRTC_PORT,0xA6, 0x60); 945 } 946 else if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) ) 947 { 948 SetIndexReg(CRTC_PORT,0xA7, 0x3F); 949 SetIndexReg(CRTC_PORT,0xA6, 0x2F); 950 } 951 else 952 { 953 SetIndexReg(CRTC_PORT,0xA7, 0x2F); 954 SetIndexReg(CRTC_PORT,0xA6, 0x1F); 955 } 956 957} 958 959static void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 960{ 961 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 962 ASTRecPtr pAST; 963 UCHAR jReg; 964 965 pAST = ASTPTR(pScrn); 966 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 967 968 jReg = GetReg(MISC_PORT_READ); 969 jReg &= ~0xC0; 970 if (pEnhModePtr->Flags & NVSync) jReg |= 0x80; 971 if (pEnhModePtr->Flags & NHSync) jReg |= 0x40; 972 SetReg(MISC_PORT_WRITE,jReg); 973} 974 975static Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 976{ 977 PVBIOS_DAC_INFO pDACPtr; 978 ASTRecPtr pAST; 979 ULONG i, ulDACNumber; 980 UCHAR DACR, DACG, DACB; 981 982 pAST = ASTPTR(pScrn); 983 984 switch (pScrn->bitsPerPixel) 985 { 986 case 8: 987 ulDACNumber = DAC_NUM_VGA; 988 pDACPtr = (PVBIOS_DAC_INFO) &DAC_VGA[0]; 989 break; 990 default: 991 return (FALSE); 992 } 993 994 for (i=0; i<ulDACNumber; i++) 995 { 996 DACR = pDACPtr->DACR; 997 DACG = pDACPtr->DACG; 998 DACB = pDACPtr->DACB; 999 1000 VGA_LOAD_PALETTE_INDEX (i, DACR, DACG, DACB); 1001 1002 pDACPtr++; 1003 } 1004 1005 return (TRUE); 1006 1007} 1008 1009static ULONG AST1180DCLKTable [] = { 1010 0x0008676b, /* 00: VCLK25_175 */ 1011 0x00086342, /* 01: VCLK28_322 */ 1012 0x00086568, /* 02: VCLK31_5 */ 1013 0x00082118, /* 03: VCLK36 */ 1014 0x0008232e, /* 04: VCLK40 */ 1015 0x000c256d, /* 05: VCLK49_5 */ 1016 0x00082016, /* 06: VCLK50 */ 1017 0x000c0010, /* 07: VCLK56_25 */ 1018 0x000c0332, /* 08: VCLK65 */ 1019 0x00080010, /* 09: VCLK75 */ 1020 0x000c033d, /* 0A: VCLK78_75 */ 1021 0x000c0568, /* 0B: VCLK94_5 */ 1022 0x00040118, /* 0C: VCLK108 */ 1023 0x00040334, /* 0D: VCLK135 */ 1024 0x0004033d, /* 0E: VCLK157_5 */ 1025 0x00040018, /* 0F: VCLK162 */ 1026 0x00040123, /* 10: VCLK154 */ 1027 0x000c0669, /* 11: VCLK83_5 */ 1028 0x0004074b, /* 12: VCLK106_5 */ 1029 0x0004022d, /* 13: VCLK146_25 */ 1030 0x00040769, /* 14: VCLK148_5 */ 1031}; 1032 1033static BOOL bSetAST1180CRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1034{ 1035 ASTRecPtr pAST = ASTPTR(pScrn); 1036 1037 ULONG HTIndex, HRIndex, VTIndex, VRIndex; 1038 ULONG HT, HDE, HBS, HBE, HRS, HRE; 1039 ULONG VT, VDE, VBS, VBE, VRS, VRE; 1040 ULONG HT2, HDE2, HRS2, HRE2; 1041 ULONG VT2, VDE2, VRS2, VRE2; 1042 1043 /* Reg. Index Select */ 1044 { 1045 HTIndex = AST1180_VGA1_HTREG; 1046 HRIndex = AST1180_VGA1_HRREG; 1047 VTIndex = AST1180_VGA1_VTREG; 1048 VRIndex = AST1180_VGA1_VRREG; 1049 } 1050 1051 /* Get CRTC Info */ 1052 HT = mode->CrtcHTotal; 1053 HDE= mode->CrtcHDisplay; 1054 HBS= mode->CrtcHBlankStart; 1055 HBE= mode->CrtcHBlankEnd; 1056 HRS= mode->CrtcHSyncStart; 1057 HRE= mode->CrtcHSyncEnd; 1058 VT = mode->CrtcVTotal; 1059 VDE= mode->CrtcVDisplay; 1060 VBS= mode->CrtcVBlankStart; 1061 VBE= mode->CrtcVBlankEnd; 1062 VRS= mode->CrtcVSyncStart; 1063 VRE= mode->CrtcVSyncEnd; 1064 1065 /* Calculate CRTC Reg Setting */ 1066 HT2 = HT - 1; 1067 HDE2 = HDE - 1; 1068 HRS2 = HRS - 1; 1069 HRE2 = HRE - 1; 1070 VT2 = VT - 1; 1071 VDE2 = VDE - 1; 1072 VRS2 = VRS - 1; 1073 VRE2 = VRE - 1; 1074 1075 /* Write Reg */ 1076 WriteAST1180SOC(AST1180_GFX_BASE + HTIndex, (ULONG)(HDE2 << 16) | (ULONG) (HT2)); 1077 WriteAST1180SOC(AST1180_GFX_BASE + HRIndex, (ULONG)(HRE2 << 16) | (ULONG) (HRS2)); 1078 WriteAST1180SOC(AST1180_GFX_BASE + VTIndex, (ULONG)(VDE2 << 16) | (ULONG) (VT2)); 1079 WriteAST1180SOC(AST1180_GFX_BASE + VRIndex, (ULONG)(VRE2 << 16) | (ULONG) (VRS2)); 1080 1081 return (TRUE); 1082 1083} /* bSetAST1180CRTCReg */ 1084 1085static BOOL bSetAST1180OffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1086{ 1087 ASTRecPtr pAST = ASTPTR(pScrn); 1088 ULONG ulOffset, ulTermalCount; 1089 1090 ulOffset = pAST->VideoModeInfo.ScreenPitch; 1091 ulTermalCount = (pAST->VideoModeInfo.ScreenPitch + 7) >> 3; 1092 1093 /* Write Reg */ 1094 WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_OFFSET, (ULONG) (ulTermalCount << 16) | (ULONG) (ulOffset)); 1095 1096 return (TRUE); 1097 1098} /* bSetAST1180OffsetReg */ 1099 1100static BOOL bSetAST1180DCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1101{ 1102 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 1103 ASTRecPtr pAST = ASTPTR(pScrn); 1104 ULONG ulDCLK; 1105 1106 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1107 ulDCLK = AST1180DCLKTable[pEnhModePtr->DCLKIndex]; 1108 if (pEnhModePtr->Flags & HalfDCLK) 1109 ulDCLK |= 0x00400000; /* D[22]: div by 2 */ 1110 WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_PLL, ulDCLK); 1111 1112 return (TRUE); 1113} 1114 1115static BOOL bSetAST1180ExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1116{ 1117 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 1118 ASTRecPtr pAST = ASTPTR(pScrn); 1119 1120 ULONG ulCtlRegIndex, ulCtlReg; /* enable display */ 1121 ULONG ulCtlReg2Index, ulCtlReg2 = 0x80; /* single edge */ 1122 ULONG ulThresholdRegIndex ; /* Threshold */ 1123 ULONG ulStartAddressIndex; /* ulStartAddress */ 1124 ULONG ulStartAddress = pAST->ulVRAMBase; 1125 1126 /* Reg. Index Select */ 1127 { 1128 ulCtlRegIndex = AST1180_VGA1_CTRL; 1129 ulCtlReg2Index = AST1180_VGA1_CTRL2; 1130 ulThresholdRegIndex = AST1180_VGA1_THRESHOLD; 1131 ulStartAddressIndex = AST1180_VGA1_STARTADDR; 1132 } 1133 1134 /* Mode Type Setting */ 1135 ulCtlReg = 0x30000000; 1136 { 1137 switch (pScrn->bitsPerPixel) { 1138 case 15: 1139 case 16: 1140 ulCtlReg |= 0x100001; /* RGB565, SCREEN OFF, ENABLE */ 1141 break; 1142 case 32: 1143 ulCtlReg |= 0x100101; /* XRGB8888, SCREEN OFF, ENABLE */ 1144 break; 1145 } 1146 } 1147 1148 /* Polarity */ 1149 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1150 ulCtlReg |= (ULONG) (pEnhModePtr->Flags & SyncNN) << 10; 1151 1152 /* Single/Dual Edge */ 1153 ulCtlReg2 |= 0x40; /* dual-edge */ 1154 1155 /* Write Reg */ 1156 WriteAST1180SOC(AST1180_GFX_BASE + ulStartAddressIndex, ulStartAddress); 1157 WriteAST1180SOC(AST1180_GFX_BASE + ulThresholdRegIndex, ((ULONG) CRT_HIGH_THRESHOLD_VALUE << 8) | (ULONG) (CRT_LOW_THRESHOLD_VALUE)); 1158 WriteAST1180SOC(AST1180_GFX_BASE + ulCtlReg2Index, ulCtlReg2); 1159 WriteAST1180SOC(AST1180_GFX_BASE + ulCtlRegIndex, ulCtlReg); 1160 1161 return (TRUE); 1162 1163} /* bSetAST1180ExtReg */ 1164 1165#define I2C_BASE_AST1180 0x80fcb000 1166#define I2C_DEVICEADDR_AST1180 0x0EC /* slave addr */ 1167 1168static void SetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex, UCHAR jData ) 1169{ 1170 ULONG ulData, ulI2CAddr, ulI2CPortBase; 1171 ULONG retry; 1172 1173 { 1174 ulI2CPortBase = I2C_BASE_AST1180 + 0x40 * jChannel; 1175 ulI2CAddr = I2C_DEVICEADDR_AST1180; 1176 } 1177 1178 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x00); 1179 WriteAST1180SOC(ulI2CPortBase + 0x04, 0x77743355); 1180 WriteAST1180SOC(ulI2CPortBase + 0x08, 0x0); 1181 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1182 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x1); 1183 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xAF); 1184 WriteAST1180SOC(ulI2CPortBase + 0x20, ulI2CAddr); 1185 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x03); 1186 retry = 0; 1187 do { 1188 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1189 usleep(10); 1190 if (retry++ > 1000) 1191 goto Exit_SetChrontelReg; 1192 } while (!(ulData & 0x01)); 1193 1194 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1195 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jIndex); 1196 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1197 do { 1198 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1199 } while (!(ulData & 0x01)); 1200 1201 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1202 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jData); 1203 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1204 do { 1205 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1206 } while (!(ulData & 0x01)); 1207 1208 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1209 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xBF); 1210 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x20); 1211 do { 1212 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1213 } while (!(ulData & 0x10)); 1214 1215 ReadAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1216 ulData &= 0xffffffef; 1217 WriteAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1218 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1219 1220Exit_SetChrontelReg: 1221 ; 1222} 1223 1224static UCHAR GetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex) 1225{ 1226 ULONG ulData, ulI2CAddr, ulI2CPortBase; 1227 UCHAR jData; 1228 ULONG retry; 1229 1230 { 1231 ulI2CPortBase = I2C_BASE_AST1180 + 0x40 * jChannel; 1232 ulI2CAddr = I2C_DEVICEADDR_AST1180; 1233 } 1234 1235 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x00); 1236 WriteAST1180SOC(ulI2CPortBase + 0x04, 0x77743355); 1237 WriteAST1180SOC(ulI2CPortBase + 0x08, 0x0); 1238 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1239 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x1); 1240 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xAF); 1241 WriteAST1180SOC(ulI2CPortBase + 0x20, ulI2CAddr); 1242 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x03); 1243 retry = 0; 1244 do { 1245 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1246 usleep(10); 1247 if (retry++ > 1000) 1248 return 0; 1249 } while (!(ulData & 0x01)); 1250 1251 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1252 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jIndex); 1253 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1254 do { 1255 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1256 } while (!(ulData & 0x01)); 1257 1258 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1259 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) (ulI2CAddr + 1) ); 1260 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x1B); 1261 do { 1262 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1263 } while (!(ulData & 0x04)); 1264 1265 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1266 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xBF); 1267 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x20); 1268 do { 1269 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1270 } while (!(ulData & 0x10)); 1271 1272 ReadAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1273 ulData &= 0xffffffef; 1274 WriteAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1275 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1276 1277 ReadAST1180SOC(ulI2CPortBase + 0x20, ulData); 1278 jData = (UCHAR) ((ulData & 0xFF00) >> 8); 1279 1280 return (jData); 1281} 1282 1283static void vInitChrontelReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1284{ 1285 1286 PVBIOS_ENHTABLE_STRUCT pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1287 ASTRecPtr pAST = ASTPTR(pScrn); 1288 ULONG ulDCLK = 65; /* todo */ 1289 UCHAR jReg; 1290 1291 jReg = GetChrontelReg(pAST, 1, 0x4A); /* get vendor id */ 1292 if (jReg == 0x95) 1293 { 1294 jReg = GetChrontelReg(pAST, 1, 0x20); /* DVI/D-Sub */ 1295 if (jReg & 0x20) /* DVI */ 1296 { 1297 1298 /* DVI PLL Filter */ 1299 if (ulDCLK > 65) 1300 { 1301 SetChrontelReg(pAST, 1, 0x33, 0x06); 1302 SetChrontelReg(pAST, 1, 0x34, 0x26); 1303 SetChrontelReg(pAST, 1, 0x36, 0xA0); 1304 } 1305 else 1306 { 1307 SetChrontelReg(pAST, 1, 0x33, 0x08); 1308 SetChrontelReg(pAST, 1, 0x34, 0x16); 1309 SetChrontelReg(pAST, 1, 0x36, 0x60); 1310 } 1311 1312 SetChrontelReg(pAST, 1, 0x49, 0xc0); 1313 } 1314 else /* D-Sub */ 1315 { 1316 1317 SetChrontelReg(pAST, 1, 0x21, 0x09); 1318 SetChrontelReg(pAST, 1, 0x49, 0x00); 1319 SetChrontelReg(pAST, 1, 0x56, 0x00); 1320 } 1321 } 1322 1323} 1324 1325