ast_mode.c revision 7fe5393c
1/* 2 * Copyright (c) 2005 ASPEED Technology Inc. 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that 7 * copyright notice and this permission notice appear in supporting 8 * documentation, and that the name of the authors not be used in 9 * advertising or publicity pertaining to distribution of the software without 10 * specific, written prior permission. The authors makes no representations 11 * about the suitability of this software for any purpose. It is provided 12 * "as is" without express or implied warranty. 13 * 14 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#ifdef HAVE_CONFIG_H 24#include <config.h> 25#endif 26#include "xf86.h" 27#include "xf86_OSproc.h" 28#include "xf86cmap.h" 29#include "compiler.h" 30#include "vgaHW.h" 31#include "mipointer.h" 32#include "micmap.h" 33 34#include "fb.h" 35#include "regionstr.h" 36#include "xf86xv.h" 37#include <X11/extensions/Xv.h> 38 39#include "xf86PciInfo.h" 40#include "xf86Pci.h" 41 42/* framebuffer offscreen manager */ 43#include "xf86fbman.h" 44 45/* include xaa includes */ 46#include "xaarop.h" 47 48/* H/W cursor support */ 49#include "xf86Cursor.h" 50 51/* usleep() */ 52#include <unistd.h> 53 54/* Driver specific headers */ 55#include "ast.h" 56 57/* external reference fucntion */ 58extern Bool bInitAST1180(ScrnInfoPtr pScrn); 59 60VBIOS_STDTABLE_STRUCT StdTable[] = { 61 /* MD_2_3_400 */ 62 { 63 0x67, 64 {0x00,0x03,0x00,0x02}, 65 {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, 66 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, 67 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, 68 0xff}, 69 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 70 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 71 0x0c,0x00,0x0f,0x08}, 72 {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, 73 0xff} 74 }, 75 /* Mode12/ExtEGATable */ 76 { 77 0xe3, 78 {0x01,0x0f,0x00,0x06}, 79 {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, 80 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 81 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, 82 0xff}, 83 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 84 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 85 0x01,0x00,0x0f,0x00}, 86 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 87 0xff} 88 }, 89 /* ExtVGATable */ 90 { 91 0x2f, 92 {0x01,0x0f,0x00,0x0e}, 93 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 94 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 95 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 96 0xff}, 97 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 98 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 99 0x01,0x00,0x00,0x00}, 100 {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, 101 0xff} 102 }, 103 /* ExtHiCTable */ 104 { 105 0x2f, 106 {0x01,0x0f,0x00,0x0e}, 107 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 108 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 109 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 110 0xff}, 111 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 112 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 113 0x01,0x00,0x00,0x00}, 114 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 115 0xff} 116 }, 117 /* ExtTrueCTable */ 118 { 119 0x2f, 120 {0x01,0x0f,0x00,0x0e}, 121 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 122 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 123 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 124 0xff}, 125 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 126 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 127 0x01,0x00,0x00,0x00}, 128 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 129 0xff} 130 }, 131}; 132 133VBIOS_ENHTABLE_STRUCT Res640x480Table[] = { 134 { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ 135 (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, 136 { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ 137 (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, 138 { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ 139 (SyncNN | Charx8Dot) , 75, 3, 0x2E }, 140 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ 141 (SyncNN | Charx8Dot) , 85, 4, 0x2E }, 142 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ 143 (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, 144}; 145 146 147VBIOS_ENHTABLE_STRUCT Res800x600Table[] = { 148 {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ 149 (SyncPP | Charx8Dot), 56, 1, 0x30 }, 150 {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ 151 (SyncPP | Charx8Dot), 60, 2, 0x30 }, 152 {1040, 800, 56, 120, 666, 600, 37, 6, VCLK50, /* 72Hz */ 153 (SyncPP | Charx8Dot), 72, 3, 0x30 }, 154 {1056, 800, 16, 80, 625, 600, 1, 3, VCLK49_5, /* 75Hz */ 155 (SyncPP | Charx8Dot), 75, 4, 0x30 }, 156 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* 85Hz */ 157 (SyncPP | Charx8Dot), 84, 5, 0x30 }, 158 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* end */ 159 (SyncPP | Charx8Dot), 0xFF, 5, 0x30 }, 160}; 161 162 163VBIOS_ENHTABLE_STRUCT Res1024x768Table[] = { 164 {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ 165 (SyncNN | Charx8Dot), 60, 1, 0x31 }, 166 {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ 167 (SyncNN | Charx8Dot), 70, 2, 0x31 }, 168 {1312, 1024, 16, 96, 800, 768, 1, 3, VCLK78_75, /* 75Hz */ 169 (SyncPP | Charx8Dot), 75, 3, 0x31 }, 170 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* 85Hz */ 171 (SyncPP | Charx8Dot), 84, 4, 0x31 }, 172 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* end */ 173 (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, 174}; 175 176VBIOS_ENHTABLE_STRUCT Res1280x1024Table[] = { 177 {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ 178 (SyncPP | Charx8Dot), 60, 1, 0x32 }, 179 {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ 180 (SyncPP | Charx8Dot), 75, 2, 0x32 }, 181 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* 85Hz */ 182 (SyncPP | Charx8Dot), 85, 3, 0x32 }, 183 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* end */ 184 (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, 185}; 186 187VBIOS_ENHTABLE_STRUCT Res1600x1200Table[] = { 188 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ 189 (SyncPP | Charx8Dot), 60, 1, 0x33 }, 190 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ 191 (SyncPP | Charx8Dot), 0xFF, 1, 0x33 }, 192}; 193 194/* 16:9 */ 195VBIOS_ENHTABLE_STRUCT Res1360x768Table[] = { 196 {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ 197 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, 198 {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ 199 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, 200}; 201 202VBIOS_ENHTABLE_STRUCT Res1600x900Table[] = { 203 {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ 204 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, 205 {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* end */ 206 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x3A }, 207}; 208 209VBIOS_ENHTABLE_STRUCT Res1920x1080Table[] = { 210 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* HDTV 60Hz */ 211 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 }, 212 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* end */ 213 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 }, 214}; 215 216/* 16:10 */ 217VBIOS_ENHTABLE_STRUCT Res1280x800Table[] = { 218 {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ 219 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 35 }, 220 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ 221 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 }, 222 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ 223 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x35 }, 224 225}; 226 227VBIOS_ENHTABLE_STRUCT Res1440x900Table[] = { 228 {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ 229 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, 230 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ 231 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, 232 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ 233 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x36 }, 234}; 235 236VBIOS_ENHTABLE_STRUCT Res1680x1050Table[] = { 237 {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ 238 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, 239 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ 240 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, 241 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ 242 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x37 }, 243}; 244 245VBIOS_ENHTABLE_STRUCT Res1920x1200Table[] = { 246 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 247 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 }, 248 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 249 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 }, 250}; 251 252VBIOS_DCLK_INFO DCLKTable [] = { 253 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 254 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 255 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 256 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 257 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 258 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 259 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 260 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 261 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 262 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 263 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 264 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 265 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 266 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 267 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 268 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 269 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 270 {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */ 271 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 272 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 273 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 274 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 275 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 276 {0x77, 0x58, 0x80}, /* 17: VCLK119 */ 277 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ 278}; 279 280VBIOS_DCLK_INFO DCLKTable_AST2100 [] = { 281 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 282 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 283 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 284 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 285 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 286 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 287 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 288 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 289 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 290 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 291 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 292 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 293 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 294 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 295 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 296 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 297 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 298 {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ 299 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 300 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 301 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 302 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 303 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 304 {0x77, 0x58, 0x80}, /* 17: VCLK119 */ 305 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ 306}; 307 308VBIOS_DAC_INFO DAC_TEXT[] = { 309 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 310 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 311 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 312 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 313 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 314 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 315 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 316 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 317 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 318 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 319 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 320 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 321 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 322 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 323 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 324 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 325}; 326 327VBIOS_DAC_INFO DAC_EGA[] = { 328 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 329 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 330 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 331 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 332 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 333 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 334 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 335 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 336 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 337 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 338 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 339 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 340 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 341 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 342 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 343 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 344}; 345 346VBIOS_DAC_INFO DAC_VGA[] = { 347 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 348 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x15, 0x00 }, { 0x2a, 0x2a, 0x2a }, 349 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 350 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 351 { 0x00, 0x00, 0x00 }, { 0x05, 0x05, 0x05 }, { 0x08, 0x08, 0x08 }, { 0x0b, 0x0b, 0x0b }, 352 { 0x0e, 0x0e, 0x0e }, { 0x11, 0x11, 0x11 }, { 0x14, 0x14, 0x14 }, { 0x18, 0x18, 0x18 }, 353 { 0x1c, 0x1c, 0x1c }, { 0x20, 0x20, 0x20 }, { 0x24, 0x24, 0x24 }, { 0x28, 0x28, 0x28 }, 354 { 0x2d, 0x2d, 0x2d }, { 0x32, 0x32, 0x32 }, { 0x38, 0x38, 0x38 }, { 0x3f, 0x3f, 0x3f }, 355 { 0x00, 0x00, 0x3f }, { 0x10, 0x00, 0x3f }, { 0x1f, 0x00, 0x3f }, { 0x2f, 0x00, 0x3f }, 356 { 0x3f, 0x00, 0x3f }, { 0x3f, 0x00, 0x2f }, { 0x3f, 0x00, 0x1f }, { 0x3f, 0x00, 0x10 }, 357 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x10, 0x00 }, { 0x3f, 0x1f, 0x00 }, { 0x3f, 0x2f, 0x00 }, 358 { 0x3f, 0x3f, 0x00 }, { 0x2f, 0x3f, 0x00 }, { 0x1f, 0x3f, 0x00 }, { 0x10, 0x3f, 0x00 }, 359 { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x10 }, { 0x00, 0x3f, 0x1f }, { 0x00, 0x3f, 0x2f }, 360 { 0x00, 0x3f, 0x3f }, { 0x00, 0x2f, 0x3f }, { 0x00, 0x1f, 0x3f }, { 0x00, 0x10, 0x3f }, 361 { 0x1f, 0x1f, 0x3f }, { 0x27, 0x1f, 0x3f }, { 0x2f, 0x1f, 0x3f }, { 0x37, 0x1f, 0x3f }, 362 { 0x3f, 0x1f, 0x3f }, { 0x3f, 0x1f, 0x37 }, { 0x3f, 0x1f, 0x2f }, { 0x3f, 0x1f, 0x27 }, 363 { 0x3f, 0x1f, 0x1f }, { 0x3f, 0x27, 0x1f }, { 0x3f, 0x2f, 0x1f }, { 0x3f, 0x37, 0x1f }, 364 { 0x3f, 0x3f, 0x1f }, { 0x37, 0x3f, 0x1f }, { 0x2f, 0x3f, 0x1f }, { 0x27, 0x3f, 0x1f }, 365 { 0x1f, 0x3f, 0x1f }, { 0x1f, 0x3f, 0x27 }, { 0x1f, 0x3f, 0x2f }, { 0x1f, 0x3f, 0x37 }, 366 { 0x1f, 0x3f, 0x3f }, { 0x1f, 0x37, 0x3f }, { 0x1f, 0x2f, 0x3f }, { 0x1f, 0x27, 0x3f }, 367 { 0x2d, 0x2d, 0x3f }, { 0x31, 0x2d, 0x3f }, { 0x36, 0x2d, 0x3f }, { 0x3a, 0x2d, 0x3f }, 368 { 0x3f, 0x2d, 0x3f }, { 0x3f, 0x2d, 0x3a }, { 0x3f, 0x2d, 0x36 }, { 0x3f, 0x2d, 0x31 }, 369 { 0x3f, 0x2d, 0x2d }, { 0x3f, 0x31, 0x2d }, { 0x3f, 0x36, 0x2d }, { 0x3f, 0x3a, 0x2d }, 370 { 0x3f, 0x3f, 0x2d }, { 0x3a, 0x3f, 0x2d }, { 0x36, 0x3f, 0x2d }, { 0x31, 0x3f, 0x2d }, 371 { 0x2d, 0x3f, 0x2d }, { 0x2d, 0x3f, 0x31 }, { 0x2d, 0x3f, 0x36 }, { 0x2d, 0x3f, 0x3a }, 372 { 0x2d, 0x3f, 0x3f }, { 0x2d, 0x3a, 0x3f }, { 0x2d, 0x36, 0x3f }, { 0x2d, 0x31, 0x3f }, 373 { 0x00, 0x00, 0x1c }, { 0x07, 0x00, 0x1c }, { 0x0e, 0x00, 0x1c }, { 0x15, 0x00, 0x1c }, 374 { 0x1c, 0x00, 0x1c }, { 0x1c, 0x00, 0x15 }, { 0x1c, 0x00, 0x0e }, { 0x1c, 0x00, 0x07 }, 375 { 0x1c, 0x00, 0x00 }, { 0x1c, 0x07, 0x00 }, { 0x1c, 0x0e, 0x00 }, { 0x1c, 0x15, 0x00 }, 376 { 0x1c, 0x1c, 0x00 }, { 0x15, 0x1c, 0x00 }, { 0x0e, 0x1c, 0x00 }, { 0x07, 0x1c, 0x00 }, 377 { 0x00, 0x1c, 0x00 }, { 0x00, 0x1c, 0x07 }, { 0x00, 0x1c, 0x0e }, { 0x00, 0x1c, 0x15 }, 378 { 0x00, 0x1c, 0x1c }, { 0x00, 0x15, 0x1c }, { 0x00, 0x0e, 0x1c }, { 0x00, 0x07, 0x1c }, 379 { 0x0e, 0x0e, 0x1c }, { 0x11, 0x0e, 0x1c }, { 0x15, 0x0e, 0x1c }, { 0x18, 0x0e, 0x1c }, 380 { 0x1c, 0x0e, 0x1c }, { 0x1c, 0x0e, 0x18 }, { 0x1c, 0x0e, 0x15 }, { 0x1c, 0x0e, 0x11 }, 381 { 0x1c, 0x0e, 0x0e }, { 0x1c, 0x11, 0x0e }, { 0x1c, 0x15, 0x0e }, { 0x1c, 0x18, 0x0e }, 382 { 0x1c, 0x1c, 0x0e }, { 0x18, 0x1c, 0x0e }, { 0x15, 0x1c, 0x0e }, { 0x11, 0x1c, 0x0e }, 383 { 0x0e, 0x1c, 0x0e }, { 0x0e, 0x1c, 0x11 }, { 0x0e, 0x1c, 0x15 }, { 0x0e, 0x1c, 0x18 }, 384 { 0x0e, 0x1c, 0x1c }, { 0x0e, 0x18, 0x1c }, { 0x0e, 0x15, 0x1c }, { 0x0e, 0x11, 0x1c }, 385 { 0x14, 0x14, 0x1c }, { 0x16, 0x14, 0x1c }, { 0x18, 0x14, 0x1c }, { 0x1a, 0x14, 0x1c }, 386 { 0x1c, 0x14, 0x1c }, { 0x1c, 0x14, 0x1a }, { 0x1c, 0x14, 0x18 }, { 0x1c, 0x14, 0x16 }, 387 { 0x1c, 0x14, 0x14 }, { 0x1c, 0x16, 0x14 }, { 0x1c, 0x18, 0x14 }, { 0x1c, 0x1a, 0x14 }, 388 { 0x1c, 0x1c, 0x14 }, { 0x1a, 0x1c, 0x14 }, { 0x18, 0x1c, 0x14 }, { 0x16, 0x1c, 0x14 }, 389 { 0x14, 0x1c, 0x14 }, { 0x14, 0x1c, 0x16 }, { 0x14, 0x1c, 0x18 }, { 0x14, 0x1c, 0x1a }, 390 { 0x14, 0x1c, 0x1c }, { 0x14, 0x1a, 0x1c }, { 0x14, 0x18, 0x1c }, { 0x14, 0x16, 0x1c }, 391 { 0x00, 0x00, 0x10 }, { 0x04, 0x00, 0x10 }, { 0x08, 0x00, 0x10 }, { 0x0c, 0x00, 0x10 }, 392 { 0x10, 0x00, 0x10 }, { 0x10, 0x00, 0x0c }, { 0x10, 0x00, 0x08 }, { 0x10, 0x00, 0x04 }, 393 { 0x10, 0x00, 0x00 }, { 0x10, 0x04, 0x00 }, { 0x10, 0x08, 0x00 }, { 0x10, 0x0c, 0x00 }, 394 { 0x10, 0x10, 0x00 }, { 0x0c, 0x10, 0x00 }, { 0x08, 0x10, 0x00 }, { 0x04, 0x10, 0x00 }, 395 { 0x00, 0x10, 0x00 }, { 0x00, 0x10, 0x04 }, { 0x00, 0x10, 0x08 }, { 0x00, 0x10, 0x0c }, 396 { 0x00, 0x10, 0x10 }, { 0x00, 0x0c, 0x10 }, { 0x00, 0x08, 0x10 }, { 0x00, 0x04, 0x10 }, 397 { 0x08, 0x08, 0x10 }, { 0x0a, 0x08, 0x10 }, { 0x0c, 0x08, 0x10 }, { 0x0e, 0x08, 0x10 }, 398 { 0x10, 0x08, 0x10 }, { 0x10, 0x08, 0x0e }, { 0x10, 0x08, 0x0c }, { 0x10, 0x08, 0x0a }, 399 { 0x10, 0x08, 0x08 }, { 0x10, 0x0a, 0x08 }, { 0x10, 0x0c, 0x08 }, { 0x10, 0x0e, 0x08 }, 400 { 0x10, 0x10, 0x08 }, { 0x0e, 0x10, 0x08 }, { 0x0c, 0x10, 0x08 }, { 0x0a, 0x10, 0x08 }, 401 { 0x08, 0x10, 0x08 }, { 0x08, 0x10, 0x0a }, { 0x08, 0x10, 0x0c }, { 0x08, 0x10, 0x0e }, 402 { 0x08, 0x10, 0x10 }, { 0x08, 0x0e, 0x10 }, { 0x08, 0x0c, 0x10 }, { 0x08, 0x0a, 0x10 }, 403 { 0x0b, 0x0b, 0x10 }, { 0x0c, 0x0b, 0x10 }, { 0x0d, 0x0b, 0x10 }, { 0x0f, 0x0b, 0x10 }, 404 { 0x10, 0x0b, 0x10 }, { 0x10, 0x0b, 0x0f }, { 0x10, 0x0b, 0x0d }, { 0x10, 0x0b, 0x0c }, 405 { 0x10, 0x0b, 0x0b }, { 0x10, 0x0c, 0x0b }, { 0x10, 0x0d, 0x0b }, { 0x10, 0x0f, 0x0b }, 406 { 0x10, 0x10, 0x0b }, { 0x0f, 0x10, 0x0b }, { 0x0d, 0x10, 0x0b }, { 0x0c, 0x10, 0x0b }, 407 { 0x0b, 0x10, 0x0b }, { 0x0b, 0x10, 0x0c }, { 0x0b, 0x10, 0x0d }, { 0x0b, 0x10, 0x0f }, 408 { 0x0b, 0x10, 0x10 }, { 0x0b, 0x0f, 0x10 }, { 0x0b, 0x0d, 0x10 }, { 0x0b, 0x0c, 0x10 }, 409 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 410 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 411}; 412 413/* extern. function */ 414extern void vASTOpenKey(ScrnInfoPtr pScrn); 415extern Bool bASTRegInit(ScrnInfoPtr pScrn); 416extern void vAST1000DisplayOn(ASTRecPtr pAST); 417extern void vAST1000DisplayOff(ASTRecPtr pAST); 418 419extern Bool bEnable2D(ScrnInfoPtr pScrn, ASTRecPtr pAST); 420extern void vDisable2D(ScrnInfoPtr pScrn, ASTRecPtr pAST); 421 422extern Bool bInitHWC(ScrnInfoPtr pScrn, ASTRecPtr pAST); 423 424/* Prototype type declaration*/ 425Bool ASTSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode); 426Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 427void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 428void vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 429void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 430void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 431void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 432void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 433Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 434BOOL bSetAST1180CRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 435BOOL bSetAST1180OffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 436BOOL bSetAST1180DCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 437BOOL bSetAST1180ExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 438void vInitChontelReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 439 440Bool 441ASTSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode) 442{ 443 ASTRecPtr pAST; 444 VBIOS_MODE_INFO vgamodeinfo; 445 446 pAST = ASTPTR(pScrn); 447 448 /* pre set mode */ 449 bGetAST1000VGAModeInfo(pScrn, mode, &vgamodeinfo); 450 451 /* set mode */ 452 if (pAST->jChipType == AST1180) 453 { 454 bInitAST1180(pScrn); 455 456 bSetAST1180CRTCReg(pScrn, mode, &vgamodeinfo); 457 bSetAST1180OffsetReg(pScrn, mode, &vgamodeinfo); 458 bSetAST1180DCLKReg(pScrn, mode, &vgamodeinfo); 459 bSetAST1180ExtReg(pScrn, mode, &vgamodeinfo); 460 461 vInitChontelReg(pScrn, mode, &vgamodeinfo); 462 } 463 else 464 { 465 vASTOpenKey(pScrn); 466 bASTRegInit(pScrn); 467 468 vSetStdReg(pScrn, mode, &vgamodeinfo); 469 vSetCRTCReg(pScrn, mode, &vgamodeinfo); 470 vSetOffsetReg(pScrn, mode, &vgamodeinfo); 471 vSetDCLKReg(pScrn, mode, &vgamodeinfo); 472 vSetExtReg(pScrn, mode, &vgamodeinfo); 473 vSetSyncReg(pScrn, mode, &vgamodeinfo); 474 bSetDACReg(pScrn, mode, &vgamodeinfo); 475 } 476 477 /* post set mode */ 478#ifdef Accel_2D 479 if (!pAST->noAccel) { 480 if (!bEnable2D(pScrn, pAST)) { 481 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Enable 2D failed\n"); 482 pAST->noAccel = TRUE; 483 } 484 } 485#endif 486#ifdef HWC 487 if (!pAST->noHWC) { 488 if (!bInitHWC(pScrn, pAST)) { 489 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Init HWC failed\n"); 490 pAST->noHWC = TRUE; 491 } 492 } 493#endif 494 vAST1000DisplayOn(pAST); 495 496 return (TRUE); 497} 498 499 500Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 501{ 502 ASTRecPtr pAST; 503 ULONG ulModeID, ulColorIndex, ulRefreshRate, ulRefreshRateIndex = 0; 504 ULONG ulHBorder, ulVBorder; 505 506 pAST = ASTPTR(pScrn); 507 508 switch (pScrn->bitsPerPixel) 509 { 510 case 8: 511 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[VGAModeIndex]; 512 ulColorIndex = VGAModeIndex-1; 513 break; 514 case 16: 515 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[HiCModeIndex]; 516 ulColorIndex = HiCModeIndex; 517 break; 518 case 24: 519 case 32: 520 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[TrueCModeIndex]; 521 ulColorIndex = TrueCModeIndex; 522 break; 523 default: 524 return (FALSE); 525 } 526 527 switch (mode->CrtcHDisplay) 528 { 529 case 640: 530 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res640x480Table[ulRefreshRateIndex]; 531 break; 532 case 800: 533 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res800x600Table[ulRefreshRateIndex]; 534 break; 535 case 1024: 536 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1024x768Table[ulRefreshRateIndex]; 537 break; 538 case 1280: 539 if (mode->CrtcVDisplay == 800) 540 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x800Table[ulRefreshRateIndex]; 541 else 542 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x1024Table[ulRefreshRateIndex]; 543 break; 544 case 1360: 545 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1360x768Table[ulRefreshRateIndex]; 546 break; 547 case 1440: 548 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1440x900Table[ulRefreshRateIndex]; 549 break; 550 case 1600: 551 if (mode->CrtcVDisplay == 900) 552 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1600x900Table[ulRefreshRateIndex]; 553 else 554 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1600x1200Table[ulRefreshRateIndex]; 555 break; 556 case 1680: 557 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1680x1050Table[ulRefreshRateIndex]; 558 break; 559 case 1920: 560 if (mode->CrtcVDisplay == 1080) 561 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1080Table[ulRefreshRateIndex]; 562 else 563 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1200Table[ulRefreshRateIndex]; 564 break; 565 default: 566 return (FALSE); 567 } 568 569 /* Get Proper Mode Index */ 570 ulRefreshRate = (mode->Clock * 1000) / (mode->HTotal * mode->VTotal); 571 572 while (pVGAModeInfo->pEnhTableEntry->ulRefreshRate < ulRefreshRate) 573 { 574 pVGAModeInfo->pEnhTableEntry++; 575 if ((pVGAModeInfo->pEnhTableEntry->ulRefreshRate > ulRefreshRate) || 576 (pVGAModeInfo->pEnhTableEntry->ulRefreshRate == 0xFF)) 577 { 578 pVGAModeInfo->pEnhTableEntry--; 579 break; 580 } 581 } 582 583 /* parsing for wide scrren reduced blank mode */ 584 if (pVGAModeInfo->pEnhTableEntry->Flags & WideScreenMode) 585 { 586 if ((mode->Flags & V_PVSYNC) && (mode->Flags & V_NHSYNC)) /* CVT */ 587 pVGAModeInfo->pEnhTableEntry++; 588 } 589 590 /* Update mode CRTC info */ 591 ulHBorder = (pVGAModeInfo->pEnhTableEntry->Flags & HBorder) ? 8:0; 592 ulVBorder = (pVGAModeInfo->pEnhTableEntry->Flags & VBorder) ? 8:0; 593 594 mode->CrtcHTotal = (int) pVGAModeInfo->pEnhTableEntry->HT; 595 mode->CrtcHBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder); 596 mode->CrtcHBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->HT - ulHBorder); 597 mode->CrtcHSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 598 + pVGAModeInfo->pEnhTableEntry->HFP); 599 mode->CrtcHSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 600 + pVGAModeInfo->pEnhTableEntry->HFP 601 + pVGAModeInfo->pEnhTableEntry->HSYNC); 602 603 mode->CrtcVTotal = (int) pVGAModeInfo->pEnhTableEntry->VT; 604 mode->CrtcVBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder); 605 mode->CrtcVBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->VT - ulVBorder); 606 mode->CrtcVSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 607 + pVGAModeInfo->pEnhTableEntry->VFP); 608 mode->CrtcVSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 609 + pVGAModeInfo->pEnhTableEntry->VFP 610 + pVGAModeInfo->pEnhTableEntry->VSYNC); 611 612 /* Write mode info to scratch */ 613 ulRefreshRateIndex = pVGAModeInfo->pEnhTableEntry->ulRefreshRateIndex; 614 ulModeID = pVGAModeInfo->pEnhTableEntry->ulModeID; 615 616 if (pAST->jChipType == AST1180) 617 { 618 /* TODO */ 619 } 620 else 621 { 622 SetIndexReg(CRTC_PORT, 0x8C, (UCHAR) ((ulColorIndex & 0x0F) << 4)); 623 SetIndexReg(CRTC_PORT, 0x8D, (UCHAR) (ulRefreshRateIndex & 0xFF)); 624 SetIndexReg(CRTC_PORT, 0x8E, (UCHAR) (ulModeID & 0xFF)); 625 626 /* NewModeInfo */ 627 SetIndexReg(CRTC_PORT, 0x91, 0x00); /* clear signature */ 628 if (pVGAModeInfo->pEnhTableEntry->Flags & NewModeInfo) 629 { 630 SetIndexReg(CRTC_PORT, 0x91, 0xA8); /* signature */ 631 SetIndexReg(CRTC_PORT, 0x92, (UCHAR) (pScrn->bitsPerPixel) ); 632 SetIndexReg(CRTC_PORT, 0x93, (UCHAR) (mode->Clock / 1000) ); 633 SetIndexReg(CRTC_PORT, 0x94, (UCHAR) (mode->CrtcHDisplay) ); 634 SetIndexReg(CRTC_PORT, 0x95, (UCHAR) (mode->CrtcHDisplay >> 8) ); /* color depth */ 635 SetIndexReg(CRTC_PORT, 0x96, (UCHAR) (mode->CrtcVDisplay) ); 636 SetIndexReg(CRTC_PORT, 0x97, (UCHAR) (mode->CrtcVDisplay >> 8) ); /* color depth */ 637 } 638 } 639 640 return (TRUE); 641} 642 643void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 644{ 645 646 PVBIOS_STDTABLE_STRUCT pStdModePtr; 647 ASTRecPtr pAST; 648 ULONG i; 649 UCHAR jReg; 650 651 pStdModePtr = pVGAModeInfo->pStdTableEntry; 652 pAST = ASTPTR(pScrn); 653 654 /* Set Misc */ 655 jReg = pStdModePtr->MISC; 656 SetReg(MISC_PORT_WRITE,jReg); 657 658 /* Set Seq */ 659 SetIndexReg(SEQ_PORT,0x00, 0x03); 660 for (i=0; i<4; i++) 661 { 662 jReg = pStdModePtr->SEQ[i]; 663 if (!i) (jReg |= 0x20); /* display off */ 664 SetIndexReg(SEQ_PORT,(UCHAR) (i+1), jReg); 665 } 666 667 /* Set CRTC */ 668 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 669 for (i=0; i<25; i++) 670 { 671 jReg = pStdModePtr->CRTC[i]; 672 SetIndexReg(CRTC_PORT,(UCHAR) i, jReg); 673 } 674 675 /* Set AR */ 676 jReg = GetReg(INPUT_STATUS1_READ); 677 for (i=0; i<20; i++) 678 { 679 jReg = pStdModePtr->AR[i]; 680 SetReg(AR_PORT_WRITE, (UCHAR) i); 681 SetReg(AR_PORT_WRITE, jReg); 682 } 683 SetReg(AR_PORT_WRITE, 0x14); 684 SetReg(AR_PORT_WRITE, 0x00); 685 686 jReg = GetReg(INPUT_STATUS1_READ); 687 SetReg (AR_PORT_WRITE, 0x20); /* set POS */ 688 689 /* Set GR */ 690 for (i=0; i<9; i++) 691 { 692 jReg = pStdModePtr->GR[i]; 693 SetIndexReg(GR_PORT,(UCHAR) i, jReg); 694 695 } 696 697 698} 699 700void 701vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 702{ 703 ASTRecPtr pAST; 704 USHORT usTemp; 705 UCHAR jReg05, jReg07, jReg09, jRegAC, jRegAD, jRegAE; 706 707 pAST = ASTPTR(pScrn); 708 jReg05 = jReg07 = jReg09 = jRegAC = jRegAD = jRegAE = 0; 709 710 /* unlock CRTC */ 711 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 712 713 /* Horizontal Timing Programming */ 714 usTemp = (mode->CrtcHTotal >> 3) - 5; 715 if (usTemp & 0x100) jRegAC |= 0x01; /* HT D[8] */ 716 SetIndexRegMask(CRTC_PORT,0x00, 0x00, (UCHAR) usTemp); 717 usTemp = (mode->CrtcHDisplay >> 3) - 1; 718 if (usTemp & 0x100) jRegAC |= 0x04; /* HDE D[8] */ 719 SetIndexRegMask(CRTC_PORT,0x01, 0x00, (UCHAR) usTemp); 720 usTemp = (mode->CrtcHBlankStart >> 3) - 1; 721 if (usTemp & 0x100) jRegAC |= 0x10; /* HBS D[8] */ 722 SetIndexRegMask(CRTC_PORT,0x02, 0x00, (UCHAR) usTemp); 723 usTemp = ((mode->CrtcHBlankEnd >> 3) - 1) & 0x7F; 724 if (usTemp & 0x20) jReg05 |= 0x80; /* HBE D[5] */ 725 if (usTemp & 0x40) jRegAD |= 0x01; /* HBE D[6] */ 726 SetIndexRegMask(CRTC_PORT,0x03, 0xE0, (UCHAR) (usTemp & 0x1F)); 727 usTemp = (mode->CrtcHSyncStart >> 3 ) - 1; 728 if (usTemp & 0x100) jRegAC |= 0x40; /* HRS D[5] */ 729 SetIndexRegMask(CRTC_PORT,0x04, 0x00, (UCHAR) (usTemp)); 730 usTemp = ((mode->CrtcHSyncEnd >> 3 ) - 1) & 0x3F; 731 if (usTemp & 0x20) jRegAD |= 0x04; /* HRE D[5] */ 732 SetIndexRegMask(CRTC_PORT,0x05, 0x60, (UCHAR) ((usTemp & 0x1F) | jReg05)); 733 734 SetIndexRegMask(CRTC_PORT,0xAC, 0x00, (UCHAR) jRegAC); 735 SetIndexRegMask(CRTC_PORT,0xAD, 0x00, (UCHAR) jRegAD); 736 737 /* Vetical Timing Programming */ 738 usTemp = (mode->CrtcVTotal) - 2; 739 if (usTemp & 0x100) jReg07 |= 0x01; /* VT D[8] */ 740 if (usTemp & 0x200) jReg07 |= 0x20; 741 if (usTemp & 0x400) jRegAE |= 0x01; /* VT D[10] */ 742 SetIndexRegMask(CRTC_PORT,0x06, 0x00, (UCHAR) usTemp); 743 usTemp = (mode->CrtcVSyncStart) - 1; 744 if (usTemp & 0x100) jReg07 |= 0x04; /* VRS D[8] */ 745 if (usTemp & 0x200) jReg07 |= 0x80; /* VRS D[9] */ 746 if (usTemp & 0x400) jRegAE |= 0x08; /* VRS D[10] */ 747 SetIndexRegMask(CRTC_PORT,0x10, 0x00, (UCHAR) usTemp); 748 usTemp = ((mode->CrtcVSyncEnd) - 1) & 0x3F; 749 if (usTemp & 0x10) jRegAE |= 0x20; /* VRE D[4] */ 750 if (usTemp & 0x20) jRegAE |= 0x40; /* VRE D[5] */ 751 SetIndexRegMask(CRTC_PORT,0x11, 0x70, (UCHAR) (usTemp & 0x0F)); 752 usTemp = (mode->CrtcVDisplay) - 1; 753 if (usTemp & 0x100) jReg07 |= 0x02; /* VDE D[8] */ 754 if (usTemp & 0x200) jReg07 |= 0x40; /* VDE D[9] */ 755 if (usTemp & 0x400) jRegAE |= 0x02; /* VDE D[10] */ 756 SetIndexRegMask(CRTC_PORT,0x12, 0x00, (UCHAR) usTemp); 757 usTemp = (mode->CrtcVBlankStart) - 1; 758 if (usTemp & 0x100) jReg07 |= 0x08; /* VBS D[8] */ 759 if (usTemp & 0x200) jReg09 |= 0x20; /* VBS D[9] */ 760 if (usTemp & 0x400) jRegAE |= 0x04; /* VBS D[10] */ 761 SetIndexRegMask(CRTC_PORT,0x15, 0x00, (UCHAR) usTemp); 762 usTemp = (mode->CrtcVBlankEnd) - 1 ; 763 if (usTemp & 0x100) jRegAE |= 0x10; /* VBE D[8] */ 764 SetIndexRegMask(CRTC_PORT,0x16, 0x00, (UCHAR) usTemp); 765 766 SetIndexRegMask(CRTC_PORT,0x07, 0x00, (UCHAR) jReg07); 767 SetIndexRegMask(CRTC_PORT,0x09, 0xDF, (UCHAR) jReg09); 768 SetIndexRegMask(CRTC_PORT,0xAE, 0x00, (UCHAR) (jRegAE | 0x80)); /* disable line compare */ 769 770 /* lock CRTC */ 771 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x80); 772 773} 774 775void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 776{ 777 ASTRecPtr pAST; 778 USHORT usOffset; 779 780 pAST = ASTPTR(pScrn); 781 782 usOffset = pAST->VideoModeInfo.ScreenPitch >> 3; /* Unit: char */ 783 784 SetIndexReg(CRTC_PORT,0x13, (UCHAR) (usOffset & 0xFF)); 785 SetIndexReg(CRTC_PORT,0xB0, (UCHAR) ((usOffset >> 8) & 0x3F)); 786 787} 788 789void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 790{ 791 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 792 PVBIOS_DCLK_INFO pDCLKPtr; 793 ASTRecPtr pAST; 794 795 pAST = ASTPTR(pScrn); 796 797 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 798 if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) || (pAST->jChipType == AST2300)) 799 pDCLKPtr = &DCLKTable_AST2100[pEnhModePtr->DCLKIndex]; 800 else 801 pDCLKPtr = &DCLKTable[pEnhModePtr->DCLKIndex]; 802 803 SetIndexRegMask(CRTC_PORT,0xC0, 0x00, pDCLKPtr->Param1); 804 SetIndexRegMask(CRTC_PORT,0xC1, 0x00, pDCLKPtr->Param2); 805 SetIndexRegMask(CRTC_PORT,0xBB, 0x0F, (pDCLKPtr->Param3 & 0x80) | ((pDCLKPtr->Param3 & 0x03) << 4) ); 806 807} 808 809 810void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 811{ 812 813 ASTRecPtr pAST; 814 UCHAR jRegA0, jRegA3, jRegA8; 815 816 pAST = ASTPTR(pScrn); 817 818 jRegA0=jRegA3=jRegA8=0; 819 /* Mode Type Setting */ 820 switch (pScrn->bitsPerPixel) { 821 case 8: 822 jRegA0 = 0x70; 823 jRegA3 = 0x01; 824 jRegA8 = 0x00; 825 break; 826 case 15: 827 case 16: 828 jRegA0 = 0x70; 829 jRegA3 = 0x04; 830 jRegA8 = 0x02; 831 break; 832 case 32: 833 jRegA0 = 0x70; 834 jRegA3 = 0x08; 835 jRegA8 = 0x02; 836 break; 837 } 838 SetIndexRegMask(CRTC_PORT,0xA0, 0x8F, (UCHAR) jRegA0); 839 SetIndexRegMask(CRTC_PORT,0xA3, 0xF0, (UCHAR) jRegA3); 840 SetIndexRegMask(CRTC_PORT,0xA8, 0xFD, (UCHAR) jRegA8); 841 842#if defined(__sparc__) 843 UCHAR jRegA2 = 0x80; 844 if ((pScrn->bitsPerPixel == 15) || (pScrn->bitsPerPixel == 16) ) 845 jRegA2 |= 0x40; 846 SetIndexRegMask(CRTC_PORT,0xA2, 0x3F, (UCHAR) jRegA2); 847#endif 848 849 /* Set Threshold */ 850 if (pAST->jChipType == AST2300) 851 { 852 SetIndexReg(CRTC_PORT,0xA7, 0x78); 853 SetIndexReg(CRTC_PORT,0xA6, 0x60); 854 } 855 else if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) ) 856 { 857 SetIndexReg(CRTC_PORT,0xA7, 0x3F); 858 SetIndexReg(CRTC_PORT,0xA6, 0x2F); 859 } 860 else 861 { 862 SetIndexReg(CRTC_PORT,0xA7, 0x2F); 863 SetIndexReg(CRTC_PORT,0xA6, 0x1F); 864 } 865 866} 867 868void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 869{ 870 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 871 ASTRecPtr pAST; 872 UCHAR jReg; 873 874 pAST = ASTPTR(pScrn); 875 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 876 877 jReg = GetReg(MISC_PORT_READ); 878 jReg |= (UCHAR) (pEnhModePtr->Flags & SyncNN); 879 SetReg(MISC_PORT_WRITE,jReg); 880 881} 882 883Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 884{ 885 PVBIOS_DAC_INFO pDACPtr; 886 ASTRecPtr pAST; 887 ULONG i, ulDACNumber; 888 UCHAR DACR, DACG, DACB; 889 890 pAST = ASTPTR(pScrn); 891 892 switch (pScrn->bitsPerPixel) 893 { 894 case 8: 895 ulDACNumber = DAC_NUM_VGA; 896 pDACPtr = (PVBIOS_DAC_INFO) &DAC_VGA[0]; 897 break; 898 default: 899 return (FALSE); 900 } 901 902 for (i=0; i<ulDACNumber; i++) 903 { 904 DACR = pDACPtr->DACR; 905 DACG = pDACPtr->DACG; 906 DACB = pDACPtr->DACB; 907 908 VGA_LOAD_PALETTE_INDEX (i, DACR, DACG, DACB); 909 910 pDACPtr++; 911 } 912 913 return (TRUE); 914 915} 916 917ULONG AST1180DCLKTable [] = { 918 0x0008676b, /* 00: VCLK25_175 */ 919 0x00086342, /* 01: VCLK28_322 */ 920 0x00086568, /* 02: VCLK31_5 */ 921 0x00082118, /* 03: VCLK36 */ 922 0x0008232e, /* 04: VCLK40 */ 923 0x000c256d, /* 05: VCLK49_5 */ 924 0x00082016, /* 06: VCLK50 */ 925 0x000c0010, /* 07: VCLK56_25 */ 926 0x000c0332, /* 08: VCLK65 */ 927 0x00080010, /* 09: VCLK75 */ 928 0x000c033d, /* 0A: VCLK78_75 */ 929 0x000c0568, /* 0B: VCLK94_5 */ 930 0x00040118, /* 0C: VCLK108 */ 931 0x00040334, /* 0D: VCLK135 */ 932 0x0004033d, /* 0E: VCLK157_5 */ 933 0x00040018, /* 0F: VCLK162 */ 934 0x00040123, /* 10: VCLK154 */ 935 0x000c0669, /* 11: VCLK83_5 */ 936 0x0004074b, /* 12: VCLK106_5 */ 937 0x0004022d, /* 13: VCLK146_25 */ 938 0x00040769, /* 14: VCLK148_5 */ 939}; 940 941BOOL bSetAST1180CRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 942{ 943 ASTRecPtr pAST = ASTPTR(pScrn); 944 945 ULONG HTIndex, HRIndex, VTIndex, VRIndex; 946 ULONG HT, HDE, HBS, HBE, HRS, HRE; 947 ULONG VT, VDE, VBS, VBE, VRS, VRE; 948 ULONG HT2, HDE2, HRS2, HRE2; 949 ULONG VT2, VDE2, VRS2, VRE2; 950 951 /* Reg. Index Select */ 952 { 953 HTIndex = AST1180_VGA1_HTREG; 954 HRIndex = AST1180_VGA1_HRREG; 955 VTIndex = AST1180_VGA1_VTREG; 956 VRIndex = AST1180_VGA1_VRREG; 957 } 958 959 /* Get CRTC Info */ 960 HT = mode->CrtcHTotal; 961 HDE= mode->CrtcHDisplay; 962 HBS= mode->CrtcHBlankStart; 963 HBE= mode->CrtcHBlankEnd; 964 HRS= mode->CrtcHSyncStart; 965 HRE= mode->CrtcHSyncEnd; 966 VT = mode->CrtcVTotal; 967 VDE= mode->CrtcVDisplay; 968 VBS= mode->CrtcVBlankStart; 969 VBE= mode->CrtcVBlankEnd; 970 VRS= mode->CrtcVSyncStart; 971 VRE= mode->CrtcVSyncEnd; 972 973 /* Calculate CRTC Reg Setting */ 974 HT2 = HT - 1; 975 HDE2 = HDE - 1; 976 HRS2 = HRS - 1; 977 HRE2 = HRE - 1; 978 VT2 = VT - 1; 979 VDE2 = VDE - 1; 980 VRS2 = VRS - 1; 981 VRE2 = VRE - 1; 982 983 /* Write Reg */ 984 WriteAST1180SOC(AST1180_GFX_BASE + HTIndex, (ULONG)(HDE2 << 16) | (ULONG) (HT2)); 985 WriteAST1180SOC(AST1180_GFX_BASE + HRIndex, (ULONG)(HRE2 << 16) | (ULONG) (HRS2)); 986 WriteAST1180SOC(AST1180_GFX_BASE + VTIndex, (ULONG)(VDE2 << 16) | (ULONG) (VT2)); 987 WriteAST1180SOC(AST1180_GFX_BASE + VRIndex, (ULONG)(VRE2 << 16) | (ULONG) (VRS2)); 988 989 return (TRUE); 990 991} /* bSetAST1180CRTCReg */ 992 993BOOL bSetAST1180OffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 994{ 995 ASTRecPtr pAST = ASTPTR(pScrn); 996 ULONG ulOffset, ulTermalCount; 997 998 ulOffset = pAST->VideoModeInfo.ScreenPitch; 999 ulTermalCount = (pAST->VideoModeInfo.ScreenPitch + 7) >> 3; 1000 1001 /* Write Reg */ 1002 WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_OFFSET, (ULONG) (ulTermalCount << 16) | (ULONG) (ulOffset)); 1003 1004 return (TRUE); 1005 1006} /* bSetAST1180OffsetReg */ 1007 1008BOOL bSetAST1180DCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1009{ 1010 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 1011 ASTRecPtr pAST = ASTPTR(pScrn); 1012 ULONG ulDCLK; 1013 1014 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1015 ulDCLK = AST1180DCLKTable[pEnhModePtr->DCLKIndex]; 1016 if (pEnhModePtr->Flags & HalfDCLK) 1017 ulDCLK |= 0x00400000; /* D[22]: div by 2 */ 1018 WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_PLL, ulDCLK); 1019 1020 return (TRUE); 1021} 1022 1023BOOL bSetAST1180ExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1024{ 1025 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 1026 ASTRecPtr pAST = ASTPTR(pScrn); 1027 1028 ULONG ulCtlRegIndex, ulCtlReg; /* enable display */ 1029 ULONG ulCtlReg2Index, ulCtlReg2 = 0x80; /* single edge */ 1030 ULONG ulThresholdRegIndex ; /* Threshold */ 1031 ULONG ulStartAddressIndex; /* ulStartAddress */ 1032 ULONG ulStartAddress = pAST->ulVRAMBase; 1033 1034 /* Reg. Index Select */ 1035 { 1036 ulCtlRegIndex = AST1180_VGA1_CTRL; 1037 ulCtlReg2Index = AST1180_VGA1_CTRL2; 1038 ulThresholdRegIndex = AST1180_VGA1_THRESHOLD; 1039 ulStartAddressIndex = AST1180_VGA1_STARTADDR; 1040 } 1041 1042 /* Mode Type Setting */ 1043 ulCtlReg = 0x30000000; 1044 { 1045 switch (pScrn->bitsPerPixel) { 1046 case 15: 1047 case 16: 1048 ulCtlReg |= 0x100001; /* RGB565, SCREEN OFF, ENABLE */ 1049 break; 1050 case 32: 1051 ulCtlReg |= 0x100101; /* XRGB8888, SCREEN OFF, ENABLE */ 1052 break; 1053 } 1054 } 1055 1056 /* Polarity */ 1057 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1058 ulCtlReg |= (ULONG) (pEnhModePtr->Flags & SyncNN) << 10; 1059 1060 /* Single/Dual Edge */ 1061 ulCtlReg2 |= 0x40; /* dual-edge */ 1062 1063 /* Write Reg */ 1064 WriteAST1180SOC(AST1180_GFX_BASE + ulStartAddressIndex, ulStartAddress); 1065 WriteAST1180SOC(AST1180_GFX_BASE + ulThresholdRegIndex, ((ULONG) CRT_HIGH_THRESHOLD_VALUE << 8) | (ULONG) (CRT_LOW_THRESHOLD_VALUE)); 1066 WriteAST1180SOC(AST1180_GFX_BASE + ulCtlReg2Index, ulCtlReg2); 1067 WriteAST1180SOC(AST1180_GFX_BASE + ulCtlRegIndex, ulCtlReg); 1068 1069 return (TRUE); 1070 1071} /* bSetAST1180ExtReg */ 1072 1073#define I2C_BASE_AST1180 0x80fcb000 1074#define I2C_DEVICEADDR_AST1180 0x0EC /* slave addr */ 1075 1076void SetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex, UCHAR jData ) 1077{ 1078 ULONG ulData, ulI2CAddr, ulI2CPortBase; 1079 ULONG retry; 1080 1081 { 1082 ulI2CPortBase = I2C_BASE_AST1180 + 0x40 * jChannel; 1083 ulI2CAddr = I2C_DEVICEADDR_AST1180; 1084 } 1085 1086 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x00); 1087 WriteAST1180SOC(ulI2CPortBase + 0x04, 0x77743355); 1088 WriteAST1180SOC(ulI2CPortBase + 0x08, 0x0); 1089 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1090 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x1); 1091 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xAF); 1092 WriteAST1180SOC(ulI2CPortBase + 0x20, ulI2CAddr); 1093 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x03); 1094 retry = 0; 1095 do { 1096 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1097 usleep(10); 1098 if (retry++ > 1000) 1099 goto Exit_SetChrontelReg; 1100 } while (!(ulData & 0x01)); 1101 1102 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1103 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jIndex); 1104 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1105 do { 1106 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1107 } while (!(ulData & 0x01)); 1108 1109 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1110 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jData); 1111 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1112 do { 1113 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1114 } while (!(ulData & 0x01)); 1115 1116 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1117 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xBF); 1118 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x20); 1119 do { 1120 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1121 } while (!(ulData & 0x10)); 1122 1123 ReadAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1124 ulData &= 0xffffffef; 1125 WriteAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1126 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1127 1128Exit_SetChrontelReg: 1129 ; 1130} 1131 1132UCHAR GetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex) 1133{ 1134 ULONG ulData, ulI2CAddr, ulI2CPortBase; 1135 UCHAR jData; 1136 ULONG retry; 1137 1138 { 1139 ulI2CPortBase = I2C_BASE_AST1180 + 0x40 * jChannel; 1140 ulI2CAddr = I2C_DEVICEADDR_AST1180; 1141 } 1142 1143 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x00); 1144 WriteAST1180SOC(ulI2CPortBase + 0x04, 0x77743355); 1145 WriteAST1180SOC(ulI2CPortBase + 0x08, 0x0); 1146 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1147 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x1); 1148 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xAF); 1149 WriteAST1180SOC(ulI2CPortBase + 0x20, ulI2CAddr); 1150 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x03); 1151 retry = 0; 1152 do { 1153 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1154 usleep(10); 1155 if (retry++ > 1000) 1156 return 0; 1157 } while (!(ulData & 0x01)); 1158 1159 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1160 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jIndex); 1161 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1162 do { 1163 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1164 } while (!(ulData & 0x01)); 1165 1166 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1167 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) (ulI2CAddr + 1) ); 1168 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x1B); 1169 do { 1170 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1171 } while (!(ulData & 0x04)); 1172 1173 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1174 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xBF); 1175 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x20); 1176 do { 1177 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1178 } while (!(ulData & 0x10)); 1179 1180 ReadAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1181 ulData &= 0xffffffef; 1182 WriteAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1183 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1184 1185 ReadAST1180SOC(ulI2CPortBase + 0x20, ulData); 1186 jData = (UCHAR) ((ulData & 0xFF00) >> 8); 1187 1188 return (jData); 1189} 1190 1191void vInitChontelReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1192{ 1193 1194 PVBIOS_ENHTABLE_STRUCT pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1195 ASTRecPtr pAST = ASTPTR(pScrn); 1196 ULONG ulDCLK = 65; /* todo */ 1197 UCHAR jReg; 1198 1199 jReg = GetChrontelReg(pAST, 1, 0x4A); /* get vendor id */ 1200 if (jReg == 0x95) 1201 { 1202 jReg = GetChrontelReg(pAST, 1, 0x20); /* DVI/D-Sub */ 1203 if (jReg & 0x20) /* DVI */ 1204 { 1205 1206 /* DVI PLL Filter */ 1207 if (ulDCLK > 65) 1208 { 1209 SetChrontelReg(pAST, 1, 0x33, 0x06); 1210 SetChrontelReg(pAST, 1, 0x34, 0x26); 1211 SetChrontelReg(pAST, 1, 0x36, 0xA0); 1212 } 1213 else 1214 { 1215 SetChrontelReg(pAST, 1, 0x33, 0x08); 1216 SetChrontelReg(pAST, 1, 0x34, 0x16); 1217 SetChrontelReg(pAST, 1, 0x36, 0x60); 1218 } 1219 1220 SetChrontelReg(pAST, 1, 0x49, 0xc0); 1221 } 1222 else /* D-Sub */ 1223 { 1224 1225 SetChrontelReg(pAST, 1, 0x21, 0x09); 1226 SetChrontelReg(pAST, 1, 0x49, 0x00); 1227 SetChrontelReg(pAST, 1, 0x56, 0x00); 1228 } 1229 } 1230 1231} 1232 1233