ast_mode.c revision 83cab373
1/* 2 * Copyright (c) 2005 ASPEED Technology Inc. 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that 7 * copyright notice and this permission notice appear in supporting 8 * documentation, and that the name of the authors not be used in 9 * advertising or publicity pertaining to distribution of the software without 10 * specific, written prior permission. The authors makes no representations 11 * about the suitability of this software for any purpose. It is provided 12 * "as is" without express or implied warranty. 13 * 14 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#ifdef HAVE_CONFIG_H 24#include <config.h> 25#endif 26#include "xf86.h" 27#include "xf86_OSproc.h" 28#include "xf86cmap.h" 29#include "compiler.h" 30#include "mibstore.h" 31#include "vgaHW.h" 32#include "mipointer.h" 33#include "micmap.h" 34 35#include "fb.h" 36#include "regionstr.h" 37#include "xf86xv.h" 38#include <X11/extensions/Xv.h> 39#include "vbe.h" 40 41#include "xf86PciInfo.h" 42#include "xf86Pci.h" 43 44/* framebuffer offscreen manager */ 45#include "xf86fbman.h" 46 47/* include xaa includes */ 48#include "xaa.h" 49#include "xaarop.h" 50 51/* H/W cursor support */ 52#include "xf86Cursor.h" 53 54/* Driver specific headers */ 55#include "ast.h" 56 57VBIOS_STDTABLE_STRUCT StdTable[] = { 58 /* MD_2_3_400 */ 59 { 60 0x67, 61 {0x00,0x03,0x00,0x02}, 62 {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, 63 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, 64 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, 65 0xff}, 66 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 67 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 68 0x0c,0x00,0x0f,0x08}, 69 {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, 70 0xff} 71 }, 72 /* Mode12/ExtEGATable */ 73 { 74 0xe3, 75 {0x01,0x0f,0x00,0x06}, 76 {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, 77 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 78 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, 79 0xff}, 80 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 81 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 82 0x01,0x00,0x0f,0x00}, 83 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 84 0xff} 85 }, 86 /* ExtVGATable */ 87 { 88 0x2f, 89 {0x01,0x0f,0x00,0x0e}, 90 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 91 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 92 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 93 0xff}, 94 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 95 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 96 0x01,0x00,0x00,0x00}, 97 {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, 98 0xff} 99 }, 100 /* ExtHiCTable */ 101 { 102 0x2f, 103 {0x01,0x0f,0x00,0x0e}, 104 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 105 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 106 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 107 0xff}, 108 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 109 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 110 0x01,0x00,0x00,0x00}, 111 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 112 0xff} 113 }, 114 /* ExtTrueCTable */ 115 { 116 0x2f, 117 {0x01,0x0f,0x00,0x0e}, 118 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 119 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 120 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 121 0xff}, 122 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 123 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 124 0x01,0x00,0x00,0x00}, 125 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 126 0xff} 127 }, 128}; 129 130VBIOS_ENHTABLE_STRUCT Res640x480Table[] = { 131 { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ 132 (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, 133 { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ 134 (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, 135 { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ 136 (SyncNN | Charx8Dot) , 75, 3, 0x2E }, 137 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ 138 (SyncNN | Charx8Dot) , 85, 4, 0x2E }, 139 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ 140 (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, 141}; 142 143 144VBIOS_ENHTABLE_STRUCT Res800x600Table[] = { 145 {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ 146 (SyncPP | Charx8Dot), 56, 1, 0x30 }, 147 {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ 148 (SyncPP | Charx8Dot), 60, 2, 0x30 }, 149 {1040, 800, 56, 120, 666, 600, 37, 6, VCLK50, /* 72Hz */ 150 (SyncPP | Charx8Dot), 72, 3, 0x30 }, 151 {1056, 800, 16, 80, 625, 600, 1, 3, VCLK49_5, /* 75Hz */ 152 (SyncPP | Charx8Dot), 75, 4, 0x30 }, 153 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* 85Hz */ 154 (SyncPP | Charx8Dot), 85, 5, 0x30 }, 155 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* end */ 156 (SyncPP | Charx8Dot), 0xFF, 5, 0x30 }, 157}; 158 159 160VBIOS_ENHTABLE_STRUCT Res1024x768Table[] = { 161 {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ 162 (SyncNN | Charx8Dot), 60, 1, 0x31 }, 163 {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ 164 (SyncNN | Charx8Dot), 70, 2, 0x31 }, 165 {1312, 1024, 16, 96, 800, 768, 1, 3, VCLK78_75, /* 75Hz */ 166 (SyncPP | Charx8Dot), 75, 3, 0x31 }, 167 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* 85Hz */ 168 (SyncPP | Charx8Dot), 84, 4, 0x31 }, 169 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* end */ 170 (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, 171}; 172 173VBIOS_ENHTABLE_STRUCT Res1280x1024Table[] = { 174 {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ 175 (SyncPP | Charx8Dot), 60, 1, 0x32 }, 176 {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ 177 (SyncPP | Charx8Dot), 75, 2, 0x32 }, 178 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* 85Hz */ 179 (SyncPP | Charx8Dot), 85, 3, 0x32 }, 180 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* end */ 181 (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, 182}; 183 184VBIOS_ENHTABLE_STRUCT Res1600x1200Table[] = { 185 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ 186 (SyncPP | Charx8Dot), 60, 1, 0x33 }, 187 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ 188 (SyncPP | Charx8Dot), 0xFF, 1, 0x33 }, 189}; 190 191VBIOS_ENHTABLE_STRUCT Res1920x1200Table[] = { 192 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 193 (SyncNP | Charx8Dot), 60, 1, 0x34 }, 194 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 195 (SyncNP | Charx8Dot), 0xFF, 1, 0x34 }, 196}; 197 198VBIOS_DCLK_INFO DCLKTable [] = { 199 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 200 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 201 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 202 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 203 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 204 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 205 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 206 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 207 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 208 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 209 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 210 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 211 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 212 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 213 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 214 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 215 {0x4d, 0x4c, 0x80}, /* 10: VCLK193_25 */ 216}; 217 218VBIOS_DAC_INFO DAC_TEXT[] = { 219 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 220 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 221 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 222 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 223 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 224 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 225 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 226 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 227 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 228 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 229 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 230 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 231 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 232 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 233 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 234 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 235}; 236 237VBIOS_DAC_INFO DAC_EGA[] = { 238 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 239 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 240 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 241 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 242 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 243 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 244 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 245 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 246 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 247 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 248 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 249 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 250 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 251 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 252 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 253 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 254}; 255 256VBIOS_DAC_INFO DAC_VGA[] = { 257 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 258 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x15, 0x00 }, { 0x2a, 0x2a, 0x2a }, 259 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 260 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 261 { 0x00, 0x00, 0x00 }, { 0x05, 0x05, 0x05 }, { 0x08, 0x08, 0x08 }, { 0x0b, 0x0b, 0x0b }, 262 { 0x0e, 0x0e, 0x0e }, { 0x11, 0x11, 0x11 }, { 0x14, 0x14, 0x14 }, { 0x18, 0x18, 0x18 }, 263 { 0x1c, 0x1c, 0x1c }, { 0x20, 0x20, 0x20 }, { 0x24, 0x24, 0x24 }, { 0x28, 0x28, 0x28 }, 264 { 0x2d, 0x2d, 0x2d }, { 0x32, 0x32, 0x32 }, { 0x38, 0x38, 0x38 }, { 0x3f, 0x3f, 0x3f }, 265 { 0x00, 0x00, 0x3f }, { 0x10, 0x00, 0x3f }, { 0x1f, 0x00, 0x3f }, { 0x2f, 0x00, 0x3f }, 266 { 0x3f, 0x00, 0x3f }, { 0x3f, 0x00, 0x2f }, { 0x3f, 0x00, 0x1f }, { 0x3f, 0x00, 0x10 }, 267 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x10, 0x00 }, { 0x3f, 0x1f, 0x00 }, { 0x3f, 0x2f, 0x00 }, 268 { 0x3f, 0x3f, 0x00 }, { 0x2f, 0x3f, 0x00 }, { 0x1f, 0x3f, 0x00 }, { 0x10, 0x3f, 0x00 }, 269 { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x10 }, { 0x00, 0x3f, 0x1f }, { 0x00, 0x3f, 0x2f }, 270 { 0x00, 0x3f, 0x3f }, { 0x00, 0x2f, 0x3f }, { 0x00, 0x1f, 0x3f }, { 0x00, 0x10, 0x3f }, 271 { 0x1f, 0x1f, 0x3f }, { 0x27, 0x1f, 0x3f }, { 0x2f, 0x1f, 0x3f }, { 0x37, 0x1f, 0x3f }, 272 { 0x3f, 0x1f, 0x3f }, { 0x3f, 0x1f, 0x37 }, { 0x3f, 0x1f, 0x2f }, { 0x3f, 0x1f, 0x27 }, 273 { 0x3f, 0x1f, 0x1f }, { 0x3f, 0x27, 0x1f }, { 0x3f, 0x2f, 0x1f }, { 0x3f, 0x37, 0x1f }, 274 { 0x3f, 0x3f, 0x1f }, { 0x37, 0x3f, 0x1f }, { 0x2f, 0x3f, 0x1f }, { 0x27, 0x3f, 0x1f }, 275 { 0x1f, 0x3f, 0x1f }, { 0x1f, 0x3f, 0x27 }, { 0x1f, 0x3f, 0x2f }, { 0x1f, 0x3f, 0x37 }, 276 { 0x1f, 0x3f, 0x3f }, { 0x1f, 0x37, 0x3f }, { 0x1f, 0x2f, 0x3f }, { 0x1f, 0x27, 0x3f }, 277 { 0x2d, 0x2d, 0x3f }, { 0x31, 0x2d, 0x3f }, { 0x36, 0x2d, 0x3f }, { 0x3a, 0x2d, 0x3f }, 278 { 0x3f, 0x2d, 0x3f }, { 0x3f, 0x2d, 0x3a }, { 0x3f, 0x2d, 0x36 }, { 0x3f, 0x2d, 0x31 }, 279 { 0x3f, 0x2d, 0x2d }, { 0x3f, 0x31, 0x2d }, { 0x3f, 0x36, 0x2d }, { 0x3f, 0x3a, 0x2d }, 280 { 0x3f, 0x3f, 0x2d }, { 0x3a, 0x3f, 0x2d }, { 0x36, 0x3f, 0x2d }, { 0x31, 0x3f, 0x2d }, 281 { 0x2d, 0x3f, 0x2d }, { 0x2d, 0x3f, 0x31 }, { 0x2d, 0x3f, 0x36 }, { 0x2d, 0x3f, 0x3a }, 282 { 0x2d, 0x3f, 0x3f }, { 0x2d, 0x3a, 0x3f }, { 0x2d, 0x36, 0x3f }, { 0x2d, 0x31, 0x3f }, 283 { 0x00, 0x00, 0x1c }, { 0x07, 0x00, 0x1c }, { 0x0e, 0x00, 0x1c }, { 0x15, 0x00, 0x1c }, 284 { 0x1c, 0x00, 0x1c }, { 0x1c, 0x00, 0x15 }, { 0x1c, 0x00, 0x0e }, { 0x1c, 0x00, 0x07 }, 285 { 0x1c, 0x00, 0x00 }, { 0x1c, 0x07, 0x00 }, { 0x1c, 0x0e, 0x00 }, { 0x1c, 0x15, 0x00 }, 286 { 0x1c, 0x1c, 0x00 }, { 0x15, 0x1c, 0x00 }, { 0x0e, 0x1c, 0x00 }, { 0x07, 0x1c, 0x00 }, 287 { 0x00, 0x1c, 0x00 }, { 0x00, 0x1c, 0x07 }, { 0x00, 0x1c, 0x0e }, { 0x00, 0x1c, 0x15 }, 288 { 0x00, 0x1c, 0x1c }, { 0x00, 0x15, 0x1c }, { 0x00, 0x0e, 0x1c }, { 0x00, 0x07, 0x1c }, 289 { 0x0e, 0x0e, 0x1c }, { 0x11, 0x0e, 0x1c }, { 0x15, 0x0e, 0x1c }, { 0x18, 0x0e, 0x1c }, 290 { 0x1c, 0x0e, 0x1c }, { 0x1c, 0x0e, 0x18 }, { 0x1c, 0x0e, 0x15 }, { 0x1c, 0x0e, 0x11 }, 291 { 0x1c, 0x0e, 0x0e }, { 0x1c, 0x11, 0x0e }, { 0x1c, 0x15, 0x0e }, { 0x1c, 0x18, 0x0e }, 292 { 0x1c, 0x1c, 0x0e }, { 0x18, 0x1c, 0x0e }, { 0x15, 0x1c, 0x0e }, { 0x11, 0x1c, 0x0e }, 293 { 0x0e, 0x1c, 0x0e }, { 0x0e, 0x1c, 0x11 }, { 0x0e, 0x1c, 0x15 }, { 0x0e, 0x1c, 0x18 }, 294 { 0x0e, 0x1c, 0x1c }, { 0x0e, 0x18, 0x1c }, { 0x0e, 0x15, 0x1c }, { 0x0e, 0x11, 0x1c }, 295 { 0x14, 0x14, 0x1c }, { 0x16, 0x14, 0x1c }, { 0x18, 0x14, 0x1c }, { 0x1a, 0x14, 0x1c }, 296 { 0x1c, 0x14, 0x1c }, { 0x1c, 0x14, 0x1a }, { 0x1c, 0x14, 0x18 }, { 0x1c, 0x14, 0x16 }, 297 { 0x1c, 0x14, 0x14 }, { 0x1c, 0x16, 0x14 }, { 0x1c, 0x18, 0x14 }, { 0x1c, 0x1a, 0x14 }, 298 { 0x1c, 0x1c, 0x14 }, { 0x1a, 0x1c, 0x14 }, { 0x18, 0x1c, 0x14 }, { 0x16, 0x1c, 0x14 }, 299 { 0x14, 0x1c, 0x14 }, { 0x14, 0x1c, 0x16 }, { 0x14, 0x1c, 0x18 }, { 0x14, 0x1c, 0x1a }, 300 { 0x14, 0x1c, 0x1c }, { 0x14, 0x1a, 0x1c }, { 0x14, 0x18, 0x1c }, { 0x14, 0x16, 0x1c }, 301 { 0x00, 0x00, 0x10 }, { 0x04, 0x00, 0x10 }, { 0x08, 0x00, 0x10 }, { 0x0c, 0x00, 0x10 }, 302 { 0x10, 0x00, 0x10 }, { 0x10, 0x00, 0x0c }, { 0x10, 0x00, 0x08 }, { 0x10, 0x00, 0x04 }, 303 { 0x10, 0x00, 0x00 }, { 0x10, 0x04, 0x00 }, { 0x10, 0x08, 0x00 }, { 0x10, 0x0c, 0x00 }, 304 { 0x10, 0x10, 0x00 }, { 0x0c, 0x10, 0x00 }, { 0x08, 0x10, 0x00 }, { 0x04, 0x10, 0x00 }, 305 { 0x00, 0x10, 0x00 }, { 0x00, 0x10, 0x04 }, { 0x00, 0x10, 0x08 }, { 0x00, 0x10, 0x0c }, 306 { 0x00, 0x10, 0x10 }, { 0x00, 0x0c, 0x10 }, { 0x00, 0x08, 0x10 }, { 0x00, 0x04, 0x10 }, 307 { 0x08, 0x08, 0x10 }, { 0x0a, 0x08, 0x10 }, { 0x0c, 0x08, 0x10 }, { 0x0e, 0x08, 0x10 }, 308 { 0x10, 0x08, 0x10 }, { 0x10, 0x08, 0x0e }, { 0x10, 0x08, 0x0c }, { 0x10, 0x08, 0x0a }, 309 { 0x10, 0x08, 0x08 }, { 0x10, 0x0a, 0x08 }, { 0x10, 0x0c, 0x08 }, { 0x10, 0x0e, 0x08 }, 310 { 0x10, 0x10, 0x08 }, { 0x0e, 0x10, 0x08 }, { 0x0c, 0x10, 0x08 }, { 0x0a, 0x10, 0x08 }, 311 { 0x08, 0x10, 0x08 }, { 0x08, 0x10, 0x0a }, { 0x08, 0x10, 0x0c }, { 0x08, 0x10, 0x0e }, 312 { 0x08, 0x10, 0x10 }, { 0x08, 0x0e, 0x10 }, { 0x08, 0x0c, 0x10 }, { 0x08, 0x0a, 0x10 }, 313 { 0x0b, 0x0b, 0x10 }, { 0x0c, 0x0b, 0x10 }, { 0x0d, 0x0b, 0x10 }, { 0x0f, 0x0b, 0x10 }, 314 { 0x10, 0x0b, 0x10 }, { 0x10, 0x0b, 0x0f }, { 0x10, 0x0b, 0x0d }, { 0x10, 0x0b, 0x0c }, 315 { 0x10, 0x0b, 0x0b }, { 0x10, 0x0c, 0x0b }, { 0x10, 0x0d, 0x0b }, { 0x10, 0x0f, 0x0b }, 316 { 0x10, 0x10, 0x0b }, { 0x0f, 0x10, 0x0b }, { 0x0d, 0x10, 0x0b }, { 0x0c, 0x10, 0x0b }, 317 { 0x0b, 0x10, 0x0b }, { 0x0b, 0x10, 0x0c }, { 0x0b, 0x10, 0x0d }, { 0x0b, 0x10, 0x0f }, 318 { 0x0b, 0x10, 0x10 }, { 0x0b, 0x0f, 0x10 }, { 0x0b, 0x0d, 0x10 }, { 0x0b, 0x0c, 0x10 }, 319 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 320 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 321}; 322 323/* extern. function */ 324extern void vASTOpenKey(ScrnInfoPtr pScrn); 325extern Bool bASTRegInit(ScrnInfoPtr pScrn); 326extern void vAST1000DisplayOn(ASTRecPtr pAST); 327extern void vAST1000DisplayOff(ASTRecPtr pAST); 328 329extern Bool bEnable2D(ScrnInfoPtr pScrn, ASTRecPtr pAST); 330extern void vDisable2D(ScrnInfoPtr pScrn, ASTRecPtr pAST); 331 332extern Bool bInitHWC(ScrnInfoPtr pScrn, ASTRecPtr pAST); 333 334/* Prototype type declaration*/ 335Bool ASTSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode); 336Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 337void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 338void vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 339void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 340void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 341void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 342void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 343Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 344 345Bool 346ASTSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode) 347{ 348 ASTRecPtr pAST; 349 VBIOS_MODE_INFO vgamodeinfo; 350 351 pAST = ASTPTR(pScrn); 352 353 vASTOpenKey(pScrn); 354 bASTRegInit(pScrn); 355 356 /* pre set mode */ 357 bGetAST1000VGAModeInfo(pScrn, mode, &vgamodeinfo); 358 359 /* set mode */ 360 vSetStdReg(pScrn, mode, &vgamodeinfo); 361 vSetCRTCReg(pScrn, mode, &vgamodeinfo); 362 vSetOffsetReg(pScrn, mode, &vgamodeinfo); 363 vSetDCLKReg(pScrn, mode, &vgamodeinfo); 364 vSetExtReg(pScrn, mode, &vgamodeinfo); 365 vSetSyncReg(pScrn, mode, &vgamodeinfo); 366 bSetDACReg(pScrn, mode, &vgamodeinfo); 367 368 /* post set mode */ 369#ifdef Accel_2D 370 if (!pAST->noAccel) { 371 if (!bEnable2D(pScrn, pAST)) { 372 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Enable 2D failed\n"); 373 pAST->noAccel = TRUE; 374 } 375 } 376#endif 377#ifdef HWC 378 if (!pAST->noHWC) { 379 if (!bInitHWC(pScrn, pAST)) { 380 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Init HWC failed\n"); 381 pAST->noHWC = TRUE; 382 } 383 } 384#endif 385 vAST1000DisplayOn(pAST); 386 387 return (TRUE); 388} 389 390 391Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 392{ 393 ASTRecPtr pAST; 394 ULONG ulModeID, ulColorIndex, ulRefreshRate, ulRefreshRateIndex = 0; 395 ULONG ulHBorder, ulVBorder; 396 397 pAST = ASTPTR(pScrn); 398 399 switch (pScrn->bitsPerPixel) 400 { 401 case 8: 402 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[VGAModeIndex]; 403 ulColorIndex = VGAModeIndex-1; 404 break; 405 case 16: 406 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[HiCModeIndex]; 407 ulColorIndex = HiCModeIndex-1; 408 break; 409 case 24: 410 case 32: 411 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[TrueCModeIndex]; 412 ulColorIndex = TrueCModeIndex-1; 413 break; 414 default: 415 return (FALSE); 416 } 417 418 switch (mode->CrtcHDisplay) 419 { 420 case 640: 421 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res640x480Table[ulRefreshRateIndex]; 422 break; 423 case 800: 424 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res800x600Table[ulRefreshRateIndex]; 425 break; 426 case 1024: 427 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1024x768Table[ulRefreshRateIndex]; 428 break; 429 case 1280: 430 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x1024Table[ulRefreshRateIndex]; 431 break; 432 case 1600: 433 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1600x1200Table[ulRefreshRateIndex]; 434 break; 435 case 1920: 436 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1200Table[ulRefreshRateIndex]; 437 break; default: 438 return (FALSE); 439 } 440 441 /* Get Proper Mode Index */ 442 ulRefreshRate = (mode->Clock * 1000) / (mode->HTotal * mode->VTotal); 443 444 while (pVGAModeInfo->pEnhTableEntry->ulRefreshRate < ulRefreshRate) 445 { 446 pVGAModeInfo->pEnhTableEntry++; 447 if ((pVGAModeInfo->pEnhTableEntry->ulRefreshRate > ulRefreshRate) || 448 (pVGAModeInfo->pEnhTableEntry->ulRefreshRate == 0xFF)) 449 { 450 pVGAModeInfo->pEnhTableEntry--; 451 break; 452 } 453 } 454 455 /* Update mode CRTC info */ 456 ulHBorder = (pVGAModeInfo->pEnhTableEntry->Flags & HBorder) ? 1:0; 457 ulVBorder = (pVGAModeInfo->pEnhTableEntry->Flags & VBorder) ? 1:0; 458 459 mode->CrtcHTotal = (int) pVGAModeInfo->pEnhTableEntry->HT; 460 mode->CrtcHBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder); 461 mode->CrtcHBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->HT - ulHBorder); 462 mode->CrtcHSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 463 + pVGAModeInfo->pEnhTableEntry->HFP); 464 mode->CrtcHSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 465 + pVGAModeInfo->pEnhTableEntry->HFP 466 + pVGAModeInfo->pEnhTableEntry->HSYNC); 467 468 mode->CrtcVTotal = (int) pVGAModeInfo->pEnhTableEntry->VT; 469 mode->CrtcVBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder); 470 mode->CrtcVBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->VT - ulVBorder); 471 mode->CrtcVSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 472 + pVGAModeInfo->pEnhTableEntry->VFP); 473 mode->CrtcVSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 474 + pVGAModeInfo->pEnhTableEntry->VFP 475 + pVGAModeInfo->pEnhTableEntry->VSYNC); 476 477 /* Write mode info to scratch */ 478 ulRefreshRateIndex = pVGAModeInfo->pEnhTableEntry->ulRefreshRateIndex; 479 ulModeID = pVGAModeInfo->pEnhTableEntry->ulModeID; 480 481 SetIndexReg(CRTC_PORT, 0x8C, (UCHAR) ((ulColorIndex & 0x0F) << 4)); 482 SetIndexReg(CRTC_PORT, 0x8D, (UCHAR) (ulRefreshRateIndex & 0xFF)); 483 SetIndexReg(CRTC_PORT, 0x8E, (UCHAR) (ulModeID & 0xFF)); 484 485 return (TRUE); 486} 487 488void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 489{ 490 491 PVBIOS_STDTABLE_STRUCT pStdModePtr; 492 ASTRecPtr pAST; 493 ULONG i; 494 UCHAR jReg; 495 496 pStdModePtr = pVGAModeInfo->pStdTableEntry; 497 pAST = ASTPTR(pScrn); 498 499 /* Set Misc */ 500 jReg = pStdModePtr->MISC; 501 SetReg(MISC_PORT_WRITE,jReg); 502 503 /* Set Seq */ 504 SetIndexReg(SEQ_PORT,0x00, 0x03); 505 for (i=0; i<4; i++) 506 { 507 jReg = pStdModePtr->SEQ[i]; 508 if (!i) (jReg |= 0x20); /* display off */ 509 SetIndexReg(SEQ_PORT,(UCHAR) (i+1), jReg); 510 } 511 512 /* Set CRTC */ 513 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 514 for (i=0; i<25; i++) 515 { 516 jReg = pStdModePtr->CRTC[i]; 517 SetIndexReg(CRTC_PORT,(UCHAR) i, jReg); 518 } 519 520 /* Set AR */ 521 jReg = GetReg(INPUT_STATUS1_READ); 522 for (i=0; i<20; i++) 523 { 524 jReg = pStdModePtr->AR[i]; 525 SetReg(AR_PORT_WRITE, (UCHAR) i); 526 SetReg(AR_PORT_WRITE, jReg); 527 } 528 SetReg(AR_PORT_WRITE, 0x14); 529 SetReg(AR_PORT_WRITE, 0x00); 530 531 jReg = GetReg(INPUT_STATUS1_READ); 532 SetReg (AR_PORT_WRITE, 0x20); /* set POS */ 533 534 /* Set GR */ 535 for (i=0; i<9; i++) 536 { 537 jReg = pStdModePtr->GR[i]; 538 SetIndexReg(GR_PORT,(UCHAR) i, jReg); 539 540 } 541 542 543} 544 545void 546vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 547{ 548 ASTRecPtr pAST; 549 USHORT usTemp; 550 UCHAR jReg05, jReg07, jReg09, jRegAC, jRegAD, jRegAE; 551 552 pAST = ASTPTR(pScrn); 553 jReg05 = jReg07 = jReg09 = jRegAC = jRegAD = jRegAE = 0; 554 555 /* unlock CRTC */ 556 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 557 558 /* Horizontal Timing Programming */ 559 usTemp = (mode->CrtcHTotal >> 3) - 5; 560 if (usTemp & 0x100) jRegAC |= 0x01; /* HT D[8] */ 561 SetIndexRegMask(CRTC_PORT,0x00, 0x00, (UCHAR) usTemp); 562 usTemp = (mode->CrtcHDisplay >> 3) - 1; 563 if (usTemp & 0x100) jRegAC |= 0x04; /* HDE D[8] */ 564 SetIndexRegMask(CRTC_PORT,0x01, 0x00, (UCHAR) usTemp); 565 usTemp = (mode->CrtcHBlankStart >> 3) - 1; 566 if (usTemp & 0x100) jRegAC |= 0x10; /* HBS D[8] */ 567 SetIndexRegMask(CRTC_PORT,0x02, 0x00, (UCHAR) usTemp); 568 usTemp = ((mode->CrtcHBlankEnd >> 3) - 1) & 0x7F; 569 if (usTemp & 0x20) jReg05 |= 0x80; /* HBE D[5] */ 570 if (usTemp & 0x40) jRegAD |= 0x01; /* HBE D[6] */ 571 SetIndexRegMask(CRTC_PORT,0x03, 0xE0, (UCHAR) (usTemp & 0x1F)); 572 usTemp = (mode->CrtcHSyncStart >> 3 ) + 2; 573 if (usTemp & 0x100) jRegAC |= 0x40; /* HRS D[5] */ 574 SetIndexRegMask(CRTC_PORT,0x04, 0x00, (UCHAR) (usTemp)); 575 usTemp = ((mode->CrtcHSyncEnd >> 3 ) + 2) & 0x3F; 576 if (usTemp & 0x20) jRegAD |= 0x04; /* HRE D[5] */ 577 SetIndexRegMask(CRTC_PORT,0x05, 0x60, (UCHAR) ((usTemp & 0x1F) | jReg05)); 578 579 SetIndexRegMask(CRTC_PORT,0xAC, 0x00, (UCHAR) jRegAC); 580 SetIndexRegMask(CRTC_PORT,0xAD, 0x00, (UCHAR) jRegAD); 581 582 /* Vetical Timing Programming */ 583 usTemp = (mode->CrtcVTotal) - 2; 584 if (usTemp & 0x100) jReg07 |= 0x01; /* VT D[8] */ 585 if (usTemp & 0x200) jReg07 |= 0x20; 586 if (usTemp & 0x400) jRegAE |= 0x01; /* VT D[10] */ 587 SetIndexRegMask(CRTC_PORT,0x06, 0x00, (UCHAR) usTemp); 588 usTemp = (mode->CrtcVSyncStart) - 1; 589 if (usTemp & 0x100) jReg07 |= 0x04; /* VRS D[8] */ 590 if (usTemp & 0x200) jReg07 |= 0x80; /* VRS D[9] */ 591 if (usTemp & 0x400) jRegAE |= 0x08; /* VRS D[10] */ 592 SetIndexRegMask(CRTC_PORT,0x10, 0x00, (UCHAR) usTemp); 593 usTemp = ((mode->CrtcVSyncEnd) - 1) & 0x3F; 594 if (usTemp & 0x10) jRegAE |= 0x20; /* VRE D[4] */ 595 if (usTemp & 0x20) jRegAE |= 0x40; /* VRE D[5] */ 596 SetIndexRegMask(CRTC_PORT,0x11, 0x70, (UCHAR) (usTemp & 0x0F)); 597 usTemp = (mode->CrtcVDisplay) - 1; 598 if (usTemp & 0x100) jReg07 |= 0x02; /* VDE D[8] */ 599 if (usTemp & 0x200) jReg07 |= 0x40; /* VDE D[9] */ 600 if (usTemp & 0x400) jRegAE |= 0x02; /* VDE D[10] */ 601 SetIndexRegMask(CRTC_PORT,0x12, 0x00, (UCHAR) usTemp); 602 usTemp = (mode->CrtcVBlankStart) - 1; 603 if (usTemp & 0x100) jReg07 |= 0x08; /* VBS D[8] */ 604 if (usTemp & 0x200) jReg09 |= 0x20; /* VBS D[9] */ 605 if (usTemp & 0x400) jRegAE |= 0x04; /* VBS D[10] */ 606 SetIndexRegMask(CRTC_PORT,0x15, 0x00, (UCHAR) usTemp); 607 usTemp = (mode->CrtcVBlankEnd) - 1 ; 608 if (usTemp & 0x100) jRegAE |= 0x10; /* VBE D[8] */ 609 SetIndexRegMask(CRTC_PORT,0x16, 0x00, (UCHAR) usTemp); 610 611 SetIndexRegMask(CRTC_PORT,0x07, 0x00, (UCHAR) jReg07); 612 SetIndexRegMask(CRTC_PORT,0x09, 0xDF, (UCHAR) jReg09); 613 SetIndexRegMask(CRTC_PORT,0xAE, 0x00, (UCHAR) (jRegAE | 0x80)); /* disable line compare */ 614 615 /* lock CRTC */ 616 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x80); 617 618} 619 620void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 621{ 622 ASTRecPtr pAST; 623 USHORT usOffset; 624 625 pAST = ASTPTR(pScrn); 626 627 usOffset = pAST->VideoModeInfo.ScreenPitch >> 3; /* Unit: char */ 628 629 SetIndexReg(CRTC_PORT,0x13, (UCHAR) (usOffset & 0xFF)); 630 SetIndexReg(CRTC_PORT,0xB0, (UCHAR) ((usOffset >> 8) & 0x3F)); 631 632} 633 634void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 635{ 636 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 637 PVBIOS_DCLK_INFO pDCLKPtr; 638 ASTRecPtr pAST; 639 640 pAST = ASTPTR(pScrn); 641 642 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 643 pDCLKPtr = &DCLKTable[pEnhModePtr->DCLKIndex]; 644 645 SetIndexRegMask(CRTC_PORT,0xC0, 0x00, pDCLKPtr->Param1); 646 SetIndexRegMask(CRTC_PORT,0xC1, 0x00, pDCLKPtr->Param2); 647 SetIndexRegMask(CRTC_PORT,0xBB, 0x0F, (pDCLKPtr->Param3 & 0x80) | ((pDCLKPtr->Param3 & 0x03) << 4) ); 648 649} 650 651 652void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 653{ 654 655 ASTRecPtr pAST; 656 UCHAR jRegA0, jRegA3, jRegA8; 657 658 pAST = ASTPTR(pScrn); 659 660 jRegA0=jRegA3=jRegA8=0; 661 /* Mode Type Setting */ 662 switch (pScrn->bitsPerPixel) { 663 case 8: 664 jRegA0 = 0x70; 665 jRegA3 = 0x01; 666 jRegA8 = 0x00; 667 break; 668 case 15: 669 case 16: 670 jRegA0 = 0x70; 671 jRegA3 = 0x04; 672 jRegA8 = 0x02; 673 break; 674 case 32: 675 jRegA0 = 0x70; 676 jRegA3 = 0x08; 677 jRegA8 = 0x02; 678 break; 679 } 680 SetIndexRegMask(CRTC_PORT,0xA0, 0x8F, (UCHAR) jRegA0); 681 SetIndexRegMask(CRTC_PORT,0xA3, 0xF0, (UCHAR) jRegA3); 682 SetIndexRegMask(CRTC_PORT,0xA8, 0xFD, (UCHAR) jRegA8); 683 684 /* Set Threshold */ 685 if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) ) 686 { 687 SetIndexReg(CRTC_PORT,0xA7, 0x3F); 688 SetIndexReg(CRTC_PORT,0xA6, 0x2F); 689 } 690 else 691 { 692 SetIndexReg(CRTC_PORT,0xA7, 0x2F); 693 SetIndexReg(CRTC_PORT,0xA6, 0x1F); 694 } 695 696} 697 698void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 699{ 700 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 701 ASTRecPtr pAST; 702 UCHAR jReg; 703 704 pAST = ASTPTR(pScrn); 705 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 706 707 jReg = GetReg(MISC_PORT_READ); 708 jReg |= (UCHAR) (pEnhModePtr->Flags & SyncNN); 709 SetReg(MISC_PORT_WRITE,jReg); 710 711} 712 713Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 714{ 715 PVBIOS_DAC_INFO pDACPtr; 716 ASTRecPtr pAST; 717 ULONG i, ulDACNumber; 718 UCHAR DACR, DACG, DACB; 719 720 pAST = ASTPTR(pScrn); 721 722 switch (pScrn->bitsPerPixel) 723 { 724 case 8: 725 ulDACNumber = DAC_NUM_VGA; 726 pDACPtr = (PVBIOS_DAC_INFO) &DAC_VGA[0]; 727 break; 728 default: 729 return (FALSE); 730 } 731 732 for (i=0; i<ulDACNumber; i++) 733 { 734 DACR = pDACPtr->DACR; 735 DACG = pDACPtr->DACG; 736 DACB = pDACPtr->DACB; 737 738 VGA_LOAD_PALETTE_INDEX (i, DACR, DACG, DACB); 739 740 pDACPtr++; 741 } 742 743 return (TRUE); 744 745} 746 747 748