ast_mode.c revision b4d38c65
1/* 2 * Copyright (c) 2005 ASPEED Technology Inc. 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that 7 * copyright notice and this permission notice appear in supporting 8 * documentation, and that the name of the authors not be used in 9 * advertising or publicity pertaining to distribution of the software without 10 * specific, written prior permission. The authors makes no representations 11 * about the suitability of this software for any purpose. It is provided 12 * "as is" without express or implied warranty. 13 * 14 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#ifdef HAVE_CONFIG_H 24#include <config.h> 25#endif 26#include "xf86.h" 27#include "xf86_OSproc.h" 28#include "xf86cmap.h" 29#include "compiler.h" 30#include "mibstore.h" 31#include "vgaHW.h" 32#include "mipointer.h" 33#include "micmap.h" 34 35#include "fb.h" 36#include "regionstr.h" 37#include "xf86xv.h" 38#include <X11/extensions/Xv.h> 39#include "vbe.h" 40 41#include "xf86PciInfo.h" 42#include "xf86Pci.h" 43 44/* framebuffer offscreen manager */ 45#include "xf86fbman.h" 46 47/* include xaa includes */ 48#include "xaarop.h" 49 50/* H/W cursor support */ 51#include "xf86Cursor.h" 52 53/* usleep() */ 54#include <unistd.h> 55 56/* Driver specific headers */ 57#include "ast.h" 58 59/* external reference fucntion */ 60extern Bool bInitAST1180(ScrnInfoPtr pScrn); 61 62VBIOS_STDTABLE_STRUCT StdTable[] = { 63 /* MD_2_3_400 */ 64 { 65 0x67, 66 {0x00,0x03,0x00,0x02}, 67 {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, 68 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, 69 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, 70 0xff}, 71 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 72 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 73 0x0c,0x00,0x0f,0x08}, 74 {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, 75 0xff} 76 }, 77 /* Mode12/ExtEGATable */ 78 { 79 0xe3, 80 {0x01,0x0f,0x00,0x06}, 81 {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, 82 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 83 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, 84 0xff}, 85 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 86 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 87 0x01,0x00,0x0f,0x00}, 88 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 89 0xff} 90 }, 91 /* ExtVGATable */ 92 { 93 0x2f, 94 {0x01,0x0f,0x00,0x0e}, 95 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 96 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 97 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 98 0xff}, 99 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 100 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 101 0x01,0x00,0x00,0x00}, 102 {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, 103 0xff} 104 }, 105 /* ExtHiCTable */ 106 { 107 0x2f, 108 {0x01,0x0f,0x00,0x0e}, 109 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 110 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 111 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 112 0xff}, 113 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 114 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 115 0x01,0x00,0x00,0x00}, 116 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 117 0xff} 118 }, 119 /* ExtTrueCTable */ 120 { 121 0x2f, 122 {0x01,0x0f,0x00,0x0e}, 123 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 124 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 125 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 126 0xff}, 127 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 128 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 129 0x01,0x00,0x00,0x00}, 130 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 131 0xff} 132 }, 133}; 134 135VBIOS_ENHTABLE_STRUCT Res640x480Table[] = { 136 { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ 137 (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, 138 { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ 139 (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, 140 { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ 141 (SyncNN | Charx8Dot) , 75, 3, 0x2E }, 142 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ 143 (SyncNN | Charx8Dot) , 85, 4, 0x2E }, 144 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ 145 (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, 146}; 147 148 149VBIOS_ENHTABLE_STRUCT Res800x600Table[] = { 150 {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ 151 (SyncPP | Charx8Dot), 56, 1, 0x30 }, 152 {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ 153 (SyncPP | Charx8Dot), 60, 2, 0x30 }, 154 {1040, 800, 56, 120, 666, 600, 37, 6, VCLK50, /* 72Hz */ 155 (SyncPP | Charx8Dot), 72, 3, 0x30 }, 156 {1056, 800, 16, 80, 625, 600, 1, 3, VCLK49_5, /* 75Hz */ 157 (SyncPP | Charx8Dot), 75, 4, 0x30 }, 158 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* 85Hz */ 159 (SyncPP | Charx8Dot), 84, 5, 0x30 }, 160 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* end */ 161 (SyncPP | Charx8Dot), 0xFF, 5, 0x30 }, 162}; 163 164 165VBIOS_ENHTABLE_STRUCT Res1024x768Table[] = { 166 {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ 167 (SyncNN | Charx8Dot), 60, 1, 0x31 }, 168 {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ 169 (SyncNN | Charx8Dot), 70, 2, 0x31 }, 170 {1312, 1024, 16, 96, 800, 768, 1, 3, VCLK78_75, /* 75Hz */ 171 (SyncPP | Charx8Dot), 75, 3, 0x31 }, 172 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* 85Hz */ 173 (SyncPP | Charx8Dot), 84, 4, 0x31 }, 174 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* end */ 175 (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, 176}; 177 178VBIOS_ENHTABLE_STRUCT Res1280x1024Table[] = { 179 {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ 180 (SyncPP | Charx8Dot), 60, 1, 0x32 }, 181 {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ 182 (SyncPP | Charx8Dot), 75, 2, 0x32 }, 183 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* 85Hz */ 184 (SyncPP | Charx8Dot), 85, 3, 0x32 }, 185 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* end */ 186 (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, 187}; 188 189VBIOS_ENHTABLE_STRUCT Res1600x1200Table[] = { 190 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ 191 (SyncPP | Charx8Dot), 60, 1, 0x33 }, 192 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ 193 (SyncPP | Charx8Dot), 0xFF, 1, 0x33 }, 194}; 195 196VBIOS_ENHTABLE_STRUCT Res1920x1200Table[] = { 197 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 198 (SyncNP | Charx8Dot), 60, 1, 0x34 }, 199 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 200 (SyncNP | Charx8Dot), 0xFF, 1, 0x34 }, 201}; 202 203/* 16:10 */ 204VBIOS_ENHTABLE_STRUCT Res1280x800Table[] = { 205 {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ 206 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 35 }, 207 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ 208 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 2, 0x35 }, 209 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ 210 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x35 }, 211 212}; 213 214VBIOS_ENHTABLE_STRUCT Res1440x900Table[] = { 215 {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ 216 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x36 }, 217 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ 218 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 2, 0x36 }, 219 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ 220 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x36 }, 221}; 222 223VBIOS_ENHTABLE_STRUCT Res1680x1050Table[] = { 224 {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ 225 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x37 }, 226 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ 227 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 2, 0x37 }, 228 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ 229 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x37 }, 230}; 231 232/* HDTV */ 233VBIOS_ENHTABLE_STRUCT Res1920x1080Table[] = { 234 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ 235 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x38 }, 236 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ 237 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x38 }, 238}; 239 240VBIOS_DCLK_INFO DCLKTable [] = { 241 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 242 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 243 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 244 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 245 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 246 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 247 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 248 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 249 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 250 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 251 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 252 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 253 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 254 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 255 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 256 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 257 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 258 {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */ 259 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 260 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 261 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 262 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 263 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 264 {0x77, 0x58, 0x80}, /* 17: VCLK119 */ 265}; 266 267VBIOS_DCLK_INFO DCLKTable_AST2100 [] = { 268 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 269 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 270 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 271 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 272 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 273 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 274 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 275 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 276 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 277 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 278 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 279 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 280 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 281 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 282 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 283 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 284 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 285 {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ 286 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 287 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 288 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 289 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 290 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 291 {0x77, 0x58, 0x80}, /* 17: VCLK119 */ 292}; 293 294VBIOS_DAC_INFO DAC_TEXT[] = { 295 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 296 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 297 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 298 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 299 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 300 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 301 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 302 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 303 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 304 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 305 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 306 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 307 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 308 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 309 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 310 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 311}; 312 313VBIOS_DAC_INFO DAC_EGA[] = { 314 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 315 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 316 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 317 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 318 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 319 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 320 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 321 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 322 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 323 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 324 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 325 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 326 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 327 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 328 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 329 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 330}; 331 332VBIOS_DAC_INFO DAC_VGA[] = { 333 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 334 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x15, 0x00 }, { 0x2a, 0x2a, 0x2a }, 335 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 336 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 337 { 0x00, 0x00, 0x00 }, { 0x05, 0x05, 0x05 }, { 0x08, 0x08, 0x08 }, { 0x0b, 0x0b, 0x0b }, 338 { 0x0e, 0x0e, 0x0e }, { 0x11, 0x11, 0x11 }, { 0x14, 0x14, 0x14 }, { 0x18, 0x18, 0x18 }, 339 { 0x1c, 0x1c, 0x1c }, { 0x20, 0x20, 0x20 }, { 0x24, 0x24, 0x24 }, { 0x28, 0x28, 0x28 }, 340 { 0x2d, 0x2d, 0x2d }, { 0x32, 0x32, 0x32 }, { 0x38, 0x38, 0x38 }, { 0x3f, 0x3f, 0x3f }, 341 { 0x00, 0x00, 0x3f }, { 0x10, 0x00, 0x3f }, { 0x1f, 0x00, 0x3f }, { 0x2f, 0x00, 0x3f }, 342 { 0x3f, 0x00, 0x3f }, { 0x3f, 0x00, 0x2f }, { 0x3f, 0x00, 0x1f }, { 0x3f, 0x00, 0x10 }, 343 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x10, 0x00 }, { 0x3f, 0x1f, 0x00 }, { 0x3f, 0x2f, 0x00 }, 344 { 0x3f, 0x3f, 0x00 }, { 0x2f, 0x3f, 0x00 }, { 0x1f, 0x3f, 0x00 }, { 0x10, 0x3f, 0x00 }, 345 { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x10 }, { 0x00, 0x3f, 0x1f }, { 0x00, 0x3f, 0x2f }, 346 { 0x00, 0x3f, 0x3f }, { 0x00, 0x2f, 0x3f }, { 0x00, 0x1f, 0x3f }, { 0x00, 0x10, 0x3f }, 347 { 0x1f, 0x1f, 0x3f }, { 0x27, 0x1f, 0x3f }, { 0x2f, 0x1f, 0x3f }, { 0x37, 0x1f, 0x3f }, 348 { 0x3f, 0x1f, 0x3f }, { 0x3f, 0x1f, 0x37 }, { 0x3f, 0x1f, 0x2f }, { 0x3f, 0x1f, 0x27 }, 349 { 0x3f, 0x1f, 0x1f }, { 0x3f, 0x27, 0x1f }, { 0x3f, 0x2f, 0x1f }, { 0x3f, 0x37, 0x1f }, 350 { 0x3f, 0x3f, 0x1f }, { 0x37, 0x3f, 0x1f }, { 0x2f, 0x3f, 0x1f }, { 0x27, 0x3f, 0x1f }, 351 { 0x1f, 0x3f, 0x1f }, { 0x1f, 0x3f, 0x27 }, { 0x1f, 0x3f, 0x2f }, { 0x1f, 0x3f, 0x37 }, 352 { 0x1f, 0x3f, 0x3f }, { 0x1f, 0x37, 0x3f }, { 0x1f, 0x2f, 0x3f }, { 0x1f, 0x27, 0x3f }, 353 { 0x2d, 0x2d, 0x3f }, { 0x31, 0x2d, 0x3f }, { 0x36, 0x2d, 0x3f }, { 0x3a, 0x2d, 0x3f }, 354 { 0x3f, 0x2d, 0x3f }, { 0x3f, 0x2d, 0x3a }, { 0x3f, 0x2d, 0x36 }, { 0x3f, 0x2d, 0x31 }, 355 { 0x3f, 0x2d, 0x2d }, { 0x3f, 0x31, 0x2d }, { 0x3f, 0x36, 0x2d }, { 0x3f, 0x3a, 0x2d }, 356 { 0x3f, 0x3f, 0x2d }, { 0x3a, 0x3f, 0x2d }, { 0x36, 0x3f, 0x2d }, { 0x31, 0x3f, 0x2d }, 357 { 0x2d, 0x3f, 0x2d }, { 0x2d, 0x3f, 0x31 }, { 0x2d, 0x3f, 0x36 }, { 0x2d, 0x3f, 0x3a }, 358 { 0x2d, 0x3f, 0x3f }, { 0x2d, 0x3a, 0x3f }, { 0x2d, 0x36, 0x3f }, { 0x2d, 0x31, 0x3f }, 359 { 0x00, 0x00, 0x1c }, { 0x07, 0x00, 0x1c }, { 0x0e, 0x00, 0x1c }, { 0x15, 0x00, 0x1c }, 360 { 0x1c, 0x00, 0x1c }, { 0x1c, 0x00, 0x15 }, { 0x1c, 0x00, 0x0e }, { 0x1c, 0x00, 0x07 }, 361 { 0x1c, 0x00, 0x00 }, { 0x1c, 0x07, 0x00 }, { 0x1c, 0x0e, 0x00 }, { 0x1c, 0x15, 0x00 }, 362 { 0x1c, 0x1c, 0x00 }, { 0x15, 0x1c, 0x00 }, { 0x0e, 0x1c, 0x00 }, { 0x07, 0x1c, 0x00 }, 363 { 0x00, 0x1c, 0x00 }, { 0x00, 0x1c, 0x07 }, { 0x00, 0x1c, 0x0e }, { 0x00, 0x1c, 0x15 }, 364 { 0x00, 0x1c, 0x1c }, { 0x00, 0x15, 0x1c }, { 0x00, 0x0e, 0x1c }, { 0x00, 0x07, 0x1c }, 365 { 0x0e, 0x0e, 0x1c }, { 0x11, 0x0e, 0x1c }, { 0x15, 0x0e, 0x1c }, { 0x18, 0x0e, 0x1c }, 366 { 0x1c, 0x0e, 0x1c }, { 0x1c, 0x0e, 0x18 }, { 0x1c, 0x0e, 0x15 }, { 0x1c, 0x0e, 0x11 }, 367 { 0x1c, 0x0e, 0x0e }, { 0x1c, 0x11, 0x0e }, { 0x1c, 0x15, 0x0e }, { 0x1c, 0x18, 0x0e }, 368 { 0x1c, 0x1c, 0x0e }, { 0x18, 0x1c, 0x0e }, { 0x15, 0x1c, 0x0e }, { 0x11, 0x1c, 0x0e }, 369 { 0x0e, 0x1c, 0x0e }, { 0x0e, 0x1c, 0x11 }, { 0x0e, 0x1c, 0x15 }, { 0x0e, 0x1c, 0x18 }, 370 { 0x0e, 0x1c, 0x1c }, { 0x0e, 0x18, 0x1c }, { 0x0e, 0x15, 0x1c }, { 0x0e, 0x11, 0x1c }, 371 { 0x14, 0x14, 0x1c }, { 0x16, 0x14, 0x1c }, { 0x18, 0x14, 0x1c }, { 0x1a, 0x14, 0x1c }, 372 { 0x1c, 0x14, 0x1c }, { 0x1c, 0x14, 0x1a }, { 0x1c, 0x14, 0x18 }, { 0x1c, 0x14, 0x16 }, 373 { 0x1c, 0x14, 0x14 }, { 0x1c, 0x16, 0x14 }, { 0x1c, 0x18, 0x14 }, { 0x1c, 0x1a, 0x14 }, 374 { 0x1c, 0x1c, 0x14 }, { 0x1a, 0x1c, 0x14 }, { 0x18, 0x1c, 0x14 }, { 0x16, 0x1c, 0x14 }, 375 { 0x14, 0x1c, 0x14 }, { 0x14, 0x1c, 0x16 }, { 0x14, 0x1c, 0x18 }, { 0x14, 0x1c, 0x1a }, 376 { 0x14, 0x1c, 0x1c }, { 0x14, 0x1a, 0x1c }, { 0x14, 0x18, 0x1c }, { 0x14, 0x16, 0x1c }, 377 { 0x00, 0x00, 0x10 }, { 0x04, 0x00, 0x10 }, { 0x08, 0x00, 0x10 }, { 0x0c, 0x00, 0x10 }, 378 { 0x10, 0x00, 0x10 }, { 0x10, 0x00, 0x0c }, { 0x10, 0x00, 0x08 }, { 0x10, 0x00, 0x04 }, 379 { 0x10, 0x00, 0x00 }, { 0x10, 0x04, 0x00 }, { 0x10, 0x08, 0x00 }, { 0x10, 0x0c, 0x00 }, 380 { 0x10, 0x10, 0x00 }, { 0x0c, 0x10, 0x00 }, { 0x08, 0x10, 0x00 }, { 0x04, 0x10, 0x00 }, 381 { 0x00, 0x10, 0x00 }, { 0x00, 0x10, 0x04 }, { 0x00, 0x10, 0x08 }, { 0x00, 0x10, 0x0c }, 382 { 0x00, 0x10, 0x10 }, { 0x00, 0x0c, 0x10 }, { 0x00, 0x08, 0x10 }, { 0x00, 0x04, 0x10 }, 383 { 0x08, 0x08, 0x10 }, { 0x0a, 0x08, 0x10 }, { 0x0c, 0x08, 0x10 }, { 0x0e, 0x08, 0x10 }, 384 { 0x10, 0x08, 0x10 }, { 0x10, 0x08, 0x0e }, { 0x10, 0x08, 0x0c }, { 0x10, 0x08, 0x0a }, 385 { 0x10, 0x08, 0x08 }, { 0x10, 0x0a, 0x08 }, { 0x10, 0x0c, 0x08 }, { 0x10, 0x0e, 0x08 }, 386 { 0x10, 0x10, 0x08 }, { 0x0e, 0x10, 0x08 }, { 0x0c, 0x10, 0x08 }, { 0x0a, 0x10, 0x08 }, 387 { 0x08, 0x10, 0x08 }, { 0x08, 0x10, 0x0a }, { 0x08, 0x10, 0x0c }, { 0x08, 0x10, 0x0e }, 388 { 0x08, 0x10, 0x10 }, { 0x08, 0x0e, 0x10 }, { 0x08, 0x0c, 0x10 }, { 0x08, 0x0a, 0x10 }, 389 { 0x0b, 0x0b, 0x10 }, { 0x0c, 0x0b, 0x10 }, { 0x0d, 0x0b, 0x10 }, { 0x0f, 0x0b, 0x10 }, 390 { 0x10, 0x0b, 0x10 }, { 0x10, 0x0b, 0x0f }, { 0x10, 0x0b, 0x0d }, { 0x10, 0x0b, 0x0c }, 391 { 0x10, 0x0b, 0x0b }, { 0x10, 0x0c, 0x0b }, { 0x10, 0x0d, 0x0b }, { 0x10, 0x0f, 0x0b }, 392 { 0x10, 0x10, 0x0b }, { 0x0f, 0x10, 0x0b }, { 0x0d, 0x10, 0x0b }, { 0x0c, 0x10, 0x0b }, 393 { 0x0b, 0x10, 0x0b }, { 0x0b, 0x10, 0x0c }, { 0x0b, 0x10, 0x0d }, { 0x0b, 0x10, 0x0f }, 394 { 0x0b, 0x10, 0x10 }, { 0x0b, 0x0f, 0x10 }, { 0x0b, 0x0d, 0x10 }, { 0x0b, 0x0c, 0x10 }, 395 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 396 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 397}; 398 399/* extern. function */ 400extern void vASTOpenKey(ScrnInfoPtr pScrn); 401extern Bool bASTRegInit(ScrnInfoPtr pScrn); 402extern void vAST1000DisplayOn(ASTRecPtr pAST); 403extern void vAST1000DisplayOff(ASTRecPtr pAST); 404 405extern Bool bEnable2D(ScrnInfoPtr pScrn, ASTRecPtr pAST); 406extern void vDisable2D(ScrnInfoPtr pScrn, ASTRecPtr pAST); 407 408extern Bool bInitHWC(ScrnInfoPtr pScrn, ASTRecPtr pAST); 409 410/* Prototype type declaration*/ 411Bool ASTSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode); 412Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 413void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 414void vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 415void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 416void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 417void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 418void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 419Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 420BOOL bSetAST1180CRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 421BOOL bSetAST1180OffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 422BOOL bSetAST1180DCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 423BOOL bSetAST1180ExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 424void vInitChontelReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 425 426Bool 427ASTSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode) 428{ 429 ASTRecPtr pAST; 430 VBIOS_MODE_INFO vgamodeinfo; 431 432 pAST = ASTPTR(pScrn); 433 434 /* pre set mode */ 435 bGetAST1000VGAModeInfo(pScrn, mode, &vgamodeinfo); 436 437 /* set mode */ 438 if (pAST->jChipType == AST1180) 439 { 440 bInitAST1180(pScrn); 441 442 bSetAST1180CRTCReg(pScrn, mode, &vgamodeinfo); 443 bSetAST1180OffsetReg(pScrn, mode, &vgamodeinfo); 444 bSetAST1180DCLKReg(pScrn, mode, &vgamodeinfo); 445 bSetAST1180ExtReg(pScrn, mode, &vgamodeinfo); 446 447 vInitChontelReg(pScrn, mode, &vgamodeinfo); 448 } 449 else 450 { 451 vASTOpenKey(pScrn); 452 bASTRegInit(pScrn); 453 454 vSetStdReg(pScrn, mode, &vgamodeinfo); 455 vSetCRTCReg(pScrn, mode, &vgamodeinfo); 456 vSetOffsetReg(pScrn, mode, &vgamodeinfo); 457 vSetDCLKReg(pScrn, mode, &vgamodeinfo); 458 vSetExtReg(pScrn, mode, &vgamodeinfo); 459 vSetSyncReg(pScrn, mode, &vgamodeinfo); 460 bSetDACReg(pScrn, mode, &vgamodeinfo); 461 } 462 463 /* post set mode */ 464#ifdef Accel_2D 465 if (!pAST->noAccel) { 466 if (!bEnable2D(pScrn, pAST)) { 467 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Enable 2D failed\n"); 468 pAST->noAccel = TRUE; 469 } 470 } 471#endif 472#ifdef HWC 473 if (!pAST->noHWC) { 474 if (!bInitHWC(pScrn, pAST)) { 475 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Init HWC failed\n"); 476 pAST->noHWC = TRUE; 477 } 478 } 479#endif 480 vAST1000DisplayOn(pAST); 481 482 return (TRUE); 483} 484 485 486Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 487{ 488 ASTRecPtr pAST; 489 ULONG ulModeID, ulColorIndex, ulRefreshRate, ulRefreshRateIndex = 0; 490 ULONG ulHBorder, ulVBorder; 491 492 pAST = ASTPTR(pScrn); 493 494 switch (pScrn->bitsPerPixel) 495 { 496 case 8: 497 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[VGAModeIndex]; 498 ulColorIndex = VGAModeIndex-1; 499 break; 500 case 16: 501 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[HiCModeIndex]; 502 ulColorIndex = HiCModeIndex; 503 break; 504 case 24: 505 case 32: 506 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[TrueCModeIndex]; 507 ulColorIndex = TrueCModeIndex; 508 break; 509 default: 510 return (FALSE); 511 } 512 513 switch (mode->CrtcHDisplay) 514 { 515 case 640: 516 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res640x480Table[ulRefreshRateIndex]; 517 break; 518 case 800: 519 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res800x600Table[ulRefreshRateIndex]; 520 break; 521 case 1024: 522 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1024x768Table[ulRefreshRateIndex]; 523 break; 524 case 1280: 525 if (mode->CrtcVDisplay == 800) 526 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x800Table[ulRefreshRateIndex]; 527 else 528 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x1024Table[ulRefreshRateIndex]; 529 break; 530 case 1440: 531 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1440x900Table[ulRefreshRateIndex]; 532 break; 533 case 1600: 534 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1600x1200Table[ulRefreshRateIndex]; 535 break; 536 case 1680: 537 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1680x1050Table[ulRefreshRateIndex]; 538 break; 539 case 1920: 540 if (mode->CrtcVDisplay == 1080) 541 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1080Table[ulRefreshRateIndex]; 542 else 543 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1200Table[ulRefreshRateIndex]; 544 break; 545 default: 546 return (FALSE); 547 } 548 549 /* Get Proper Mode Index */ 550 ulRefreshRate = (mode->Clock * 1000) / (mode->HTotal * mode->VTotal); 551 552 while (pVGAModeInfo->pEnhTableEntry->ulRefreshRate < ulRefreshRate) 553 { 554 pVGAModeInfo->pEnhTableEntry++; 555 if ((pVGAModeInfo->pEnhTableEntry->ulRefreshRate > ulRefreshRate) || 556 (pVGAModeInfo->pEnhTableEntry->ulRefreshRate == 0xFF)) 557 { 558 pVGAModeInfo->pEnhTableEntry--; 559 break; 560 } 561 } 562 563 /* parsing for wide scrren reduced blank mode */ 564 if (pVGAModeInfo->pEnhTableEntry->Flags & WideScreenMode) 565 { 566 if ((mode->Flags & V_PVSYNC) && (mode->Flags & V_NHSYNC)) /* CVT */ 567 pVGAModeInfo->pEnhTableEntry++; 568 } 569 570 /* Update mode CRTC info */ 571 ulHBorder = (pVGAModeInfo->pEnhTableEntry->Flags & HBorder) ? 8:0; 572 ulVBorder = (pVGAModeInfo->pEnhTableEntry->Flags & VBorder) ? 8:0; 573 574 mode->CrtcHTotal = (int) pVGAModeInfo->pEnhTableEntry->HT; 575 mode->CrtcHBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder); 576 mode->CrtcHBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->HT - ulHBorder); 577 mode->CrtcHSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 578 + pVGAModeInfo->pEnhTableEntry->HFP); 579 mode->CrtcHSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 580 + pVGAModeInfo->pEnhTableEntry->HFP 581 + pVGAModeInfo->pEnhTableEntry->HSYNC); 582 583 mode->CrtcVTotal = (int) pVGAModeInfo->pEnhTableEntry->VT; 584 mode->CrtcVBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder); 585 mode->CrtcVBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->VT - ulVBorder); 586 mode->CrtcVSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 587 + pVGAModeInfo->pEnhTableEntry->VFP); 588 mode->CrtcVSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 589 + pVGAModeInfo->pEnhTableEntry->VFP 590 + pVGAModeInfo->pEnhTableEntry->VSYNC); 591 592 /* Write mode info to scratch */ 593 ulRefreshRateIndex = pVGAModeInfo->pEnhTableEntry->ulRefreshRateIndex; 594 ulModeID = pVGAModeInfo->pEnhTableEntry->ulModeID; 595 596 if (pAST->jChipType == AST1180) 597 { 598 /* TODO */ 599 } 600 else 601 { 602 SetIndexReg(CRTC_PORT, 0x8C, (UCHAR) ((ulColorIndex & 0x0F) << 4)); 603 SetIndexReg(CRTC_PORT, 0x8D, (UCHAR) (ulRefreshRateIndex & 0xFF)); 604 SetIndexReg(CRTC_PORT, 0x8E, (UCHAR) (ulModeID & 0xFF)); 605 606 /* NewModeInfo */ 607 SetIndexReg(CRTC_PORT, 0x91, 0xA8); /* signature */ 608 SetIndexReg(CRTC_PORT, 0x92, (UCHAR) (pScrn->bitsPerPixel) ); 609 SetIndexReg(CRTC_PORT, 0x93, (UCHAR) (mode->Clock / 1000) ); 610 SetIndexReg(CRTC_PORT, 0x94, (UCHAR) (mode->CrtcHDisplay) ); 611 SetIndexReg(CRTC_PORT, 0x95, (UCHAR) (mode->CrtcHDisplay >> 8) ); /* color depth */ 612 SetIndexReg(CRTC_PORT, 0x96, (UCHAR) (mode->CrtcVDisplay) ); 613 SetIndexReg(CRTC_PORT, 0x97, (UCHAR) (mode->CrtcVDisplay >> 8) ); /* color depth */ 614 615 } 616 617 return (TRUE); 618} 619 620void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 621{ 622 623 PVBIOS_STDTABLE_STRUCT pStdModePtr; 624 ASTRecPtr pAST; 625 ULONG i; 626 UCHAR jReg; 627 628 pStdModePtr = pVGAModeInfo->pStdTableEntry; 629 pAST = ASTPTR(pScrn); 630 631 /* Set Misc */ 632 jReg = pStdModePtr->MISC; 633 SetReg(MISC_PORT_WRITE,jReg); 634 635 /* Set Seq */ 636 SetIndexReg(SEQ_PORT,0x00, 0x03); 637 for (i=0; i<4; i++) 638 { 639 jReg = pStdModePtr->SEQ[i]; 640 if (!i) (jReg |= 0x20); /* display off */ 641 SetIndexReg(SEQ_PORT,(UCHAR) (i+1), jReg); 642 } 643 644 /* Set CRTC */ 645 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 646 for (i=0; i<25; i++) 647 { 648 jReg = pStdModePtr->CRTC[i]; 649 SetIndexReg(CRTC_PORT,(UCHAR) i, jReg); 650 } 651 652 /* Set AR */ 653 jReg = GetReg(INPUT_STATUS1_READ); 654 for (i=0; i<20; i++) 655 { 656 jReg = pStdModePtr->AR[i]; 657 SetReg(AR_PORT_WRITE, (UCHAR) i); 658 SetReg(AR_PORT_WRITE, jReg); 659 } 660 SetReg(AR_PORT_WRITE, 0x14); 661 SetReg(AR_PORT_WRITE, 0x00); 662 663 jReg = GetReg(INPUT_STATUS1_READ); 664 SetReg (AR_PORT_WRITE, 0x20); /* set POS */ 665 666 /* Set GR */ 667 for (i=0; i<9; i++) 668 { 669 jReg = pStdModePtr->GR[i]; 670 SetIndexReg(GR_PORT,(UCHAR) i, jReg); 671 672 } 673 674 675} 676 677void 678vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 679{ 680 ASTRecPtr pAST; 681 USHORT usTemp; 682 UCHAR jReg05, jReg07, jReg09, jRegAC, jRegAD, jRegAE; 683 684 pAST = ASTPTR(pScrn); 685 jReg05 = jReg07 = jReg09 = jRegAC = jRegAD = jRegAE = 0; 686 687 /* unlock CRTC */ 688 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 689 690 /* Horizontal Timing Programming */ 691 usTemp = (mode->CrtcHTotal >> 3) - 5; 692 if (usTemp & 0x100) jRegAC |= 0x01; /* HT D[8] */ 693 SetIndexRegMask(CRTC_PORT,0x00, 0x00, (UCHAR) usTemp); 694 usTemp = (mode->CrtcHDisplay >> 3) - 1; 695 if (usTemp & 0x100) jRegAC |= 0x04; /* HDE D[8] */ 696 SetIndexRegMask(CRTC_PORT,0x01, 0x00, (UCHAR) usTemp); 697 usTemp = (mode->CrtcHBlankStart >> 3) - 1; 698 if (usTemp & 0x100) jRegAC |= 0x10; /* HBS D[8] */ 699 SetIndexRegMask(CRTC_PORT,0x02, 0x00, (UCHAR) usTemp); 700 usTemp = ((mode->CrtcHBlankEnd >> 3) - 1) & 0x7F; 701 if (usTemp & 0x20) jReg05 |= 0x80; /* HBE D[5] */ 702 if (usTemp & 0x40) jRegAD |= 0x01; /* HBE D[6] */ 703 SetIndexRegMask(CRTC_PORT,0x03, 0xE0, (UCHAR) (usTemp & 0x1F)); 704 usTemp = (mode->CrtcHSyncStart >> 3 ) - 1; 705 if (usTemp & 0x100) jRegAC |= 0x40; /* HRS D[5] */ 706 SetIndexRegMask(CRTC_PORT,0x04, 0x00, (UCHAR) (usTemp)); 707 usTemp = ((mode->CrtcHSyncEnd >> 3 ) - 1) & 0x3F; 708 if (usTemp & 0x20) jRegAD |= 0x04; /* HRE D[5] */ 709 SetIndexRegMask(CRTC_PORT,0x05, 0x60, (UCHAR) ((usTemp & 0x1F) | jReg05)); 710 711 SetIndexRegMask(CRTC_PORT,0xAC, 0x00, (UCHAR) jRegAC); 712 SetIndexRegMask(CRTC_PORT,0xAD, 0x00, (UCHAR) jRegAD); 713 714 /* Vetical Timing Programming */ 715 usTemp = (mode->CrtcVTotal) - 2; 716 if (usTemp & 0x100) jReg07 |= 0x01; /* VT D[8] */ 717 if (usTemp & 0x200) jReg07 |= 0x20; 718 if (usTemp & 0x400) jRegAE |= 0x01; /* VT D[10] */ 719 SetIndexRegMask(CRTC_PORT,0x06, 0x00, (UCHAR) usTemp); 720 usTemp = (mode->CrtcVSyncStart) - 1; 721 if (usTemp & 0x100) jReg07 |= 0x04; /* VRS D[8] */ 722 if (usTemp & 0x200) jReg07 |= 0x80; /* VRS D[9] */ 723 if (usTemp & 0x400) jRegAE |= 0x08; /* VRS D[10] */ 724 SetIndexRegMask(CRTC_PORT,0x10, 0x00, (UCHAR) usTemp); 725 usTemp = ((mode->CrtcVSyncEnd) - 1) & 0x3F; 726 if (usTemp & 0x10) jRegAE |= 0x20; /* VRE D[4] */ 727 if (usTemp & 0x20) jRegAE |= 0x40; /* VRE D[5] */ 728 SetIndexRegMask(CRTC_PORT,0x11, 0x70, (UCHAR) (usTemp & 0x0F)); 729 usTemp = (mode->CrtcVDisplay) - 1; 730 if (usTemp & 0x100) jReg07 |= 0x02; /* VDE D[8] */ 731 if (usTemp & 0x200) jReg07 |= 0x40; /* VDE D[9] */ 732 if (usTemp & 0x400) jRegAE |= 0x02; /* VDE D[10] */ 733 SetIndexRegMask(CRTC_PORT,0x12, 0x00, (UCHAR) usTemp); 734 usTemp = (mode->CrtcVBlankStart) - 1; 735 if (usTemp & 0x100) jReg07 |= 0x08; /* VBS D[8] */ 736 if (usTemp & 0x200) jReg09 |= 0x20; /* VBS D[9] */ 737 if (usTemp & 0x400) jRegAE |= 0x04; /* VBS D[10] */ 738 SetIndexRegMask(CRTC_PORT,0x15, 0x00, (UCHAR) usTemp); 739 usTemp = (mode->CrtcVBlankEnd) - 1 ; 740 if (usTemp & 0x100) jRegAE |= 0x10; /* VBE D[8] */ 741 SetIndexRegMask(CRTC_PORT,0x16, 0x00, (UCHAR) usTemp); 742 743 SetIndexRegMask(CRTC_PORT,0x07, 0x00, (UCHAR) jReg07); 744 SetIndexRegMask(CRTC_PORT,0x09, 0xDF, (UCHAR) jReg09); 745 SetIndexRegMask(CRTC_PORT,0xAE, 0x00, (UCHAR) (jRegAE | 0x80)); /* disable line compare */ 746 747 /* lock CRTC */ 748 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x80); 749 750} 751 752void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 753{ 754 ASTRecPtr pAST; 755 USHORT usOffset; 756 757 pAST = ASTPTR(pScrn); 758 759 usOffset = pAST->VideoModeInfo.ScreenPitch >> 3; /* Unit: char */ 760 761 SetIndexReg(CRTC_PORT,0x13, (UCHAR) (usOffset & 0xFF)); 762 SetIndexReg(CRTC_PORT,0xB0, (UCHAR) ((usOffset >> 8) & 0x3F)); 763 764} 765 766void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 767{ 768 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 769 PVBIOS_DCLK_INFO pDCLKPtr; 770 ASTRecPtr pAST; 771 772 pAST = ASTPTR(pScrn); 773 774 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 775 if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) || (pAST->jChipType == AST2300)) 776 pDCLKPtr = &DCLKTable_AST2100[pEnhModePtr->DCLKIndex]; 777 else 778 pDCLKPtr = &DCLKTable[pEnhModePtr->DCLKIndex]; 779 780 SetIndexRegMask(CRTC_PORT,0xC0, 0x00, pDCLKPtr->Param1); 781 SetIndexRegMask(CRTC_PORT,0xC1, 0x00, pDCLKPtr->Param2); 782 SetIndexRegMask(CRTC_PORT,0xBB, 0x0F, (pDCLKPtr->Param3 & 0x80) | ((pDCLKPtr->Param3 & 0x03) << 4) ); 783 784} 785 786 787void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 788{ 789 790 ASTRecPtr pAST; 791 UCHAR jRegA0, jRegA3, jRegA8; 792 793 pAST = ASTPTR(pScrn); 794 795 jRegA0=jRegA3=jRegA8=0; 796 /* Mode Type Setting */ 797 switch (pScrn->bitsPerPixel) { 798 case 8: 799 jRegA0 = 0x70; 800 jRegA3 = 0x01; 801 jRegA8 = 0x00; 802 break; 803 case 15: 804 case 16: 805 jRegA0 = 0x70; 806 jRegA3 = 0x04; 807 jRegA8 = 0x02; 808 break; 809 case 32: 810 jRegA0 = 0x70; 811 jRegA3 = 0x08; 812 jRegA8 = 0x02; 813 break; 814 } 815 SetIndexRegMask(CRTC_PORT,0xA0, 0x8F, (UCHAR) jRegA0); 816 SetIndexRegMask(CRTC_PORT,0xA3, 0xF0, (UCHAR) jRegA3); 817 SetIndexRegMask(CRTC_PORT,0xA8, 0xFD, (UCHAR) jRegA8); 818 819#if defined(__sparc__) 820 UCHAR jRegA2 = 0x80; 821 if ((pScrn->bitsPerPixel == 15) || (pScrn->bitsPerPixel == 16) ) 822 jRegA2 |= 0x40; 823 SetIndexRegMask(CRTC_PORT,0xA2, 0x3F, (UCHAR) jRegA2); 824#endif 825 826 /* Set Threshold */ 827 if (pAST->jChipType == AST2300) 828 { 829 SetIndexReg(CRTC_PORT,0xA7, 0x78); 830 SetIndexReg(CRTC_PORT,0xA6, 0x60); 831 } 832 else if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) ) 833 { 834 SetIndexReg(CRTC_PORT,0xA7, 0x3F); 835 SetIndexReg(CRTC_PORT,0xA6, 0x2F); 836 } 837 else 838 { 839 SetIndexReg(CRTC_PORT,0xA7, 0x2F); 840 SetIndexReg(CRTC_PORT,0xA6, 0x1F); 841 } 842 843} 844 845void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 846{ 847 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 848 ASTRecPtr pAST; 849 UCHAR jReg; 850 851 pAST = ASTPTR(pScrn); 852 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 853 854 jReg = GetReg(MISC_PORT_READ); 855 jReg |= (UCHAR) (pEnhModePtr->Flags & SyncNN); 856 SetReg(MISC_PORT_WRITE,jReg); 857 858} 859 860Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 861{ 862 PVBIOS_DAC_INFO pDACPtr; 863 ASTRecPtr pAST; 864 ULONG i, ulDACNumber; 865 UCHAR DACR, DACG, DACB; 866 867 pAST = ASTPTR(pScrn); 868 869 switch (pScrn->bitsPerPixel) 870 { 871 case 8: 872 ulDACNumber = DAC_NUM_VGA; 873 pDACPtr = (PVBIOS_DAC_INFO) &DAC_VGA[0]; 874 break; 875 default: 876 return (FALSE); 877 } 878 879 for (i=0; i<ulDACNumber; i++) 880 { 881 DACR = pDACPtr->DACR; 882 DACG = pDACPtr->DACG; 883 DACB = pDACPtr->DACB; 884 885 VGA_LOAD_PALETTE_INDEX (i, DACR, DACG, DACB); 886 887 pDACPtr++; 888 } 889 890 return (TRUE); 891 892} 893 894ULONG AST1180DCLKTable [] = { 895 0x0008676b, /* 00: VCLK25_175 */ 896 0x00086342, /* 01: VCLK28_322 */ 897 0x00086568, /* 02: VCLK31_5 */ 898 0x00082118, /* 03: VCLK36 */ 899 0x0008232e, /* 04: VCLK40 */ 900 0x000c256d, /* 05: VCLK49_5 */ 901 0x00082016, /* 06: VCLK50 */ 902 0x000c0010, /* 07: VCLK56_25 */ 903 0x000c0332, /* 08: VCLK65 */ 904 0x00080010, /* 09: VCLK75 */ 905 0x000c033d, /* 0A: VCLK78_75 */ 906 0x000c0568, /* 0B: VCLK94_5 */ 907 0x00040118, /* 0C: VCLK108 */ 908 0x00040334, /* 0D: VCLK135 */ 909 0x0004033d, /* 0E: VCLK157_5 */ 910 0x00040018, /* 0F: VCLK162 */ 911 0x00040123, /* 10: VCLK154 */ 912 0x000c0669, /* 11: VCLK83_5 */ 913 0x0004074b, /* 12: VCLK106_5 */ 914 0x0004022d, /* 13: VCLK146_25 */ 915 0x00040769, /* 14: VCLK148_5 */ 916}; 917 918BOOL bSetAST1180CRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 919{ 920 ASTRecPtr pAST = ASTPTR(pScrn); 921 922 ULONG HTIndex, HRIndex, VTIndex, VRIndex; 923 ULONG HT, HDE, HBS, HBE, HRS, HRE; 924 ULONG VT, VDE, VBS, VBE, VRS, VRE; 925 ULONG HT2, HDE2, HRS2, HRE2; 926 ULONG VT2, VDE2, VRS2, VRE2; 927 928 /* Reg. Index Select */ 929 { 930 HTIndex = AST1180_VGA1_HTREG; 931 HRIndex = AST1180_VGA1_HRREG; 932 VTIndex = AST1180_VGA1_VTREG; 933 VRIndex = AST1180_VGA1_VRREG; 934 } 935 936 /* Get CRTC Info */ 937 HT = mode->CrtcHTotal; 938 HDE= mode->CrtcHDisplay; 939 HBS= mode->CrtcHBlankStart; 940 HBE= mode->CrtcHBlankEnd; 941 HRS= mode->CrtcHSyncStart; 942 HRE= mode->CrtcHSyncEnd; 943 VT = mode->CrtcVTotal; 944 VDE= mode->CrtcVDisplay; 945 VBS= mode->CrtcVBlankStart; 946 VBE= mode->CrtcVBlankEnd; 947 VRS= mode->CrtcVSyncStart; 948 VRE= mode->CrtcVSyncEnd; 949 950 /* Calculate CRTC Reg Setting */ 951 HT2 = HT - 1; 952 HDE2 = HDE - 1; 953 HRS2 = HRS - 1; 954 HRE2 = HRE - 1; 955 VT2 = VT - 1; 956 VDE2 = VDE - 1; 957 VRS2 = VRS - 1; 958 VRE2 = VRE - 1; 959 960 /* Write Reg */ 961 WriteAST1180SOC(AST1180_GFX_BASE + HTIndex, (ULONG)(HDE2 << 16) | (ULONG) (HT2)); 962 WriteAST1180SOC(AST1180_GFX_BASE + HRIndex, (ULONG)(HRE2 << 16) | (ULONG) (HRS2)); 963 WriteAST1180SOC(AST1180_GFX_BASE + VTIndex, (ULONG)(VDE2 << 16) | (ULONG) (VT2)); 964 WriteAST1180SOC(AST1180_GFX_BASE + VRIndex, (ULONG)(VRE2 << 16) | (ULONG) (VRS2)); 965 966 return (TRUE); 967 968} /* bSetAST1180CRTCReg */ 969 970BOOL bSetAST1180OffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 971{ 972 ASTRecPtr pAST = ASTPTR(pScrn); 973 ULONG ulOffset, ulTermalCount; 974 975 ulOffset = pAST->VideoModeInfo.ScreenPitch; 976 ulTermalCount = (pAST->VideoModeInfo.ScreenPitch + 7) >> 3; 977 978 /* Write Reg */ 979 WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_OFFSET, (ULONG) (ulTermalCount << 16) | (ULONG) (ulOffset)); 980 981 return (TRUE); 982 983} /* bSetAST1180OffsetReg */ 984 985BOOL bSetAST1180DCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 986{ 987 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 988 ASTRecPtr pAST = ASTPTR(pScrn); 989 ULONG ulDCLK; 990 991 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 992 ulDCLK = AST1180DCLKTable[pEnhModePtr->DCLKIndex]; 993 if (pEnhModePtr->Flags & HalfDCLK) 994 ulDCLK |= 0x00400000; /* D[22]: div by 2 */ 995 WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_PLL, ulDCLK); 996 997 return (TRUE); 998} 999 1000BOOL bSetAST1180ExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1001{ 1002 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 1003 ASTRecPtr pAST = ASTPTR(pScrn); 1004 1005 ULONG ulCtlRegIndex, ulCtlReg; /* enable display */ 1006 ULONG ulCtlReg2Index, ulCtlReg2 = 0x80; /* single edge */ 1007 ULONG ulThresholdRegIndex ; /* Threshold */ 1008 ULONG ulStartAddressIndex; /* ulStartAddress */ 1009 ULONG ulStartAddress = pAST->ulVRAMBase; 1010 1011 /* Reg. Index Select */ 1012 { 1013 ulCtlRegIndex = AST1180_VGA1_CTRL; 1014 ulCtlReg2Index = AST1180_VGA1_CTRL2; 1015 ulThresholdRegIndex = AST1180_VGA1_THRESHOLD; 1016 ulStartAddressIndex = AST1180_VGA1_STARTADDR; 1017 } 1018 1019 /* Mode Type Setting */ 1020 ulCtlReg = 0x30000000; 1021 { 1022 switch (pScrn->bitsPerPixel) { 1023 case 15: 1024 case 16: 1025 ulCtlReg |= 0x100001; /* RGB565, SCREEN OFF, ENABLE */ 1026 break; 1027 case 32: 1028 ulCtlReg |= 0x100101; /* XRGB8888, SCREEN OFF, ENABLE */ 1029 break; 1030 } 1031 } 1032 1033 /* Polarity */ 1034 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1035 ulCtlReg |= (ULONG) (pEnhModePtr->Flags & SyncNN) << 10; 1036 1037 /* Single/Dual Edge */ 1038 ulCtlReg2 |= 0x40; /* dual-edge */ 1039 1040 /* Write Reg */ 1041 WriteAST1180SOC(AST1180_GFX_BASE + ulStartAddressIndex, ulStartAddress); 1042 WriteAST1180SOC(AST1180_GFX_BASE + ulThresholdRegIndex, ((ULONG) CRT_HIGH_THRESHOLD_VALUE << 8) | (ULONG) (CRT_LOW_THRESHOLD_VALUE)); 1043 WriteAST1180SOC(AST1180_GFX_BASE + ulCtlReg2Index, ulCtlReg2); 1044 WriteAST1180SOC(AST1180_GFX_BASE + ulCtlRegIndex, ulCtlReg); 1045 1046 return (TRUE); 1047 1048} /* bSetAST1180ExtReg */ 1049 1050#define I2C_BASE_AST1180 0x80fcb000 1051#define I2C_DEVICEADDR_AST1180 0x0EC /* slave addr */ 1052 1053void SetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex, UCHAR jData ) 1054{ 1055 ULONG ulData, ulI2CAddr, ulI2CPortBase; 1056 ULONG retry; 1057 1058 { 1059 ulI2CPortBase = I2C_BASE_AST1180 + 0x40 * jChannel; 1060 ulI2CAddr = I2C_DEVICEADDR_AST1180; 1061 } 1062 1063 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x00); 1064 WriteAST1180SOC(ulI2CPortBase + 0x04, 0x77743355); 1065 WriteAST1180SOC(ulI2CPortBase + 0x08, 0x0); 1066 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1067 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x1); 1068 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xAF); 1069 WriteAST1180SOC(ulI2CPortBase + 0x20, ulI2CAddr); 1070 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x03); 1071 retry = 0; 1072 do { 1073 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1074 usleep(10); 1075 if (retry++ > 1000) 1076 goto Exit_SetChrontelReg; 1077 } while (!(ulData & 0x01)); 1078 1079 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1080 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jIndex); 1081 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1082 do { 1083 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1084 } while (!(ulData & 0x01)); 1085 1086 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1087 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jData); 1088 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1089 do { 1090 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1091 } while (!(ulData & 0x01)); 1092 1093 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1094 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xBF); 1095 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x20); 1096 do { 1097 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1098 } while (!(ulData & 0x10)); 1099 1100 ReadAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1101 ulData &= 0xffffffef; 1102 WriteAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1103 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1104 1105Exit_SetChrontelReg: 1106 ; 1107} 1108 1109UCHAR GetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex) 1110{ 1111 ULONG ulData, ulI2CAddr, ulI2CPortBase; 1112 UCHAR jData; 1113 ULONG retry; 1114 1115 { 1116 ulI2CPortBase = I2C_BASE_AST1180 + 0x40 * jChannel; 1117 ulI2CAddr = I2C_DEVICEADDR_AST1180; 1118 } 1119 1120 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x00); 1121 WriteAST1180SOC(ulI2CPortBase + 0x04, 0x77743355); 1122 WriteAST1180SOC(ulI2CPortBase + 0x08, 0x0); 1123 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1124 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x1); 1125 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xAF); 1126 WriteAST1180SOC(ulI2CPortBase + 0x20, ulI2CAddr); 1127 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x03); 1128 retry = 0; 1129 do { 1130 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1131 usleep(10); 1132 if (retry++ > 1000) 1133 return 0; 1134 } while (!(ulData & 0x01)); 1135 1136 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1137 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jIndex); 1138 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1139 do { 1140 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1141 } while (!(ulData & 0x01)); 1142 1143 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1144 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) (ulI2CAddr + 1) ); 1145 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x1B); 1146 do { 1147 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1148 } while (!(ulData & 0x04)); 1149 1150 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1151 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xBF); 1152 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x20); 1153 do { 1154 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1155 } while (!(ulData & 0x10)); 1156 1157 ReadAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1158 ulData &= 0xffffffef; 1159 WriteAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1160 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1161 1162 ReadAST1180SOC(ulI2CPortBase + 0x20, ulData); 1163 jData = (UCHAR) ((ulData & 0xFF00) >> 8); 1164 1165 return (jData); 1166} 1167 1168void vInitChontelReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1169{ 1170 1171 PVBIOS_ENHTABLE_STRUCT pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1172 ASTRecPtr pAST = ASTPTR(pScrn); 1173 ULONG ulDCLK = 65; /* todo */ 1174 UCHAR jReg; 1175 1176 jReg = GetChrontelReg(pAST, 1, 0x4A); /* get vendor id */ 1177 if (jReg == 0x95) 1178 { 1179 jReg = GetChrontelReg(pAST, 1, 0x20); /* DVI/D-Sub */ 1180 if (jReg & 0x20) /* DVI */ 1181 { 1182 1183 /* DVI PLL Filter */ 1184 if (ulDCLK > 65) 1185 { 1186 SetChrontelReg(pAST, 1, 0x33, 0x06); 1187 SetChrontelReg(pAST, 1, 0x34, 0x26); 1188 SetChrontelReg(pAST, 1, 0x36, 0xA0); 1189 } 1190 else 1191 { 1192 SetChrontelReg(pAST, 1, 0x33, 0x08); 1193 SetChrontelReg(pAST, 1, 0x34, 0x16); 1194 SetChrontelReg(pAST, 1, 0x36, 0x60); 1195 } 1196 1197 SetChrontelReg(pAST, 1, 0x49, 0xc0); 1198 } 1199 else /* D-Sub */ 1200 { 1201 1202 SetChrontelReg(pAST, 1, 0x21, 0x09); 1203 SetChrontelReg(pAST, 1, 0x49, 0x00); 1204 SetChrontelReg(pAST, 1, 0x56, 0x00); 1205 } 1206 } 1207 1208} 1209 1210