ast_mode.c revision b534f209
1/* 2 * Copyright (c) 2005 ASPEED Technology Inc. 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that 7 * copyright notice and this permission notice appear in supporting 8 * documentation, and that the name of the authors not be used in 9 * advertising or publicity pertaining to distribution of the software without 10 * specific, written prior permission. The authors makes no representations 11 * about the suitability of this software for any purpose. It is provided 12 * "as is" without express or implied warranty. 13 * 14 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#ifdef HAVE_CONFIG_H 24#include <config.h> 25#endif 26#include "xf86.h" 27#include "xf86_OSproc.h" 28#include "xf86cmap.h" 29#include "compiler.h" 30#include "mibstore.h" 31#include "vgaHW.h" 32#include "mipointer.h" 33#include "micmap.h" 34 35#include "fb.h" 36#include "regionstr.h" 37#include "xf86xv.h" 38#include <X11/extensions/Xv.h> 39#include "vbe.h" 40 41#include "xf86PciInfo.h" 42#include "xf86Pci.h" 43 44/* framebuffer offscreen manager */ 45#include "xf86fbman.h" 46 47/* include xaa includes */ 48#include "xaa.h" 49#include "xaarop.h" 50 51/* H/W cursor support */ 52#include "xf86Cursor.h" 53 54/* usleep() */ 55#include <unistd.h> 56 57/* Driver specific headers */ 58#include "ast.h" 59 60/* external reference fucntion */ 61extern Bool bInitAST1180(ScrnInfoPtr pScrn); 62 63VBIOS_STDTABLE_STRUCT StdTable[] = { 64 /* MD_2_3_400 */ 65 { 66 0x67, 67 {0x00,0x03,0x00,0x02}, 68 {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, 69 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, 70 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, 71 0xff}, 72 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 73 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 74 0x0c,0x00,0x0f,0x08}, 75 {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, 76 0xff} 77 }, 78 /* Mode12/ExtEGATable */ 79 { 80 0xe3, 81 {0x01,0x0f,0x00,0x06}, 82 {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, 83 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 84 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, 85 0xff}, 86 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 87 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 88 0x01,0x00,0x0f,0x00}, 89 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 90 0xff} 91 }, 92 /* ExtVGATable */ 93 { 94 0x2f, 95 {0x01,0x0f,0x00,0x0e}, 96 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 97 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 98 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 99 0xff}, 100 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 101 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 102 0x01,0x00,0x00,0x00}, 103 {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, 104 0xff} 105 }, 106 /* ExtHiCTable */ 107 { 108 0x2f, 109 {0x01,0x0f,0x00,0x0e}, 110 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 111 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 112 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 113 0xff}, 114 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 115 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 116 0x01,0x00,0x00,0x00}, 117 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 118 0xff} 119 }, 120 /* ExtTrueCTable */ 121 { 122 0x2f, 123 {0x01,0x0f,0x00,0x0e}, 124 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 125 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 126 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 127 0xff}, 128 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 129 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 130 0x01,0x00,0x00,0x00}, 131 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 132 0xff} 133 }, 134}; 135 136VBIOS_ENHTABLE_STRUCT Res640x480Table[] = { 137 { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ 138 (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, 139 { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ 140 (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, 141 { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ 142 (SyncNN | Charx8Dot) , 75, 3, 0x2E }, 143 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ 144 (SyncNN | Charx8Dot) , 85, 4, 0x2E }, 145 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ 146 (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, 147}; 148 149 150VBIOS_ENHTABLE_STRUCT Res800x600Table[] = { 151 {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ 152 (SyncPP | Charx8Dot), 56, 1, 0x30 }, 153 {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ 154 (SyncPP | Charx8Dot), 60, 2, 0x30 }, 155 {1040, 800, 56, 120, 666, 600, 37, 6, VCLK50, /* 72Hz */ 156 (SyncPP | Charx8Dot), 72, 3, 0x30 }, 157 {1056, 800, 16, 80, 625, 600, 1, 3, VCLK49_5, /* 75Hz */ 158 (SyncPP | Charx8Dot), 75, 4, 0x30 }, 159 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* 85Hz */ 160 (SyncPP | Charx8Dot), 84, 5, 0x30 }, 161 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* end */ 162 (SyncPP | Charx8Dot), 0xFF, 5, 0x30 }, 163}; 164 165 166VBIOS_ENHTABLE_STRUCT Res1024x768Table[] = { 167 {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ 168 (SyncNN | Charx8Dot), 60, 1, 0x31 }, 169 {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ 170 (SyncNN | Charx8Dot), 70, 2, 0x31 }, 171 {1312, 1024, 16, 96, 800, 768, 1, 3, VCLK78_75, /* 75Hz */ 172 (SyncPP | Charx8Dot), 75, 3, 0x31 }, 173 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* 85Hz */ 174 (SyncPP | Charx8Dot), 84, 4, 0x31 }, 175 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* end */ 176 (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, 177}; 178 179VBIOS_ENHTABLE_STRUCT Res1280x1024Table[] = { 180 {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ 181 (SyncPP | Charx8Dot), 60, 1, 0x32 }, 182 {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ 183 (SyncPP | Charx8Dot), 75, 2, 0x32 }, 184 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* 85Hz */ 185 (SyncPP | Charx8Dot), 85, 3, 0x32 }, 186 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* end */ 187 (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, 188}; 189 190VBIOS_ENHTABLE_STRUCT Res1600x1200Table[] = { 191 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ 192 (SyncPP | Charx8Dot), 60, 1, 0x33 }, 193 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ 194 (SyncPP | Charx8Dot), 0xFF, 1, 0x33 }, 195}; 196 197VBIOS_ENHTABLE_STRUCT Res1920x1200Table[] = { 198 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 199 (SyncNP | Charx8Dot), 60, 1, 0x34 }, 200 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 201 (SyncNP | Charx8Dot), 0xFF, 1, 0x34 }, 202}; 203 204/* 16:10 */ 205VBIOS_ENHTABLE_STRUCT Res1280x800Table[] = { 206 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ 207 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x35 }, 208 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ 209 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x35 }, 210 211}; 212 213VBIOS_ENHTABLE_STRUCT Res1440x900Table[] = { 214 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ 215 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x36 }, 216 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ 217 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x36 }, 218}; 219 220VBIOS_ENHTABLE_STRUCT Res1680x1050Table[] = { 221 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ 222 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x37 }, 223 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ 224 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x37 }, 225}; 226 227/* HDTV */ 228VBIOS_ENHTABLE_STRUCT Res1920x1080Table[] = { 229 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ 230 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x38 }, 231 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */ 232 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x38 }, 233}; 234 235VBIOS_DCLK_INFO DCLKTable [] = { 236 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 237 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 238 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 239 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 240 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 241 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 242 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 243 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 244 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 245 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 246 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 247 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 248 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 249 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 250 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 251 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 252 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 253 {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */ 254 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 255 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 256 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 257}; 258 259VBIOS_DCLK_INFO DCLKTable_AST2100 [] = { 260 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 261 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 262 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 263 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 264 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 265 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 266 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 267 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 268 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 269 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 270 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 271 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 272 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 273 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 274 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 275 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 276 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 277 {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ 278 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 279 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 280 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 281}; 282 283VBIOS_DAC_INFO DAC_TEXT[] = { 284 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 285 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 286 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 287 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 288 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 289 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 290 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 291 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 292 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 293 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 294 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 295 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 296 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 297 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 298 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 299 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 300}; 301 302VBIOS_DAC_INFO DAC_EGA[] = { 303 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 304 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 305 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 306 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 307 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 308 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 309 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 310 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 311 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 312 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 313 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 314 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 315 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 316 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 317 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 318 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 319}; 320 321VBIOS_DAC_INFO DAC_VGA[] = { 322 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 323 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x15, 0x00 }, { 0x2a, 0x2a, 0x2a }, 324 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 325 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 326 { 0x00, 0x00, 0x00 }, { 0x05, 0x05, 0x05 }, { 0x08, 0x08, 0x08 }, { 0x0b, 0x0b, 0x0b }, 327 { 0x0e, 0x0e, 0x0e }, { 0x11, 0x11, 0x11 }, { 0x14, 0x14, 0x14 }, { 0x18, 0x18, 0x18 }, 328 { 0x1c, 0x1c, 0x1c }, { 0x20, 0x20, 0x20 }, { 0x24, 0x24, 0x24 }, { 0x28, 0x28, 0x28 }, 329 { 0x2d, 0x2d, 0x2d }, { 0x32, 0x32, 0x32 }, { 0x38, 0x38, 0x38 }, { 0x3f, 0x3f, 0x3f }, 330 { 0x00, 0x00, 0x3f }, { 0x10, 0x00, 0x3f }, { 0x1f, 0x00, 0x3f }, { 0x2f, 0x00, 0x3f }, 331 { 0x3f, 0x00, 0x3f }, { 0x3f, 0x00, 0x2f }, { 0x3f, 0x00, 0x1f }, { 0x3f, 0x00, 0x10 }, 332 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x10, 0x00 }, { 0x3f, 0x1f, 0x00 }, { 0x3f, 0x2f, 0x00 }, 333 { 0x3f, 0x3f, 0x00 }, { 0x2f, 0x3f, 0x00 }, { 0x1f, 0x3f, 0x00 }, { 0x10, 0x3f, 0x00 }, 334 { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x10 }, { 0x00, 0x3f, 0x1f }, { 0x00, 0x3f, 0x2f }, 335 { 0x00, 0x3f, 0x3f }, { 0x00, 0x2f, 0x3f }, { 0x00, 0x1f, 0x3f }, { 0x00, 0x10, 0x3f }, 336 { 0x1f, 0x1f, 0x3f }, { 0x27, 0x1f, 0x3f }, { 0x2f, 0x1f, 0x3f }, { 0x37, 0x1f, 0x3f }, 337 { 0x3f, 0x1f, 0x3f }, { 0x3f, 0x1f, 0x37 }, { 0x3f, 0x1f, 0x2f }, { 0x3f, 0x1f, 0x27 }, 338 { 0x3f, 0x1f, 0x1f }, { 0x3f, 0x27, 0x1f }, { 0x3f, 0x2f, 0x1f }, { 0x3f, 0x37, 0x1f }, 339 { 0x3f, 0x3f, 0x1f }, { 0x37, 0x3f, 0x1f }, { 0x2f, 0x3f, 0x1f }, { 0x27, 0x3f, 0x1f }, 340 { 0x1f, 0x3f, 0x1f }, { 0x1f, 0x3f, 0x27 }, { 0x1f, 0x3f, 0x2f }, { 0x1f, 0x3f, 0x37 }, 341 { 0x1f, 0x3f, 0x3f }, { 0x1f, 0x37, 0x3f }, { 0x1f, 0x2f, 0x3f }, { 0x1f, 0x27, 0x3f }, 342 { 0x2d, 0x2d, 0x3f }, { 0x31, 0x2d, 0x3f }, { 0x36, 0x2d, 0x3f }, { 0x3a, 0x2d, 0x3f }, 343 { 0x3f, 0x2d, 0x3f }, { 0x3f, 0x2d, 0x3a }, { 0x3f, 0x2d, 0x36 }, { 0x3f, 0x2d, 0x31 }, 344 { 0x3f, 0x2d, 0x2d }, { 0x3f, 0x31, 0x2d }, { 0x3f, 0x36, 0x2d }, { 0x3f, 0x3a, 0x2d }, 345 { 0x3f, 0x3f, 0x2d }, { 0x3a, 0x3f, 0x2d }, { 0x36, 0x3f, 0x2d }, { 0x31, 0x3f, 0x2d }, 346 { 0x2d, 0x3f, 0x2d }, { 0x2d, 0x3f, 0x31 }, { 0x2d, 0x3f, 0x36 }, { 0x2d, 0x3f, 0x3a }, 347 { 0x2d, 0x3f, 0x3f }, { 0x2d, 0x3a, 0x3f }, { 0x2d, 0x36, 0x3f }, { 0x2d, 0x31, 0x3f }, 348 { 0x00, 0x00, 0x1c }, { 0x07, 0x00, 0x1c }, { 0x0e, 0x00, 0x1c }, { 0x15, 0x00, 0x1c }, 349 { 0x1c, 0x00, 0x1c }, { 0x1c, 0x00, 0x15 }, { 0x1c, 0x00, 0x0e }, { 0x1c, 0x00, 0x07 }, 350 { 0x1c, 0x00, 0x00 }, { 0x1c, 0x07, 0x00 }, { 0x1c, 0x0e, 0x00 }, { 0x1c, 0x15, 0x00 }, 351 { 0x1c, 0x1c, 0x00 }, { 0x15, 0x1c, 0x00 }, { 0x0e, 0x1c, 0x00 }, { 0x07, 0x1c, 0x00 }, 352 { 0x00, 0x1c, 0x00 }, { 0x00, 0x1c, 0x07 }, { 0x00, 0x1c, 0x0e }, { 0x00, 0x1c, 0x15 }, 353 { 0x00, 0x1c, 0x1c }, { 0x00, 0x15, 0x1c }, { 0x00, 0x0e, 0x1c }, { 0x00, 0x07, 0x1c }, 354 { 0x0e, 0x0e, 0x1c }, { 0x11, 0x0e, 0x1c }, { 0x15, 0x0e, 0x1c }, { 0x18, 0x0e, 0x1c }, 355 { 0x1c, 0x0e, 0x1c }, { 0x1c, 0x0e, 0x18 }, { 0x1c, 0x0e, 0x15 }, { 0x1c, 0x0e, 0x11 }, 356 { 0x1c, 0x0e, 0x0e }, { 0x1c, 0x11, 0x0e }, { 0x1c, 0x15, 0x0e }, { 0x1c, 0x18, 0x0e }, 357 { 0x1c, 0x1c, 0x0e }, { 0x18, 0x1c, 0x0e }, { 0x15, 0x1c, 0x0e }, { 0x11, 0x1c, 0x0e }, 358 { 0x0e, 0x1c, 0x0e }, { 0x0e, 0x1c, 0x11 }, { 0x0e, 0x1c, 0x15 }, { 0x0e, 0x1c, 0x18 }, 359 { 0x0e, 0x1c, 0x1c }, { 0x0e, 0x18, 0x1c }, { 0x0e, 0x15, 0x1c }, { 0x0e, 0x11, 0x1c }, 360 { 0x14, 0x14, 0x1c }, { 0x16, 0x14, 0x1c }, { 0x18, 0x14, 0x1c }, { 0x1a, 0x14, 0x1c }, 361 { 0x1c, 0x14, 0x1c }, { 0x1c, 0x14, 0x1a }, { 0x1c, 0x14, 0x18 }, { 0x1c, 0x14, 0x16 }, 362 { 0x1c, 0x14, 0x14 }, { 0x1c, 0x16, 0x14 }, { 0x1c, 0x18, 0x14 }, { 0x1c, 0x1a, 0x14 }, 363 { 0x1c, 0x1c, 0x14 }, { 0x1a, 0x1c, 0x14 }, { 0x18, 0x1c, 0x14 }, { 0x16, 0x1c, 0x14 }, 364 { 0x14, 0x1c, 0x14 }, { 0x14, 0x1c, 0x16 }, { 0x14, 0x1c, 0x18 }, { 0x14, 0x1c, 0x1a }, 365 { 0x14, 0x1c, 0x1c }, { 0x14, 0x1a, 0x1c }, { 0x14, 0x18, 0x1c }, { 0x14, 0x16, 0x1c }, 366 { 0x00, 0x00, 0x10 }, { 0x04, 0x00, 0x10 }, { 0x08, 0x00, 0x10 }, { 0x0c, 0x00, 0x10 }, 367 { 0x10, 0x00, 0x10 }, { 0x10, 0x00, 0x0c }, { 0x10, 0x00, 0x08 }, { 0x10, 0x00, 0x04 }, 368 { 0x10, 0x00, 0x00 }, { 0x10, 0x04, 0x00 }, { 0x10, 0x08, 0x00 }, { 0x10, 0x0c, 0x00 }, 369 { 0x10, 0x10, 0x00 }, { 0x0c, 0x10, 0x00 }, { 0x08, 0x10, 0x00 }, { 0x04, 0x10, 0x00 }, 370 { 0x00, 0x10, 0x00 }, { 0x00, 0x10, 0x04 }, { 0x00, 0x10, 0x08 }, { 0x00, 0x10, 0x0c }, 371 { 0x00, 0x10, 0x10 }, { 0x00, 0x0c, 0x10 }, { 0x00, 0x08, 0x10 }, { 0x00, 0x04, 0x10 }, 372 { 0x08, 0x08, 0x10 }, { 0x0a, 0x08, 0x10 }, { 0x0c, 0x08, 0x10 }, { 0x0e, 0x08, 0x10 }, 373 { 0x10, 0x08, 0x10 }, { 0x10, 0x08, 0x0e }, { 0x10, 0x08, 0x0c }, { 0x10, 0x08, 0x0a }, 374 { 0x10, 0x08, 0x08 }, { 0x10, 0x0a, 0x08 }, { 0x10, 0x0c, 0x08 }, { 0x10, 0x0e, 0x08 }, 375 { 0x10, 0x10, 0x08 }, { 0x0e, 0x10, 0x08 }, { 0x0c, 0x10, 0x08 }, { 0x0a, 0x10, 0x08 }, 376 { 0x08, 0x10, 0x08 }, { 0x08, 0x10, 0x0a }, { 0x08, 0x10, 0x0c }, { 0x08, 0x10, 0x0e }, 377 { 0x08, 0x10, 0x10 }, { 0x08, 0x0e, 0x10 }, { 0x08, 0x0c, 0x10 }, { 0x08, 0x0a, 0x10 }, 378 { 0x0b, 0x0b, 0x10 }, { 0x0c, 0x0b, 0x10 }, { 0x0d, 0x0b, 0x10 }, { 0x0f, 0x0b, 0x10 }, 379 { 0x10, 0x0b, 0x10 }, { 0x10, 0x0b, 0x0f }, { 0x10, 0x0b, 0x0d }, { 0x10, 0x0b, 0x0c }, 380 { 0x10, 0x0b, 0x0b }, { 0x10, 0x0c, 0x0b }, { 0x10, 0x0d, 0x0b }, { 0x10, 0x0f, 0x0b }, 381 { 0x10, 0x10, 0x0b }, { 0x0f, 0x10, 0x0b }, { 0x0d, 0x10, 0x0b }, { 0x0c, 0x10, 0x0b }, 382 { 0x0b, 0x10, 0x0b }, { 0x0b, 0x10, 0x0c }, { 0x0b, 0x10, 0x0d }, { 0x0b, 0x10, 0x0f }, 383 { 0x0b, 0x10, 0x10 }, { 0x0b, 0x0f, 0x10 }, { 0x0b, 0x0d, 0x10 }, { 0x0b, 0x0c, 0x10 }, 384 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 385 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 386}; 387 388/* extern. function */ 389extern void vASTOpenKey(ScrnInfoPtr pScrn); 390extern Bool bASTRegInit(ScrnInfoPtr pScrn); 391extern void vAST1000DisplayOn(ASTRecPtr pAST); 392extern void vAST1000DisplayOff(ASTRecPtr pAST); 393 394extern Bool bEnable2D(ScrnInfoPtr pScrn, ASTRecPtr pAST); 395extern void vDisable2D(ScrnInfoPtr pScrn, ASTRecPtr pAST); 396 397extern Bool bInitHWC(ScrnInfoPtr pScrn, ASTRecPtr pAST); 398 399/* Prototype type declaration*/ 400Bool ASTSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode); 401Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 402void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 403void vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 404void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 405void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 406void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 407void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 408Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 409BOOL bSetAST1180CRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 410BOOL bSetAST1180OffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 411BOOL bSetAST1180DCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 412BOOL bSetAST1180ExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 413void vInitChontelReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 414 415Bool 416ASTSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode) 417{ 418 ASTRecPtr pAST; 419 VBIOS_MODE_INFO vgamodeinfo; 420 421 pAST = ASTPTR(pScrn); 422 423 /* pre set mode */ 424 bGetAST1000VGAModeInfo(pScrn, mode, &vgamodeinfo); 425 426 /* set mode */ 427 if (pAST->jChipType == AST1180) 428 { 429 bInitAST1180(pScrn); 430 431 bSetAST1180CRTCReg(pScrn, mode, &vgamodeinfo); 432 bSetAST1180OffsetReg(pScrn, mode, &vgamodeinfo); 433 bSetAST1180DCLKReg(pScrn, mode, &vgamodeinfo); 434 bSetAST1180ExtReg(pScrn, mode, &vgamodeinfo); 435 436 vInitChontelReg(pScrn, mode, &vgamodeinfo); 437 } 438 else 439 { 440 vASTOpenKey(pScrn); 441 bASTRegInit(pScrn); 442 443 vSetStdReg(pScrn, mode, &vgamodeinfo); 444 vSetCRTCReg(pScrn, mode, &vgamodeinfo); 445 vSetOffsetReg(pScrn, mode, &vgamodeinfo); 446 vSetDCLKReg(pScrn, mode, &vgamodeinfo); 447 vSetExtReg(pScrn, mode, &vgamodeinfo); 448 vSetSyncReg(pScrn, mode, &vgamodeinfo); 449 bSetDACReg(pScrn, mode, &vgamodeinfo); 450 } 451 452 /* post set mode */ 453#ifdef Accel_2D 454 if (!pAST->noAccel) { 455 if (!bEnable2D(pScrn, pAST)) { 456 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Enable 2D failed\n"); 457 pAST->noAccel = TRUE; 458 } 459 } 460#endif 461#ifdef HWC 462 if (!pAST->noHWC) { 463 if (!bInitHWC(pScrn, pAST)) { 464 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Init HWC failed\n"); 465 pAST->noHWC = TRUE; 466 } 467 } 468#endif 469 vAST1000DisplayOn(pAST); 470 471 return (TRUE); 472} 473 474 475Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 476{ 477 ASTRecPtr pAST; 478 ULONG ulModeID, ulColorIndex, ulRefreshRate, ulRefreshRateIndex = 0; 479 ULONG ulHBorder, ulVBorder; 480 481 pAST = ASTPTR(pScrn); 482 483 switch (pScrn->bitsPerPixel) 484 { 485 case 8: 486 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[VGAModeIndex]; 487 ulColorIndex = VGAModeIndex-1; 488 break; 489 case 16: 490 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[HiCModeIndex]; 491 ulColorIndex = HiCModeIndex; 492 break; 493 case 24: 494 case 32: 495 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[TrueCModeIndex]; 496 ulColorIndex = TrueCModeIndex; 497 break; 498 default: 499 return (FALSE); 500 } 501 502 switch (mode->CrtcHDisplay) 503 { 504 case 640: 505 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res640x480Table[ulRefreshRateIndex]; 506 break; 507 case 800: 508 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res800x600Table[ulRefreshRateIndex]; 509 break; 510 case 1024: 511 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1024x768Table[ulRefreshRateIndex]; 512 break; 513 case 1280: 514 if (mode->CrtcVDisplay == 800) 515 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x800Table[ulRefreshRateIndex]; 516 else 517 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x1024Table[ulRefreshRateIndex]; 518 break; 519 case 1440: 520 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1440x900Table[ulRefreshRateIndex]; 521 break; 522 case 1600: 523 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1600x1200Table[ulRefreshRateIndex]; 524 break; 525 case 1680: 526 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1680x1050Table[ulRefreshRateIndex]; 527 break; 528 case 1920: 529 if (mode->CrtcVDisplay == 1080) 530 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1080Table[ulRefreshRateIndex]; 531 else 532 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1200Table[ulRefreshRateIndex]; 533 break; 534 default: 535 return (FALSE); 536 } 537 538 /* Get Proper Mode Index */ 539 ulRefreshRate = (mode->Clock * 1000) / (mode->HTotal * mode->VTotal); 540 541 while (pVGAModeInfo->pEnhTableEntry->ulRefreshRate < ulRefreshRate) 542 { 543 pVGAModeInfo->pEnhTableEntry++; 544 if ((pVGAModeInfo->pEnhTableEntry->ulRefreshRate > ulRefreshRate) || 545 (pVGAModeInfo->pEnhTableEntry->ulRefreshRate == 0xFF)) 546 { 547 pVGAModeInfo->pEnhTableEntry--; 548 break; 549 } 550 } 551 552 /* Update mode CRTC info */ 553 ulHBorder = (pVGAModeInfo->pEnhTableEntry->Flags & HBorder) ? 8:0; 554 ulVBorder = (pVGAModeInfo->pEnhTableEntry->Flags & VBorder) ? 8:0; 555 556 mode->CrtcHTotal = (int) pVGAModeInfo->pEnhTableEntry->HT; 557 mode->CrtcHBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder); 558 mode->CrtcHBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->HT - ulHBorder); 559 mode->CrtcHSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 560 + pVGAModeInfo->pEnhTableEntry->HFP); 561 mode->CrtcHSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 562 + pVGAModeInfo->pEnhTableEntry->HFP 563 + pVGAModeInfo->pEnhTableEntry->HSYNC); 564 565 mode->CrtcVTotal = (int) pVGAModeInfo->pEnhTableEntry->VT; 566 mode->CrtcVBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder); 567 mode->CrtcVBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->VT - ulVBorder); 568 mode->CrtcVSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 569 + pVGAModeInfo->pEnhTableEntry->VFP); 570 mode->CrtcVSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 571 + pVGAModeInfo->pEnhTableEntry->VFP 572 + pVGAModeInfo->pEnhTableEntry->VSYNC); 573 574 /* Write mode info to scratch */ 575 ulRefreshRateIndex = pVGAModeInfo->pEnhTableEntry->ulRefreshRateIndex; 576 ulModeID = pVGAModeInfo->pEnhTableEntry->ulModeID; 577 578 if (pAST->jChipType == AST1180) 579 { 580 /* TODO */ 581 } 582 else 583 { 584 SetIndexReg(CRTC_PORT, 0x8C, (UCHAR) ((ulColorIndex & 0x0F) << 4)); 585 SetIndexReg(CRTC_PORT, 0x8D, (UCHAR) (ulRefreshRateIndex & 0xFF)); 586 SetIndexReg(CRTC_PORT, 0x8E, (UCHAR) (ulModeID & 0xFF)); 587 588 /* NewModeInfo */ 589 SetIndexReg(CRTC_PORT, 0x91, 0xA8); /* signature */ 590 SetIndexReg(CRTC_PORT, 0x92, (UCHAR) (pScrn->bitsPerPixel) ); 591 SetIndexReg(CRTC_PORT, 0x93, (UCHAR) (mode->Clock / 1000) ); 592 SetIndexReg(CRTC_PORT, 0x94, (UCHAR) (mode->CrtcHDisplay) ); 593 SetIndexReg(CRTC_PORT, 0x95, (UCHAR) (mode->CrtcHDisplay >> 8) ); /* color depth */ 594 SetIndexReg(CRTC_PORT, 0x96, (UCHAR) (mode->CrtcVDisplay) ); 595 SetIndexReg(CRTC_PORT, 0x97, (UCHAR) (mode->CrtcVDisplay >> 8) ); /* color depth */ 596 597 } 598 599 return (TRUE); 600} 601 602void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 603{ 604 605 PVBIOS_STDTABLE_STRUCT pStdModePtr; 606 ASTRecPtr pAST; 607 ULONG i; 608 UCHAR jReg; 609 610 pStdModePtr = pVGAModeInfo->pStdTableEntry; 611 pAST = ASTPTR(pScrn); 612 613 /* Set Misc */ 614 jReg = pStdModePtr->MISC; 615 SetReg(MISC_PORT_WRITE,jReg); 616 617 /* Set Seq */ 618 SetIndexReg(SEQ_PORT,0x00, 0x03); 619 for (i=0; i<4; i++) 620 { 621 jReg = pStdModePtr->SEQ[i]; 622 if (!i) (jReg |= 0x20); /* display off */ 623 SetIndexReg(SEQ_PORT,(UCHAR) (i+1), jReg); 624 } 625 626 /* Set CRTC */ 627 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 628 for (i=0; i<25; i++) 629 { 630 jReg = pStdModePtr->CRTC[i]; 631 SetIndexReg(CRTC_PORT,(UCHAR) i, jReg); 632 } 633 634 /* Set AR */ 635 jReg = GetReg(INPUT_STATUS1_READ); 636 for (i=0; i<20; i++) 637 { 638 jReg = pStdModePtr->AR[i]; 639 SetReg(AR_PORT_WRITE, (UCHAR) i); 640 SetReg(AR_PORT_WRITE, jReg); 641 } 642 SetReg(AR_PORT_WRITE, 0x14); 643 SetReg(AR_PORT_WRITE, 0x00); 644 645 jReg = GetReg(INPUT_STATUS1_READ); 646 SetReg (AR_PORT_WRITE, 0x20); /* set POS */ 647 648 /* Set GR */ 649 for (i=0; i<9; i++) 650 { 651 jReg = pStdModePtr->GR[i]; 652 SetIndexReg(GR_PORT,(UCHAR) i, jReg); 653 654 } 655 656 657} 658 659void 660vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 661{ 662 ASTRecPtr pAST; 663 USHORT usTemp; 664 UCHAR jReg05, jReg07, jReg09, jRegAC, jRegAD, jRegAE; 665 666 pAST = ASTPTR(pScrn); 667 jReg05 = jReg07 = jReg09 = jRegAC = jRegAD = jRegAE = 0; 668 669 /* unlock CRTC */ 670 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 671 672 /* Horizontal Timing Programming */ 673 usTemp = (mode->CrtcHTotal >> 3) - 5; 674 if (usTemp & 0x100) jRegAC |= 0x01; /* HT D[8] */ 675 SetIndexRegMask(CRTC_PORT,0x00, 0x00, (UCHAR) usTemp); 676 usTemp = (mode->CrtcHDisplay >> 3) - 1; 677 if (usTemp & 0x100) jRegAC |= 0x04; /* HDE D[8] */ 678 SetIndexRegMask(CRTC_PORT,0x01, 0x00, (UCHAR) usTemp); 679 usTemp = (mode->CrtcHBlankStart >> 3) - 1; 680 if (usTemp & 0x100) jRegAC |= 0x10; /* HBS D[8] */ 681 SetIndexRegMask(CRTC_PORT,0x02, 0x00, (UCHAR) usTemp); 682 usTemp = ((mode->CrtcHBlankEnd >> 3) - 1) & 0x7F; 683 if (usTemp & 0x20) jReg05 |= 0x80; /* HBE D[5] */ 684 if (usTemp & 0x40) jRegAD |= 0x01; /* HBE D[6] */ 685 SetIndexRegMask(CRTC_PORT,0x03, 0xE0, (UCHAR) (usTemp & 0x1F)); 686 usTemp = (mode->CrtcHSyncStart >> 3 ) - 1; 687 if (usTemp & 0x100) jRegAC |= 0x40; /* HRS D[5] */ 688 SetIndexRegMask(CRTC_PORT,0x04, 0x00, (UCHAR) (usTemp)); 689 usTemp = ((mode->CrtcHSyncEnd >> 3 ) - 1) & 0x3F; 690 if (usTemp & 0x20) jRegAD |= 0x04; /* HRE D[5] */ 691 SetIndexRegMask(CRTC_PORT,0x05, 0x60, (UCHAR) ((usTemp & 0x1F) | jReg05)); 692 693 SetIndexRegMask(CRTC_PORT,0xAC, 0x00, (UCHAR) jRegAC); 694 SetIndexRegMask(CRTC_PORT,0xAD, 0x00, (UCHAR) jRegAD); 695 696 /* Vetical Timing Programming */ 697 usTemp = (mode->CrtcVTotal) - 2; 698 if (usTemp & 0x100) jReg07 |= 0x01; /* VT D[8] */ 699 if (usTemp & 0x200) jReg07 |= 0x20; 700 if (usTemp & 0x400) jRegAE |= 0x01; /* VT D[10] */ 701 SetIndexRegMask(CRTC_PORT,0x06, 0x00, (UCHAR) usTemp); 702 usTemp = (mode->CrtcVSyncStart) - 1; 703 if (usTemp & 0x100) jReg07 |= 0x04; /* VRS D[8] */ 704 if (usTemp & 0x200) jReg07 |= 0x80; /* VRS D[9] */ 705 if (usTemp & 0x400) jRegAE |= 0x08; /* VRS D[10] */ 706 SetIndexRegMask(CRTC_PORT,0x10, 0x00, (UCHAR) usTemp); 707 usTemp = ((mode->CrtcVSyncEnd) - 1) & 0x3F; 708 if (usTemp & 0x10) jRegAE |= 0x20; /* VRE D[4] */ 709 if (usTemp & 0x20) jRegAE |= 0x40; /* VRE D[5] */ 710 SetIndexRegMask(CRTC_PORT,0x11, 0x70, (UCHAR) (usTemp & 0x0F)); 711 usTemp = (mode->CrtcVDisplay) - 1; 712 if (usTemp & 0x100) jReg07 |= 0x02; /* VDE D[8] */ 713 if (usTemp & 0x200) jReg07 |= 0x40; /* VDE D[9] */ 714 if (usTemp & 0x400) jRegAE |= 0x02; /* VDE D[10] */ 715 SetIndexRegMask(CRTC_PORT,0x12, 0x00, (UCHAR) usTemp); 716 usTemp = (mode->CrtcVBlankStart) - 1; 717 if (usTemp & 0x100) jReg07 |= 0x08; /* VBS D[8] */ 718 if (usTemp & 0x200) jReg09 |= 0x20; /* VBS D[9] */ 719 if (usTemp & 0x400) jRegAE |= 0x04; /* VBS D[10] */ 720 SetIndexRegMask(CRTC_PORT,0x15, 0x00, (UCHAR) usTemp); 721 usTemp = (mode->CrtcVBlankEnd) - 1 ; 722 if (usTemp & 0x100) jRegAE |= 0x10; /* VBE D[8] */ 723 SetIndexRegMask(CRTC_PORT,0x16, 0x00, (UCHAR) usTemp); 724 725 SetIndexRegMask(CRTC_PORT,0x07, 0x00, (UCHAR) jReg07); 726 SetIndexRegMask(CRTC_PORT,0x09, 0xDF, (UCHAR) jReg09); 727 SetIndexRegMask(CRTC_PORT,0xAE, 0x00, (UCHAR) (jRegAE | 0x80)); /* disable line compare */ 728 729 /* lock CRTC */ 730 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x80); 731 732} 733 734void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 735{ 736 ASTRecPtr pAST; 737 USHORT usOffset; 738 739 pAST = ASTPTR(pScrn); 740 741 usOffset = pAST->VideoModeInfo.ScreenPitch >> 3; /* Unit: char */ 742 743 SetIndexReg(CRTC_PORT,0x13, (UCHAR) (usOffset & 0xFF)); 744 SetIndexReg(CRTC_PORT,0xB0, (UCHAR) ((usOffset >> 8) & 0x3F)); 745 746} 747 748void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 749{ 750 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 751 PVBIOS_DCLK_INFO pDCLKPtr; 752 ASTRecPtr pAST; 753 754 pAST = ASTPTR(pScrn); 755 756 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 757 if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) || (pAST->jChipType == AST2300)) 758 pDCLKPtr = &DCLKTable_AST2100[pEnhModePtr->DCLKIndex]; 759 else 760 pDCLKPtr = &DCLKTable[pEnhModePtr->DCLKIndex]; 761 762 SetIndexRegMask(CRTC_PORT,0xC0, 0x00, pDCLKPtr->Param1); 763 SetIndexRegMask(CRTC_PORT,0xC1, 0x00, pDCLKPtr->Param2); 764 SetIndexRegMask(CRTC_PORT,0xBB, 0x0F, (pDCLKPtr->Param3 & 0x80) | ((pDCLKPtr->Param3 & 0x03) << 4) ); 765 766} 767 768 769void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 770{ 771 772 ASTRecPtr pAST; 773 UCHAR jRegA0, jRegA3, jRegA8; 774 775 pAST = ASTPTR(pScrn); 776 777 jRegA0=jRegA3=jRegA8=0; 778 /* Mode Type Setting */ 779 switch (pScrn->bitsPerPixel) { 780 case 8: 781 jRegA0 = 0x70; 782 jRegA3 = 0x01; 783 jRegA8 = 0x00; 784 break; 785 case 15: 786 case 16: 787 jRegA0 = 0x70; 788 jRegA3 = 0x04; 789 jRegA8 = 0x02; 790 break; 791 case 32: 792 jRegA0 = 0x70; 793 jRegA3 = 0x08; 794 jRegA8 = 0x02; 795 break; 796 } 797 SetIndexRegMask(CRTC_PORT,0xA0, 0x8F, (UCHAR) jRegA0); 798 SetIndexRegMask(CRTC_PORT,0xA3, 0xF0, (UCHAR) jRegA3); 799 SetIndexRegMask(CRTC_PORT,0xA8, 0xFD, (UCHAR) jRegA8); 800 801 /* Set Threshold */ 802 if (pAST->jChipType == AST2300) 803 { 804 SetIndexReg(CRTC_PORT,0xA7, 0x78); 805 SetIndexReg(CRTC_PORT,0xA6, 0x60); 806 } 807 else if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) ) 808 { 809 SetIndexReg(CRTC_PORT,0xA7, 0x3F); 810 SetIndexReg(CRTC_PORT,0xA6, 0x2F); 811 } 812 else 813 { 814 SetIndexReg(CRTC_PORT,0xA7, 0x2F); 815 SetIndexReg(CRTC_PORT,0xA6, 0x1F); 816 } 817 818} 819 820void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 821{ 822 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 823 ASTRecPtr pAST; 824 UCHAR jReg; 825 826 pAST = ASTPTR(pScrn); 827 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 828 829 jReg = GetReg(MISC_PORT_READ); 830 jReg |= (UCHAR) (pEnhModePtr->Flags & SyncNN); 831 SetReg(MISC_PORT_WRITE,jReg); 832 833} 834 835Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 836{ 837 PVBIOS_DAC_INFO pDACPtr; 838 ASTRecPtr pAST; 839 ULONG i, ulDACNumber; 840 UCHAR DACR, DACG, DACB; 841 842 pAST = ASTPTR(pScrn); 843 844 switch (pScrn->bitsPerPixel) 845 { 846 case 8: 847 ulDACNumber = DAC_NUM_VGA; 848 pDACPtr = (PVBIOS_DAC_INFO) &DAC_VGA[0]; 849 break; 850 default: 851 return (FALSE); 852 } 853 854 for (i=0; i<ulDACNumber; i++) 855 { 856 DACR = pDACPtr->DACR; 857 DACG = pDACPtr->DACG; 858 DACB = pDACPtr->DACB; 859 860 VGA_LOAD_PALETTE_INDEX (i, DACR, DACG, DACB); 861 862 pDACPtr++; 863 } 864 865 return (TRUE); 866 867} 868 869ULONG AST1180DCLKTable [] = { 870 0x0008676b, /* 00: VCLK25_175 */ 871 0x00086342, /* 01: VCLK28_322 */ 872 0x00086568, /* 02: VCLK31_5 */ 873 0x00082118, /* 03: VCLK36 */ 874 0x0008232e, /* 04: VCLK40 */ 875 0x000c256d, /* 05: VCLK49_5 */ 876 0x00082016, /* 06: VCLK50 */ 877 0x000c0010, /* 07: VCLK56_25 */ 878 0x000c0332, /* 08: VCLK65 */ 879 0x00080010, /* 09: VCLK75 */ 880 0x000c033d, /* 0A: VCLK78_75 */ 881 0x000c0568, /* 0B: VCLK94_5 */ 882 0x00040118, /* 0C: VCLK108 */ 883 0x00040334, /* 0D: VCLK135 */ 884 0x0004033d, /* 0E: VCLK157_5 */ 885 0x00040018, /* 0F: VCLK162 */ 886 0x00040123, /* 10: VCLK154 */ 887 0x000c0669, /* 11: VCLK83_5 */ 888 0x0004074b, /* 12: VCLK106_5 */ 889 0x0004022d, /* 13: VCLK146_25 */ 890 0x00040769, /* 14: VCLK148_5 */ 891}; 892 893BOOL bSetAST1180CRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 894{ 895 ASTRecPtr pAST = ASTPTR(pScrn); 896 897 ULONG HTIndex, HRIndex, VTIndex, VRIndex; 898 ULONG HT, HDE, HBS, HBE, HRS, HRE; 899 ULONG VT, VDE, VBS, VBE, VRS, VRE; 900 ULONG HT2, HDE2, HRS2, HRE2; 901 ULONG VT2, VDE2, VRS2, VRE2; 902 903 /* Reg. Index Select */ 904 { 905 HTIndex = AST1180_VGA1_HTREG; 906 HRIndex = AST1180_VGA1_HRREG; 907 VTIndex = AST1180_VGA1_VTREG; 908 VRIndex = AST1180_VGA1_VRREG; 909 } 910 911 /* Get CRTC Info */ 912 HT = mode->CrtcHTotal; 913 HDE= mode->CrtcHDisplay; 914 HBS= mode->CrtcHBlankStart; 915 HBE= mode->CrtcHBlankEnd; 916 HRS= mode->CrtcHSyncStart; 917 HRE= mode->CrtcHSyncEnd; 918 VT = mode->CrtcVTotal; 919 VDE= mode->CrtcVDisplay; 920 VBS= mode->CrtcVBlankStart; 921 VBE= mode->CrtcVBlankEnd; 922 VRS= mode->CrtcVSyncStart; 923 VRE= mode->CrtcVSyncEnd; 924 925 /* Calculate CRTC Reg Setting */ 926 HT2 = HT - 1; 927 HDE2 = HDE - 1; 928 HRS2 = HRS - 1; 929 HRE2 = HRE - 1; 930 VT2 = VT - 1; 931 VDE2 = VDE - 1; 932 VRS2 = VRS - 1; 933 VRE2 = VRE - 1; 934 935 /* Write Reg */ 936 WriteAST1180SOC(AST1180_GFX_BASE + HTIndex, (ULONG)(HDE2 << 16) | (ULONG) (HT2)); 937 WriteAST1180SOC(AST1180_GFX_BASE + HRIndex, (ULONG)(HRE2 << 16) | (ULONG) (HRS2)); 938 WriteAST1180SOC(AST1180_GFX_BASE + VTIndex, (ULONG)(VDE2 << 16) | (ULONG) (VT2)); 939 WriteAST1180SOC(AST1180_GFX_BASE + VRIndex, (ULONG)(VRE2 << 16) | (ULONG) (VRS2)); 940 941 return (TRUE); 942 943} /* bSetAST1180CRTCReg */ 944 945BOOL bSetAST1180OffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 946{ 947 ASTRecPtr pAST = ASTPTR(pScrn); 948 ULONG ulOffset, ulTermalCount; 949 950 ulOffset = pAST->VideoModeInfo.ScreenPitch; 951 ulTermalCount = (pAST->VideoModeInfo.ScreenPitch + 7) >> 3; 952 953 /* Write Reg */ 954 WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_OFFSET, (ULONG) (ulTermalCount << 16) | (ULONG) (ulOffset)); 955 956 return (TRUE); 957 958} /* bSetAST1180OffsetReg */ 959 960BOOL bSetAST1180DCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 961{ 962 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 963 ASTRecPtr pAST = ASTPTR(pScrn); 964 ULONG ulDCLK; 965 966 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 967 ulDCLK = AST1180DCLKTable[pEnhModePtr->DCLKIndex]; 968 if (pEnhModePtr->Flags & HalfDCLK) 969 ulDCLK |= 0x00400000; /* D[22]: div by 2 */ 970 WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_PLL, ulDCLK); 971 972 return (TRUE); 973} 974 975BOOL bSetAST1180ExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 976{ 977 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 978 ASTRecPtr pAST = ASTPTR(pScrn); 979 980 ULONG ulCtlRegIndex, ulCtlReg; /* enable display */ 981 ULONG ulCtlReg2Index, ulCtlReg2 = 0x80; /* single edge */ 982 ULONG ulThresholdRegIndex ; /* Threshold */ 983 ULONG ulStartAddressIndex; /* ulStartAddress */ 984 ULONG ulStartAddress = pAST->ulVRAMBase; 985 986 /* Reg. Index Select */ 987 { 988 ulCtlRegIndex = AST1180_VGA1_CTRL; 989 ulCtlReg2Index = AST1180_VGA1_CTRL2; 990 ulThresholdRegIndex = AST1180_VGA1_THRESHOLD; 991 ulStartAddressIndex = AST1180_VGA1_STARTADDR; 992 } 993 994 /* Mode Type Setting */ 995 ulCtlReg = 0x30000000; 996 { 997 switch (pScrn->bitsPerPixel) { 998 case 15: 999 case 16: 1000 ulCtlReg |= 0x100001; /* RGB565, SCREEN OFF, ENABLE */ 1001 break; 1002 case 32: 1003 ulCtlReg |= 0x100101; /* XRGB8888, SCREEN OFF, ENABLE */ 1004 break; 1005 } 1006 } 1007 1008 /* Polarity */ 1009 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1010 ulCtlReg |= (ULONG) (pEnhModePtr->Flags & SyncNN) << 10; 1011 1012 /* Single/Dual Edge */ 1013 ulCtlReg2 |= 0x40; /* dual-edge */ 1014 1015 /* Write Reg */ 1016 WriteAST1180SOC(AST1180_GFX_BASE + ulStartAddressIndex, ulStartAddress); 1017 WriteAST1180SOC(AST1180_GFX_BASE + ulThresholdRegIndex, ((ULONG) CRT_HIGH_THRESHOLD_VALUE << 8) | (ULONG) (CRT_LOW_THRESHOLD_VALUE)); 1018 WriteAST1180SOC(AST1180_GFX_BASE + ulCtlReg2Index, ulCtlReg2); 1019 WriteAST1180SOC(AST1180_GFX_BASE + ulCtlRegIndex, ulCtlReg); 1020 1021 return (TRUE); 1022 1023} /* bSetAST1180ExtReg */ 1024 1025#define I2C_BASE_AST1180 0x80fcb000 1026#define I2C_DEVICEADDR_AST1180 0x0EC /* slave addr */ 1027 1028void SetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex, UCHAR jData ) 1029{ 1030 ULONG ulData, ulI2CAddr, ulI2CPortBase; 1031 ULONG retry; 1032 1033 { 1034 ulI2CPortBase = I2C_BASE_AST1180 + 0x40 * jChannel; 1035 ulI2CAddr = I2C_DEVICEADDR_AST1180; 1036 } 1037 1038 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x00); 1039 WriteAST1180SOC(ulI2CPortBase + 0x04, 0x77743355); 1040 WriteAST1180SOC(ulI2CPortBase + 0x08, 0x0); 1041 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1042 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x1); 1043 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xAF); 1044 WriteAST1180SOC(ulI2CPortBase + 0x20, ulI2CAddr); 1045 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x03); 1046 retry = 0; 1047 do { 1048 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1049 usleep(10); 1050 if (retry++ > 1000) 1051 goto Exit_SetChrontelReg; 1052 } while (!(ulData & 0x01)); 1053 1054 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1055 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jIndex); 1056 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1057 do { 1058 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1059 } while (!(ulData & 0x01)); 1060 1061 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1062 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jData); 1063 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1064 do { 1065 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1066 } while (!(ulData & 0x01)); 1067 1068 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1069 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xBF); 1070 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x20); 1071 do { 1072 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1073 } while (!(ulData & 0x10)); 1074 1075 ReadAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1076 ulData &= 0xffffffef; 1077 WriteAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1078 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1079 1080Exit_SetChrontelReg: 1081 ; 1082} 1083 1084UCHAR GetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex) 1085{ 1086 ULONG ulData, ulI2CAddr, ulI2CPortBase; 1087 UCHAR jData; 1088 ULONG retry; 1089 1090 { 1091 ulI2CPortBase = I2C_BASE_AST1180 + 0x40 * jChannel; 1092 ulI2CAddr = I2C_DEVICEADDR_AST1180; 1093 } 1094 1095 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x00); 1096 WriteAST1180SOC(ulI2CPortBase + 0x04, 0x77743355); 1097 WriteAST1180SOC(ulI2CPortBase + 0x08, 0x0); 1098 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1099 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x1); 1100 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xAF); 1101 WriteAST1180SOC(ulI2CPortBase + 0x20, ulI2CAddr); 1102 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x03); 1103 retry = 0; 1104 do { 1105 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1106 usleep(10); 1107 if (retry++ > 1000) 1108 return 0; 1109 } while (!(ulData & 0x01)); 1110 1111 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1112 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jIndex); 1113 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1114 do { 1115 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1116 } while (!(ulData & 0x01)); 1117 1118 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1119 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) (ulI2CAddr + 1) ); 1120 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x1B); 1121 do { 1122 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1123 } while (!(ulData & 0x04)); 1124 1125 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1126 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xBF); 1127 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x20); 1128 do { 1129 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1130 } while (!(ulData & 0x10)); 1131 1132 ReadAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1133 ulData &= 0xffffffef; 1134 WriteAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1135 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1136 1137 ReadAST1180SOC(ulI2CPortBase + 0x20, ulData); 1138 jData = (UCHAR) ((ulData & 0xFF00) >> 8); 1139 1140 return (jData); 1141} 1142 1143void vInitChontelReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1144{ 1145 1146 PVBIOS_ENHTABLE_STRUCT pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1147 ASTRecPtr pAST = ASTPTR(pScrn); 1148 ULONG ulDCLK = 65; /* todo */ 1149 UCHAR jReg; 1150 1151 jReg = GetChrontelReg(pAST, 1, 0x4A); /* get vendor id */ 1152 if (jReg == 0x95) 1153 { 1154 jReg = GetChrontelReg(pAST, 1, 0x20); /* DVI/D-Sub */ 1155 if (jReg & 0x20) /* DVI */ 1156 { 1157 1158 /* DVI PLL Filter */ 1159 if (ulDCLK > 65) 1160 { 1161 SetChrontelReg(pAST, 1, 0x33, 0x06); 1162 SetChrontelReg(pAST, 1, 0x34, 0x26); 1163 SetChrontelReg(pAST, 1, 0x36, 0xA0); 1164 } 1165 else 1166 { 1167 SetChrontelReg(pAST, 1, 0x33, 0x08); 1168 SetChrontelReg(pAST, 1, 0x34, 0x16); 1169 SetChrontelReg(pAST, 1, 0x36, 0x60); 1170 } 1171 1172 SetChrontelReg(pAST, 1, 0x49, 0xc0); 1173 } 1174 else /* D-Sub */ 1175 { 1176 1177 SetChrontelReg(pAST, 1, 0x21, 0x09); 1178 SetChrontelReg(pAST, 1, 0x49, 0x00); 1179 SetChrontelReg(pAST, 1, 0x56, 0x00); 1180 } 1181 } 1182 1183} 1184 1185