ast_vgatool.h revision 15fb4814
115fb4814Smrg/* 215fb4814Smrg * Copyright (c) 2005 ASPEED Technology Inc. 315fb4814Smrg * 415fb4814Smrg * Permission to use, copy, modify, distribute, and sell this software and its 515fb4814Smrg * documentation for any purpose is hereby granted without fee, provided that 615fb4814Smrg * the above copyright notice appear in all copies and that both that 715fb4814Smrg * copyright notice and this permission notice appear in supporting 815fb4814Smrg * documentation, and that the name of the authors not be used in 915fb4814Smrg * advertising or publicity pertaining to distribution of the software without 1015fb4814Smrg * specific, written prior permission. The authors makes no representations 1115fb4814Smrg * about the suitability of this software for any purpose. It is provided 1215fb4814Smrg * "as is" without express or implied warranty. 1315fb4814Smrg * 1415fb4814Smrg * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 1515fb4814Smrg * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 1615fb4814Smrg * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 1715fb4814Smrg * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 1815fb4814Smrg * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 1915fb4814Smrg * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 2015fb4814Smrg * PERFORMANCE OF THIS SOFTWARE. 2115fb4814Smrg */ 2215fb4814Smrg 2315fb4814Smrg/* VRAM Size Definition */ 2415fb4814Smrg#define VIDEOMEM_SIZE_08M 0x00800000 2515fb4814Smrg#define VIDEOMEM_SIZE_16M 0x01000000 2615fb4814Smrg#define VIDEOMEM_SIZE_32M 0x02000000 2715fb4814Smrg#define VIDEOMEM_SIZE_64M 0x04000000 2815fb4814Smrg 2915fb4814Smrg#define AR_PORT_WRITE (pAST->RelocateIO + 0x40) 3015fb4814Smrg#define MISC_PORT_WRITE (pAST->RelocateIO + 0x42) 3115fb4814Smrg#define SEQ_PORT (pAST->RelocateIO + 0x44) 3215fb4814Smrg#define DAC_INDEX_WRITE (pAST->RelocateIO + 0x48) 3315fb4814Smrg#define DAC_DATA (pAST->RelocateIO + 0x49) 3415fb4814Smrg#define GR_PORT (pAST->RelocateIO + 0x4E) 3515fb4814Smrg#define CRTC_PORT (pAST->RelocateIO + 0x54) 3615fb4814Smrg#define INPUT_STATUS1_READ (pAST->RelocateIO + 0x5A) 3715fb4814Smrg 3815fb4814Smrg#define GetReg(base) inb(base) 3915fb4814Smrg#define SetReg(base,val) outb(base,val) 4015fb4814Smrg#define GetIndexReg(base,index,val) do { \ 4115fb4814Smrg outb(base,index); \ 4215fb4814Smrg val = inb(base+1); \ 4315fb4814Smrg } while (0) 4415fb4814Smrg#define SetIndexReg(base,index, val) do { \ 4515fb4814Smrg outb(base,index); \ 4615fb4814Smrg outb(base+1,val); \ 4715fb4814Smrg } while (0) 4815fb4814Smrg#define GetIndexRegMask(base,index, and, val) do { \ 4915fb4814Smrg outb(base,index); \ 5015fb4814Smrg val = (inb(base+1) & and); \ 5115fb4814Smrg } while (0) 5215fb4814Smrg#define SetIndexRegMask(base,index, and, val) do { \ 5315fb4814Smrg UCHAR __Temp; \ 5415fb4814Smrg outb(base,index); \ 5515fb4814Smrg __Temp = (inb((base)+1)&(and))|(val); \ 5615fb4814Smrg SetIndexReg(base,index,__Temp); \ 5715fb4814Smrg } while (0) 5815fb4814Smrg 5915fb4814Smrg#define VGA_LOAD_PALETTE_INDEX(index, red, green, blue) \ 6015fb4814Smrg{ \ 6115fb4814Smrg UCHAR __junk; \ 6215fb4814Smrg SetReg(DAC_INDEX_WRITE,(UCHAR)(index)); \ 6315fb4814Smrg __junk = GetReg(SEQ_PORT); \ 6415fb4814Smrg SetReg(DAC_DATA,(UCHAR)(red)); \ 6515fb4814Smrg __junk = GetReg(SEQ_PORT); \ 6615fb4814Smrg SetReg(DAC_DATA,(UCHAR)(green)); \ 6715fb4814Smrg __junk = GetReg(SEQ_PORT); \ 6815fb4814Smrg SetReg(DAC_DATA,(UCHAR)(blue)); \ 6915fb4814Smrg __junk = GetReg(SEQ_PORT); \ 7015fb4814Smrg} 71