evergreen_reg_auto.h revision de2362d3
1/* 2 * Evergreen Register documentation 3 * 4 * Copyright (C) 2010 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef _EVERGREEN_REG_AUTO_H 25#define _EVERGREEN_REG_AUTO_H 26 27enum { 28 29 VGT_VTX_VECT_EJECT_REG = 0x000088b0, 30 PRIM_COUNT_mask = 0x3ff << 0, 31 PRIM_COUNT_shift = 0, 32 VGT_LAST_COPY_STATE = 0x000088c0, 33 SRC_STATE_ID_mask = 0x07 << 0, 34 SRC_STATE_ID_shift = 0, 35 DST_STATE_ID_mask = 0x07 << 16, 36 DST_STATE_ID_shift = 16, 37 VGT_CACHE_INVALIDATION = 0x000088c4, 38 CACHE_INVALIDATION_mask = 0x03 << 0, 39 CACHE_INVALIDATION_shift = 0, 40 VC_ONLY = 0x00, 41 TC_ONLY = 0x01, 42 VC_AND_TC = 0x02, 43 VS_NO_EXTRA_BUFFER_bit = 1 << 5, 44 AUTO_INVLD_EN_mask = 0x03 << 6, 45 AUTO_INVLD_EN_shift = 6, 46 VGT_GS_VERTEX_REUSE = 0x000088d4, 47 VERT_REUSE_mask = 0x1f << 0, 48 VERT_REUSE_shift = 0, 49 VGT_CNTL_STATUS = 0x000088f0, 50 VGT_OUT_INDX_BUSY_bit = 1 << 0, 51 VGT_OUT_BUSY_bit = 1 << 1, 52 VGT_PT_BUSY_bit = 1 << 2, 53 VGT_TE_BUSY_bit = 1 << 3, 54 VGT_VR_BUSY_bit = 1 << 4, 55 VGT_GRP_BUSY_bit = 1 << 5, 56 VGT_DMA_REQ_BUSY_bit = 1 << 6, 57 VGT_DMA_BUSY_bit = 1 << 7, 58 VGT_GS_BUSY_bit = 1 << 8, 59 VGT_HS_BUSY_bit = 1 << 9, 60 VGT_TE11_BUSY_bit = 1 << 10, 61 VGT_BUSY_bit = 1 << 11, 62 VGT_PRIMITIVE_TYPE = 0x00008958, 63 VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask = 0x3f << 0, 64 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift = 0, 65 DI_PT_NONE = 0x00, 66 DI_PT_POINTLIST = 0x01, 67 DI_PT_LINELIST = 0x02, 68 DI_PT_LINESTRIP = 0x03, 69 DI_PT_TRILIST = 0x04, 70 DI_PT_TRIFAN = 0x05, 71 DI_PT_TRISTRIP = 0x06, 72 DI_PT_UNUSED_0 = 0x07, 73 DI_PT_UNUSED_1 = 0x08, 74 DI_PT_PATCH = 0x09, 75 DI_PT_LINELIST_ADJ = 0x0a, 76 DI_PT_LINESTRIP_ADJ = 0x0b, 77 DI_PT_TRILIST_ADJ = 0x0c, 78 DI_PT_TRISTRIP_ADJ = 0x0d, 79 DI_PT_UNUSED_3 = 0x0e, 80 DI_PT_UNUSED_4 = 0x0f, 81 DI_PT_TRI_WITH_WFLAGS = 0x10, 82 DI_PT_RECTLIST = 0x11, 83 DI_PT_LINELOOP = 0x12, 84 DI_PT_QUADLIST = 0x13, 85 DI_PT_QUADSTRIP = 0x14, 86 DI_PT_POLYGON = 0x15, 87 DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, 88 DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, 89 DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, 90 DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, 91 DI_PT_2D_FILL_RECT_LIST = 0x1a, 92 DI_PT_2D_LINE_STRIP = 0x1b, 93 DI_PT_2D_TRI_STRIP = 0x1c, 94 VGT_INDEX_TYPE = 0x0000895c, 95 INDEX_TYPE_mask = 0x03 << 0, 96 INDEX_TYPE_shift = 0, 97 DI_INDEX_SIZE_16_BIT = 0x00, 98 DI_INDEX_SIZE_32_BIT = 0x01, 99 VGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x00008960, 100 VGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x00008964, 101 VGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x00008968, 102 VGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x0000896c, 103 VGT_NUM_INDICES = 0x00008970, 104 VGT_NUM_INSTANCES = 0x00008974, 105 PA_CL_CNTL_STATUS = 0x00008a10, 106 CL_BUSY_bit = 1 << 31, 107 PA_CL_ENHANCE = 0x00008a14, 108 CLIP_VTX_REORDER_ENA_bit = 1 << 0, 109 NUM_CLIP_SEQ_mask = 0x03 << 1, 110 NUM_CLIP_SEQ_shift = 1, 111 CLIPPED_PRIM_SEQ_STALL_bit = 1 << 3, 112 VE_NAN_PROC_DISABLE_bit = 1 << 4, 113 PA_SU_CNTL_STATUS = 0x00008a50, 114 SU_BUSY_bit = 1 << 31, 115 PA_SU_LINE_STIPPLE_VALUE = 0x00008a60, 116 LINE_STIPPLE_VALUE_mask = 0xffffff << 0, 117 LINE_STIPPLE_VALUE_shift = 0, 118 PA_SC_LINE_STIPPLE_STATE = 0x00008b10, 119 CURRENT_PTR_mask = 0x0f << 0, 120 CURRENT_PTR_shift = 0, 121 CURRENT_COUNT_mask = 0xff << 8, 122 CURRENT_COUNT_shift = 8, 123 SQ_CONFIG = 0x00008c00, 124 VC_ENABLE_bit = 1 << 0, 125 EXPORT_SRC_C_bit = 1 << 1, 126 CS_PRIO_mask = 0x03 << 18, 127 CS_PRIO_shift = 18, 128 LS_PRIO_mask = 0x03 << 20, 129 LS_PRIO_shift = 20, 130 HS_PRIO_mask = 0x03 << 22, 131 HS_PRIO_shift = 22, 132 PS_PRIO_mask = 0x03 << 24, 133 PS_PRIO_shift = 24, 134 VS_PRIO_mask = 0x03 << 26, 135 VS_PRIO_shift = 26, 136 GS_PRIO_mask = 0x03 << 28, 137 GS_PRIO_shift = 28, 138 ES_PRIO_mask = 0x03 << 30, 139 ES_PRIO_shift = 30, 140 SQ_GPR_RESOURCE_MGMT_1 = 0x00008c04, 141 NUM_PS_GPRS_mask = 0xff << 0, 142 NUM_PS_GPRS_shift = 0, 143 NUM_VS_GPRS_mask = 0xff << 16, 144 NUM_VS_GPRS_shift = 16, 145 NUM_CLAUSE_TEMP_GPRS_mask = 0x0f << 28, 146 NUM_CLAUSE_TEMP_GPRS_shift = 28, 147 SQ_GPR_RESOURCE_MGMT_2 = 0x00008c08, 148 NUM_GS_GPRS_mask = 0xff << 0, 149 NUM_GS_GPRS_shift = 0, 150 NUM_ES_GPRS_mask = 0xff << 16, 151 NUM_ES_GPRS_shift = 16, 152 SQ_GPR_RESOURCE_MGMT_3 = 0x00008c0c, 153 NUM_HS_GPRS_mask = 0xff << 0, 154 NUM_HS_GPRS_shift = 0, 155 NUM_LS_GPRS_mask = 0xff << 16, 156 NUM_LS_GPRS_shift = 16, 157 SQ_GLOBAL_GPR_RESOURCE_MGMT_1 = 0x00008c10, 158 PS_GGPR_BASE_mask = 0xff << 0, 159 PS_GGPR_BASE_shift = 0, 160 VS_GGPR_BASE_mask = 0xff << 8, 161 VS_GGPR_BASE_shift = 8, 162 GS_GGPR_BASE_mask = 0xff << 16, 163 GS_GGPR_BASE_shift = 16, 164 ES_GGPR_BASE_mask = 0xff << 24, 165 ES_GGPR_BASE_shift = 24, 166 SQ_GLOBAL_GPR_RESOURCE_MGMT_2 = 0x00008c14, 167 HS_GGPR_BASE_mask = 0xff << 0, 168 HS_GGPR_BASE_shift = 0, 169 LS_GGPR_BASE_mask = 0xff << 8, 170 LS_GGPR_BASE_shift = 8, 171 CS_GGPR_BASE_mask = 0xff << 16, 172 CS_GGPR_BASE_shift = 16, 173 SQ_THREAD_RESOURCE_MGMT = 0x00008c18, 174 NUM_PS_THREADS_mask = 0xff << 0, 175 NUM_PS_THREADS_shift = 0, 176 NUM_VS_THREADS_mask = 0xff << 8, 177 NUM_VS_THREADS_shift = 8, 178 NUM_GS_THREADS_mask = 0xff << 16, 179 NUM_GS_THREADS_shift = 16, 180 NUM_ES_THREADS_mask = 0xff << 24, 181 NUM_ES_THREADS_shift = 24, 182 SQ_THREAD_RESOURCE_MGMT_2 = 0x00008c1c, 183 NUM_HS_THREADS_mask = 0xff << 0, 184 NUM_HS_THREADS_shift = 0, 185 NUM_LS_THREADS_mask = 0xff << 8, 186 NUM_LS_THREADS_shift = 8, 187 SQ_STACK_RESOURCE_MGMT_1 = 0x00008c20, 188 NUM_PS_STACK_ENTRIES_mask = 0xfff << 0, 189 NUM_PS_STACK_ENTRIES_shift = 0, 190 NUM_VS_STACK_ENTRIES_mask = 0xfff << 16, 191 NUM_VS_STACK_ENTRIES_shift = 16, 192 SQ_STACK_RESOURCE_MGMT_2 = 0x00008c24, 193 NUM_GS_STACK_ENTRIES_mask = 0xfff << 0, 194 NUM_GS_STACK_ENTRIES_shift = 0, 195 NUM_ES_STACK_ENTRIES_mask = 0xfff << 16, 196 NUM_ES_STACK_ENTRIES_shift = 16, 197 SQ_STACK_RESOURCE_MGMT_3 = 0x00008c28, 198 NUM_HS_STACK_ENTRIES_mask = 0xfff << 0, 199 NUM_HS_STACK_ENTRIES_shift = 0, 200 NUM_LS_STACK_ENTRIES_mask = 0xfff << 16, 201 NUM_LS_STACK_ENTRIES_shift = 16, 202 SQ_ESGS_RING_BASE = 0x00008c40, 203 SQ_ESGS_RING_SIZE = 0x00008c44, 204 SQ_GSVS_RING_BASE = 0x00008c48, 205 SQ_GSVS_RING_SIZE = 0x00008c4c, 206 SQ_ESTMP_RING_BASE = 0x00008c50, 207 SQ_ESTMP_RING_SIZE = 0x00008c54, 208 SQ_GSTMP_RING_BASE = 0x00008c58, 209 SQ_GSTMP_RING_SIZE = 0x00008c5c, 210 SQ_VSTMP_RING_BASE = 0x00008c60, 211 SQ_VSTMP_RING_SIZE = 0x00008c64, 212 SQ_PSTMP_RING_BASE = 0x00008c68, 213 SQ_PSTMP_RING_SIZE = 0x00008c6c, 214 SQ_CONST_MEM_BASE = 0x00008df8, 215 SQ_ALU_WORD1_OP3 = 0x00008dfc, 216 SRC2_SEL_mask = 0x1ff << 0, 217 SRC2_SEL_shift = 0, 218 SQ_ALU_SRC_LDS_OQ_A = 0xdb, 219 SQ_ALU_SRC_LDS_OQ_B = 0xdc, 220 SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, 221 SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, 222 SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, 223 SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, 224 SQ_ALU_SRC_TIME_HI = 0xe3, 225 SQ_ALU_SRC_TIME_LO = 0xe4, 226 SQ_ALU_SRC_MASK_HI = 0xe5, 227 SQ_ALU_SRC_MASK_LO = 0xe6, 228 SQ_ALU_SRC_HW_WAVE_ID = 0xe7, 229 SQ_ALU_SRC_SIMD_ID = 0xe8, 230 SQ_ALU_SRC_SE_ID = 0xe9, 231 SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, 232 SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, 233 SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, 234 SQ_ALU_SRC_HW_ALU_ODD = 0xed, 235 SQ_ALU_SRC_LOOP_IDX = 0xee, 236 SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, 237 SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, 238 SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, 239 SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, 240 SQ_ALU_SRC_1_DBL_L = 0xf4, 241 SQ_ALU_SRC_1_DBL_M = 0xf5, 242 SQ_ALU_SRC_0_5_DBL_L = 0xf6, 243 SQ_ALU_SRC_0_5_DBL_M = 0xf7, 244 SQ_ALU_SRC_0 = 0xf8, 245 SQ_ALU_SRC_1 = 0xf9, 246 SQ_ALU_SRC_1_INT = 0xfa, 247 SQ_ALU_SRC_M_1_INT = 0xfb, 248 SQ_ALU_SRC_0_5 = 0xfc, 249 SQ_ALU_SRC_LITERAL = 0xfd, 250 SQ_ALU_SRC_PV = 0xfe, 251 SQ_ALU_SRC_PS = 0xff, 252 SRC2_REL_bit = 1 << 9, 253 SRC2_CHAN_mask = 0x03 << 10, 254 SRC2_CHAN_shift = 10, 255 SQ_CHAN_X = 0x00, 256 SQ_CHAN_Y = 0x01, 257 SQ_CHAN_Z = 0x02, 258 SQ_CHAN_W = 0x03, 259 SRC2_NEG_bit = 1 << 12, 260 SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, 261 SQ_ALU_WORD1_OP3__ALU_INST_shift = 13, 262 SQ_OP3_INST_BFE_UINT = 0x04, 263 SQ_OP3_INST_BFE_INT = 0x05, 264 SQ_OP3_INST_BFI_INT = 0x06, 265 SQ_OP3_INST_FMA = 0x07, 266 SQ_OP3_INST_CNDNE_64 = 0x09, 267 SQ_OP3_INST_FMA_64 = 0x0a, 268 SQ_OP3_INST_LERP_UINT = 0x0b, 269 SQ_OP3_INST_BIT_ALIGN_INT = 0x0c, 270 SQ_OP3_INST_BYTE_ALIGN_INT = 0x0d, 271 SQ_OP3_INST_SAD_ACCUM_UINT = 0x0e, 272 SQ_OP3_INST_SAD_ACCUM_HI_UINT = 0x0f, 273 SQ_OP3_INST_MULADD_UINT24 = 0x10, 274 SQ_OP3_INST_LDS_IDX_OP = 0x11, 275 SQ_OP3_INST_MULADD = 0x14, 276 SQ_OP3_INST_MULADD_M2 = 0x15, 277 SQ_OP3_INST_MULADD_M4 = 0x16, 278 SQ_OP3_INST_MULADD_D2 = 0x17, 279 SQ_OP3_INST_MULADD_IEEE = 0x18, 280 SQ_OP3_INST_CNDE = 0x19, 281 SQ_OP3_INST_CNDGT = 0x1a, 282 SQ_OP3_INST_CNDGE = 0x1b, 283 SQ_OP3_INST_CNDE_INT = 0x1c, 284 SQ_OP3_INST_CNDGT_INT = 0x1d, 285 SQ_OP3_INST_CNDGE_INT = 0x1e, 286 SQ_OP3_INST_MUL_LIT = 0x1f, 287 SQ_ALU_WORD1_LDS_DIRECT_LITERAL_LO = 0x00008dfc, 288 OFFSET_A_mask = 0x1fff << 0, 289 OFFSET_A_shift = 0, 290 STRIDE_A_mask = 0x7f << 13, 291 STRIDE_A_shift = 13, 292 THREAD_REL_A_bit = 1 << 22, 293 SQ_TEX_WORD2 = 0x00008dfc, 294 OFFSET_X_mask = 0x1f << 0, 295 OFFSET_X_shift = 0, 296 OFFSET_Y_mask = 0x1f << 5, 297 OFFSET_Y_shift = 5, 298 OFFSET_Z_mask = 0x1f << 10, 299 OFFSET_Z_shift = 10, 300 SAMPLER_ID_mask = 0x1f << 15, 301 SAMPLER_ID_shift = 15, 302 SQ_TEX_WORD2__SRC_SEL_X_mask = 0x07 << 20, 303 SQ_TEX_WORD2__SRC_SEL_X_shift = 20, 304 SQ_SEL_X = 0x00, 305 SQ_SEL_Y = 0x01, 306 SQ_SEL_Z = 0x02, 307 SQ_SEL_W = 0x03, 308 SQ_SEL_0 = 0x04, 309 SQ_SEL_1 = 0x05, 310 SRC_SEL_Y_mask = 0x07 << 23, 311 SRC_SEL_Y_shift = 23, 312/* SQ_SEL_X = 0x00, */ 313/* SQ_SEL_Y = 0x01, */ 314/* SQ_SEL_Z = 0x02, */ 315/* SQ_SEL_W = 0x03, */ 316/* SQ_SEL_0 = 0x04, */ 317/* SQ_SEL_1 = 0x05, */ 318 SRC_SEL_Z_mask = 0x07 << 26, 319 SRC_SEL_Z_shift = 26, 320/* SQ_SEL_X = 0x00, */ 321/* SQ_SEL_Y = 0x01, */ 322/* SQ_SEL_Z = 0x02, */ 323/* SQ_SEL_W = 0x03, */ 324/* SQ_SEL_0 = 0x04, */ 325/* SQ_SEL_1 = 0x05, */ 326 SRC_SEL_W_mask = 0x07 << 29, 327 SRC_SEL_W_shift = 29, 328/* SQ_SEL_X = 0x00, */ 329/* SQ_SEL_Y = 0x01, */ 330/* SQ_SEL_Z = 0x02, */ 331/* SQ_SEL_W = 0x03, */ 332/* SQ_SEL_0 = 0x04, */ 333/* SQ_SEL_1 = 0x05, */ 334 SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, 335 BURST_COUNT_mask = 0x0f << 16, 336 BURST_COUNT_shift = 16, 337 VALID_PIXEL_MODE_bit = 1 << 20, 338 END_OF_PROGRAM_bit = 1 << 21, 339 SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0xff << 22, 340 SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 22, 341 SQ_CF_INST_MEM_STREAM0_BUF0 = 0x40, 342 SQ_CF_INST_MEM_STREAM0_BUF1 = 0x41, 343 SQ_CF_INST_MEM_STREAM0_BUF2 = 0x42, 344 SQ_CF_INST_MEM_STREAM0_BUF3 = 0x43, 345 SQ_CF_INST_MEM_STREAM1_BUF0 = 0x44, 346 SQ_CF_INST_MEM_STREAM1_BUF1 = 0x45, 347 SQ_CF_INST_MEM_STREAM1_BUF2 = 0x46, 348 SQ_CF_INST_MEM_STREAM1_BUF3 = 0x47, 349 SQ_CF_INST_MEM_STREAM2_BUF0 = 0x48, 350 SQ_CF_INST_MEM_STREAM2_BUF1 = 0x49, 351 SQ_CF_INST_MEM_STREAM2_BUF2 = 0x4a, 352 SQ_CF_INST_MEM_STREAM2_BUF3 = 0x4b, 353 SQ_CF_INST_MEM_STREAM3_BUF0 = 0x4c, 354 SQ_CF_INST_MEM_STREAM3_BUF1 = 0x4d, 355 SQ_CF_INST_MEM_STREAM3_BUF2 = 0x4e, 356 SQ_CF_INST_MEM_STREAM3_BUF3 = 0x4f, 357 SQ_CF_INST_MEM_SCRATCH = 0x50, 358 SQ_CF_INST_MEM_RING = 0x52, 359 SQ_CF_INST_EXPORT = 0x53, 360 SQ_CF_INST_EXPORT_DONE = 0x54, 361 SQ_CF_INST_MEM_EXPORT = 0x55, 362 SQ_CF_INST_MEM_RAT = 0x56, 363 SQ_CF_INST_MEM_RAT_CACHELESS = 0x57, 364 SQ_CF_INST_MEM_RING1 = 0x58, 365 SQ_CF_INST_MEM_RING2 = 0x59, 366 SQ_CF_INST_MEM_RING3 = 0x5a, 367 SQ_CF_INST_MEM_EXPORT_COMBINED = 0x5b, 368 SQ_CF_INST_MEM_RAT_COMBINED_CACHELESS = 0x5c, 369 MARK_bit = 1 << 30, 370 BARRIER_bit = 1 << 31, 371 SQ_CF_ALU_WORD1 = 0x00008dfc, 372 KCACHE_MODE1_mask = 0x03 << 0, 373 KCACHE_MODE1_shift = 0, 374 SQ_CF_KCACHE_NOP = 0x00, 375 SQ_CF_KCACHE_LOCK_1 = 0x01, 376 SQ_CF_KCACHE_LOCK_2 = 0x02, 377 SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, 378 KCACHE_ADDR0_mask = 0xff << 2, 379 KCACHE_ADDR0_shift = 2, 380 KCACHE_ADDR1_mask = 0xff << 10, 381 KCACHE_ADDR1_shift = 10, 382 SQ_CF_ALU_WORD1__COUNT_mask = 0x7f << 18, 383 SQ_CF_ALU_WORD1__COUNT_shift = 18, 384 SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25, 385 SQ_CF_ALU_WORD1__CF_INST_mask = 0x0f << 26, 386 SQ_CF_ALU_WORD1__CF_INST_shift = 26, 387 SQ_CF_INST_ALU = 0x08, 388 SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, 389 SQ_CF_INST_ALU_POP_AFTER = 0x0a, 390 SQ_CF_INST_ALU_POP2_AFTER = 0x0b, 391 SQ_CF_INST_ALU_EXTENDED = 0x0c, 392 SQ_CF_INST_ALU_CONTINUE = 0x0d, 393 SQ_CF_INST_ALU_BREAK = 0x0e, 394 SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, 395 WHOLE_QUAD_MODE_bit = 1 << 30, 396/* BARRIER_bit = 1 << 31, */ 397 SQ_TEX_WORD1 = 0x00008dfc, 398 SQ_TEX_WORD1__DST_GPR_mask = 0x7f << 0, 399 SQ_TEX_WORD1__DST_GPR_shift = 0, 400 SQ_TEX_WORD1__DST_REL_bit = 1 << 7, 401 SQ_TEX_WORD1__DST_SEL_X_mask = 0x07 << 9, 402 SQ_TEX_WORD1__DST_SEL_X_shift = 9, 403/* SQ_SEL_X = 0x00, */ 404/* SQ_SEL_Y = 0x01, */ 405/* SQ_SEL_Z = 0x02, */ 406/* SQ_SEL_W = 0x03, */ 407/* SQ_SEL_0 = 0x04, */ 408/* SQ_SEL_1 = 0x05, */ 409 SQ_SEL_MASK = 0x07, 410 SQ_TEX_WORD1__DST_SEL_Y_mask = 0x07 << 12, 411 SQ_TEX_WORD1__DST_SEL_Y_shift = 12, 412/* SQ_SEL_X = 0x00, */ 413/* SQ_SEL_Y = 0x01, */ 414/* SQ_SEL_Z = 0x02, */ 415/* SQ_SEL_W = 0x03, */ 416/* SQ_SEL_0 = 0x04, */ 417/* SQ_SEL_1 = 0x05, */ 418/* SQ_SEL_MASK = 0x07, */ 419 SQ_TEX_WORD1__DST_SEL_Z_mask = 0x07 << 15, 420 SQ_TEX_WORD1__DST_SEL_Z_shift = 15, 421/* SQ_SEL_X = 0x00, */ 422/* SQ_SEL_Y = 0x01, */ 423/* SQ_SEL_Z = 0x02, */ 424/* SQ_SEL_W = 0x03, */ 425/* SQ_SEL_0 = 0x04, */ 426/* SQ_SEL_1 = 0x05, */ 427/* SQ_SEL_MASK = 0x07, */ 428 SQ_TEX_WORD1__DST_SEL_W_mask = 0x07 << 18, 429 SQ_TEX_WORD1__DST_SEL_W_shift = 18, 430/* SQ_SEL_X = 0x00, */ 431/* SQ_SEL_Y = 0x01, */ 432/* SQ_SEL_Z = 0x02, */ 433/* SQ_SEL_W = 0x03, */ 434/* SQ_SEL_0 = 0x04, */ 435/* SQ_SEL_1 = 0x05, */ 436/* SQ_SEL_MASK = 0x07, */ 437 SQ_TEX_WORD1__LOD_BIAS_mask = 0x7f << 21, 438 SQ_TEX_WORD1__LOD_BIAS_shift = 21, 439 COORD_TYPE_X_bit = 1 << 28, 440 COORD_TYPE_Y_bit = 1 << 29, 441 COORD_TYPE_Z_bit = 1 << 30, 442 COORD_TYPE_W_bit = 1 << 31, 443 SQ_VTX_WORD0 = 0x00008dfc, 444 VTX_INST_mask = 0x1f << 0, 445 VTX_INST_shift = 0, 446 SQ_VTX_INST_FETCH = 0x00, 447 SQ_VTX_INST_SEMANTIC = 0x01, 448 SQ_VTX_INST_GET_BUFFER_RESINFO = 0x0e, 449 FETCH_TYPE_mask = 0x03 << 5, 450 FETCH_TYPE_shift = 5, 451 SQ_VTX_FETCH_VERTEX_DATA = 0x00, 452 SQ_VTX_FETCH_INSTANCE_DATA = 0x01, 453 SQ_VTX_FETCH_NO_INDEX_OFFSET = 0x02, 454 FETCH_WHOLE_QUAD_bit = 1 << 7, 455 BUFFER_ID_mask = 0xff << 8, 456 BUFFER_ID_shift = 8, 457 SQ_VTX_WORD0__SRC_GPR_mask = 0x7f << 16, 458 SQ_VTX_WORD0__SRC_GPR_shift = 16, 459 SRC_REL_bit = 1 << 23, 460 SQ_VTX_WORD0__SRC_SEL_X_mask = 0x03 << 24, 461 SQ_VTX_WORD0__SRC_SEL_X_shift = 24, 462/* SQ_SEL_X = 0x00, */ 463/* SQ_SEL_Y = 0x01, */ 464/* SQ_SEL_Z = 0x02, */ 465/* SQ_SEL_W = 0x03, */ 466 MEGA_FETCH_COUNT_mask = 0x3f << 26, 467 MEGA_FETCH_COUNT_shift = 26, 468 SQ_CF_ALLOC_EXPORT_WORD1_SWIZ = 0x00008dfc, 469 SEL_X_mask = 0x07 << 0, 470 SEL_X_shift = 0, 471/* SQ_SEL_X = 0x00, */ 472/* SQ_SEL_Y = 0x01, */ 473/* SQ_SEL_Z = 0x02, */ 474/* SQ_SEL_W = 0x03, */ 475/* SQ_SEL_0 = 0x04, */ 476/* SQ_SEL_1 = 0x05, */ 477/* SQ_SEL_MASK = 0x07, */ 478 SEL_Y_mask = 0x07 << 3, 479 SEL_Y_shift = 3, 480/* SQ_SEL_X = 0x00, */ 481/* SQ_SEL_Y = 0x01, */ 482/* SQ_SEL_Z = 0x02, */ 483/* SQ_SEL_W = 0x03, */ 484/* SQ_SEL_0 = 0x04, */ 485/* SQ_SEL_1 = 0x05, */ 486/* SQ_SEL_MASK = 0x07, */ 487 SEL_Z_mask = 0x07 << 6, 488 SEL_Z_shift = 6, 489/* SQ_SEL_X = 0x00, */ 490/* SQ_SEL_Y = 0x01, */ 491/* SQ_SEL_Z = 0x02, */ 492/* SQ_SEL_W = 0x03, */ 493/* SQ_SEL_0 = 0x04, */ 494/* SQ_SEL_1 = 0x05, */ 495/* SQ_SEL_MASK = 0x07, */ 496 SEL_W_mask = 0x07 << 9, 497 SEL_W_shift = 9, 498/* SQ_SEL_X = 0x00, */ 499/* SQ_SEL_Y = 0x01, */ 500/* SQ_SEL_Z = 0x02, */ 501/* SQ_SEL_W = 0x03, */ 502/* SQ_SEL_0 = 0x04, */ 503/* SQ_SEL_1 = 0x05, */ 504/* SQ_SEL_MASK = 0x07, */ 505 SQ_MEM_RD_WORD0 = 0x00008dfc, 506 MEM_INST_mask = 0x1f << 0, 507 MEM_INST_shift = 0, 508 SQ_MEM_INST_MEM = 0x02, 509 SQ_MEM_RD_WORD0__ELEM_SIZE_mask = 0x03 << 5, 510 SQ_MEM_RD_WORD0__ELEM_SIZE_shift = 5, 511/* FETCH_WHOLE_QUAD_bit = 1 << 7, */ 512 MEM_OP_mask = 0x07 << 8, 513 MEM_OP_shift = 8, 514 SQ_MEM_OP_RD_SCRATCH = 0x00, 515 SQ_MEM_OP_RD_SCATTER = 0x02, 516 SQ_MEM_OP_GDS = 0x04, 517 SQ_MEM_OP_TF_WRITE = 0x05, 518 SQ_MEM_RD_WORD0__UNCACHED_bit = 1 << 11, 519 INDEXED_bit = 1 << 12, 520 SQ_MEM_RD_WORD0__SRC_GPR_mask = 0x7f << 16, 521 SQ_MEM_RD_WORD0__SRC_GPR_shift = 16, 522/* SRC_REL_bit = 1 << 23, */ 523 SQ_MEM_RD_WORD0__SRC_SEL_X_mask = 0x03 << 24, 524 SQ_MEM_RD_WORD0__SRC_SEL_X_shift = 24, 525/* SQ_SEL_X = 0x00, */ 526/* SQ_SEL_Y = 0x01, */ 527/* SQ_SEL_Z = 0x02, */ 528/* SQ_SEL_W = 0x03, */ 529 BURST_CNT_mask = 0x0f << 26, 530 BURST_CNT_shift = 26, 531 SQ_ALU_WORD1 = 0x00008dfc, 532 SQ_ALU_WORD1__ENCODING_mask = 0x07 << 15, 533 SQ_ALU_WORD1__ENCODING_shift = 15, 534 BANK_SWIZZLE_mask = 0x07 << 18, 535 BANK_SWIZZLE_shift = 18, 536 SQ_ALU_VEC_012 = 0x00, 537 SQ_ALU_VEC_021 = 0x01, 538 SQ_ALU_VEC_120 = 0x02, 539 SQ_ALU_VEC_102 = 0x03, 540 SQ_ALU_VEC_201 = 0x04, 541 SQ_ALU_VEC_210 = 0x05, 542 SQ_ALU_WORD1__DST_GPR_mask = 0x7f << 21, 543 SQ_ALU_WORD1__DST_GPR_shift = 21, 544 SQ_ALU_WORD1__DST_REL_bit = 1 << 28, 545 DST_CHAN_mask = 0x03 << 29, 546 DST_CHAN_shift = 29, 547 CHAN_X = 0x00, 548 CHAN_Y = 0x01, 549 CHAN_Z = 0x02, 550 CHAN_W = 0x03, 551 SQ_ALU_WORD1__CLAMP_bit = 1 << 31, 552 SQ_CF_ALU_WORD0_EXT = 0x00008dfc, 553 KCACHE_BANK_INDEX_MODE0_mask = 0x03 << 4, 554 KCACHE_BANK_INDEX_MODE0_shift = 4, 555 SQ_CF_INDEX_NONE = 0x00, 556 SQ_CF_INDEX_0 = 0x01, 557 SQ_CF_INDEX_1 = 0x02, 558 SQ_CF_INVALID = 0x03, 559 KCACHE_BANK_INDEX_MODE1_mask = 0x03 << 6, 560 KCACHE_BANK_INDEX_MODE1_shift = 6, 561/* SQ_CF_INDEX_NONE = 0x00, */ 562/* SQ_CF_INDEX_0 = 0x01, */ 563/* SQ_CF_INDEX_1 = 0x02, */ 564/* SQ_CF_INVALID = 0x03, */ 565 KCACHE_BANK_INDEX_MODE2_mask = 0x03 << 8, 566 KCACHE_BANK_INDEX_MODE2_shift = 8, 567/* SQ_CF_INDEX_NONE = 0x00, */ 568/* SQ_CF_INDEX_0 = 0x01, */ 569/* SQ_CF_INDEX_1 = 0x02, */ 570/* SQ_CF_INVALID = 0x03, */ 571 KCACHE_BANK_INDEX_MODE3_mask = 0x03 << 10, 572 KCACHE_BANK_INDEX_MODE3_shift = 10, 573/* SQ_CF_INDEX_NONE = 0x00, */ 574/* SQ_CF_INDEX_0 = 0x01, */ 575/* SQ_CF_INDEX_1 = 0x02, */ 576/* SQ_CF_INVALID = 0x03, */ 577 KCACHE_BANK2_mask = 0x0f << 22, 578 KCACHE_BANK2_shift = 22, 579 KCACHE_BANK3_mask = 0x0f << 26, 580 KCACHE_BANK3_shift = 26, 581 KCACHE_MODE2_mask = 0x03 << 30, 582 KCACHE_MODE2_shift = 30, 583/* SQ_CF_KCACHE_NOP = 0x00, */ 584/* SQ_CF_KCACHE_LOCK_1 = 0x01, */ 585/* SQ_CF_KCACHE_LOCK_2 = 0x02, */ 586/* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ 587 SQ_ALU_WORD0_LDS_IDX_OP = 0x00008dfc, 588 SRC0_SEL_mask = 0x1ff << 0, 589 SRC0_SEL_shift = 0, 590/* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ 591/* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ 592/* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ 593/* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ 594/* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ 595/* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ 596/* SQ_ALU_SRC_TIME_HI = 0xe3, */ 597/* SQ_ALU_SRC_TIME_LO = 0xe4, */ 598/* SQ_ALU_SRC_MASK_HI = 0xe5, */ 599/* SQ_ALU_SRC_MASK_LO = 0xe6, */ 600/* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ 601/* SQ_ALU_SRC_SIMD_ID = 0xe8, */ 602/* SQ_ALU_SRC_SE_ID = 0xe9, */ 603/* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ 604/* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ 605/* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ 606/* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ 607/* SQ_ALU_SRC_LOOP_IDX = 0xee, */ 608/* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ 609/* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ 610/* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ 611/* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ 612/* SQ_ALU_SRC_1_DBL_L = 0xf4, */ 613/* SQ_ALU_SRC_1_DBL_M = 0xf5, */ 614/* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ 615/* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ 616/* SQ_ALU_SRC_0 = 0xf8, */ 617/* SQ_ALU_SRC_1 = 0xf9, */ 618/* SQ_ALU_SRC_1_INT = 0xfa, */ 619/* SQ_ALU_SRC_M_1_INT = 0xfb, */ 620/* SQ_ALU_SRC_0_5 = 0xfc, */ 621/* SQ_ALU_SRC_LITERAL = 0xfd, */ 622/* SQ_ALU_SRC_PV = 0xfe, */ 623/* SQ_ALU_SRC_PS = 0xff, */ 624 SRC0_REL_bit = 1 << 9, 625 SRC0_CHAN_mask = 0x03 << 10, 626 SRC0_CHAN_shift = 10, 627/* SQ_CHAN_X = 0x00, */ 628/* SQ_CHAN_Y = 0x01, */ 629/* SQ_CHAN_Z = 0x02, */ 630/* SQ_CHAN_W = 0x03, */ 631 IDX_OFFSET_4_bit = 1 << 12, 632 SRC1_SEL_mask = 0x1ff << 13, 633 SRC1_SEL_shift = 13, 634/* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ 635/* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ 636/* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ 637/* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ 638/* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ 639/* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ 640/* SQ_ALU_SRC_TIME_HI = 0xe3, */ 641/* SQ_ALU_SRC_TIME_LO = 0xe4, */ 642/* SQ_ALU_SRC_MASK_HI = 0xe5, */ 643/* SQ_ALU_SRC_MASK_LO = 0xe6, */ 644/* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ 645/* SQ_ALU_SRC_SIMD_ID = 0xe8, */ 646/* SQ_ALU_SRC_SE_ID = 0xe9, */ 647/* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ 648/* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ 649/* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ 650/* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ 651/* SQ_ALU_SRC_LOOP_IDX = 0xee, */ 652/* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ 653/* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ 654/* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ 655/* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ 656/* SQ_ALU_SRC_1_DBL_L = 0xf4, */ 657/* SQ_ALU_SRC_1_DBL_M = 0xf5, */ 658/* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ 659/* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ 660/* SQ_ALU_SRC_0 = 0xf8, */ 661/* SQ_ALU_SRC_1 = 0xf9, */ 662/* SQ_ALU_SRC_1_INT = 0xfa, */ 663/* SQ_ALU_SRC_M_1_INT = 0xfb, */ 664/* SQ_ALU_SRC_0_5 = 0xfc, */ 665/* SQ_ALU_SRC_LITERAL = 0xfd, */ 666/* SQ_ALU_SRC_PV = 0xfe, */ 667/* SQ_ALU_SRC_PS = 0xff, */ 668 SRC1_REL_bit = 1 << 22, 669 SRC1_CHAN_mask = 0x03 << 23, 670 SRC1_CHAN_shift = 23, 671/* SQ_CHAN_X = 0x00, */ 672/* SQ_CHAN_Y = 0x01, */ 673/* SQ_CHAN_Z = 0x02, */ 674/* SQ_CHAN_W = 0x03, */ 675 IDX_OFFSET_5_bit = 1 << 25, 676 INDEX_MODE_mask = 0x07 << 26, 677 INDEX_MODE_shift = 26, 678 SQ_INDEX_AR_X = 0x00, 679 SQ_INDEX_LOOP = 0x04, 680 SQ_INDEX_GLOBAL = 0x05, 681 SQ_INDEX_GLOBAL_AR_X = 0x06, 682 PRED_SEL_mask = 0x03 << 29, 683 PRED_SEL_shift = 29, 684 SQ_PRED_SEL_OFF = 0x00, 685 SQ_PRED_SEL_ZERO = 0x02, 686 SQ_PRED_SEL_ONE = 0x03, 687 LAST_bit = 1 << 31, 688 SQ_MEM_GDS_WORD2 = 0x00008dfc, 689 SQ_MEM_GDS_WORD2__DST_SEL_X_mask = 0x07 << 0, 690 SQ_MEM_GDS_WORD2__DST_SEL_X_shift = 0, 691/* SQ_SEL_X = 0x00, */ 692/* SQ_SEL_Y = 0x01, */ 693/* SQ_SEL_Z = 0x02, */ 694/* SQ_SEL_W = 0x03, */ 695/* SQ_SEL_0 = 0x04, */ 696/* SQ_SEL_1 = 0x05, */ 697/* SQ_SEL_MASK = 0x07, */ 698 SQ_MEM_GDS_WORD2__DST_SEL_Y_mask = 0x07 << 3, 699 SQ_MEM_GDS_WORD2__DST_SEL_Y_shift = 3, 700/* SQ_SEL_X = 0x00, */ 701/* SQ_SEL_Y = 0x01, */ 702/* SQ_SEL_Z = 0x02, */ 703/* SQ_SEL_W = 0x03, */ 704/* SQ_SEL_0 = 0x04, */ 705/* SQ_SEL_1 = 0x05, */ 706/* SQ_SEL_MASK = 0x07, */ 707 SQ_MEM_GDS_WORD2__DST_SEL_Z_mask = 0x07 << 6, 708 SQ_MEM_GDS_WORD2__DST_SEL_Z_shift = 6, 709/* SQ_SEL_X = 0x00, */ 710/* SQ_SEL_Y = 0x01, */ 711/* SQ_SEL_Z = 0x02, */ 712/* SQ_SEL_W = 0x03, */ 713/* SQ_SEL_0 = 0x04, */ 714/* SQ_SEL_1 = 0x05, */ 715/* SQ_SEL_MASK = 0x07, */ 716 SQ_MEM_GDS_WORD2__DST_SEL_W_mask = 0x07 << 9, 717 SQ_MEM_GDS_WORD2__DST_SEL_W_shift = 9, 718/* SQ_SEL_X = 0x00, */ 719/* SQ_SEL_Y = 0x01, */ 720/* SQ_SEL_Z = 0x02, */ 721/* SQ_SEL_W = 0x03, */ 722/* SQ_SEL_0 = 0x04, */ 723/* SQ_SEL_1 = 0x05, */ 724/* SQ_SEL_MASK = 0x07, */ 725 SQ_CF_ALLOC_EXPORT_WORD0_RAT = 0x00008dfc, 726 RAT_ID_mask = 0x0f << 0, 727 RAT_ID_shift = 0, 728 RAT_INST_mask = 0x3f << 4, 729 RAT_INST_shift = 4, 730 SQ_EXPORT_RAT_INST_NOP = 0x00, 731 SQ_EXPORT_RAT_INST_STORE_TYPED = 0x01, 732 SQ_EXPORT_RAT_INST_STORE_RAW = 0x02, 733 SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x03, 734 SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x04, 735 SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x05, 736 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x06, 737 SQ_EXPORT_RAT_INST_ADD = 0x07, 738 SQ_EXPORT_RAT_INST_SUB = 0x08, 739 SQ_EXPORT_RAT_INST_RSUB = 0x09, 740 SQ_EXPORT_RAT_INST_MIN_INT = 0x0a, 741 SQ_EXPORT_RAT_INST_MIN_UINT = 0x0b, 742 SQ_EXPORT_RAT_INST_MAX_INT = 0x0c, 743 SQ_EXPORT_RAT_INST_MAX_UINT = 0x0d, 744 SQ_EXPORT_RAT_INST_AND = 0x0e, 745 SQ_EXPORT_RAT_INST_OR = 0x0f, 746 SQ_EXPORT_RAT_INST_XOR = 0x10, 747 SQ_EXPORT_RAT_INST_MSKOR = 0x11, 748 SQ_EXPORT_RAT_INST_INC_UINT = 0x12, 749 SQ_EXPORT_RAT_INST_DEC_UINT = 0x13, 750 SQ_EXPORT_RAT_INST_NOP_RTN = 0x20, 751 SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22, 752 SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23, 753 SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24, 754 SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25, 755 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26, 756 SQ_EXPORT_RAT_INST_ADD_RTN = 0x27, 757 SQ_EXPORT_RAT_INST_SUB_RTN = 0x28, 758 SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29, 759 SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a, 760 SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b, 761 SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c, 762 SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d, 763 SQ_EXPORT_RAT_INST_AND_RTN = 0x2e, 764 SQ_EXPORT_RAT_INST_OR_RTN = 0x2f, 765 SQ_EXPORT_RAT_INST_XOR_RTN = 0x30, 766 SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31, 767 SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32, 768 SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33, 769 RAT_INDEX_MODE_mask = 0x03 << 11, 770 RAT_INDEX_MODE_shift = 11, 771/* SQ_CF_INDEX_NONE = 0x00, */ 772/* SQ_CF_INDEX_0 = 0x01, */ 773/* SQ_CF_INDEX_1 = 0x02, */ 774/* SQ_CF_INVALID = 0x03, */ 775 SQ_CF_ALLOC_EXPORT_WORD0_RAT__TYPE_mask = 0x03 << 13, 776 SQ_CF_ALLOC_EXPORT_WORD0_RAT__TYPE_shift = 13, 777 SQ_EXPORT_PIXEL = 0x00, 778 SQ_EXPORT_POS = 0x01, 779 SQ_EXPORT_PARAM = 0x02, 780 X_UNUSED_FOR_SX_EXPORTS = 0x03, 781 RW_GPR_mask = 0x7f << 15, 782 RW_GPR_shift = 15, 783 RW_REL_bit = 1 << 22, 784 INDEX_GPR_mask = 0x7f << 23, 785 INDEX_GPR_shift = 23, 786 SQ_CF_ALLOC_EXPORT_WORD0_RAT__ELEM_SIZE_mask = 0x03 << 30, 787 SQ_CF_ALLOC_EXPORT_WORD0_RAT__ELEM_SIZE_shift = 30, 788 SQ_CF_ALU_WORD0 = 0x00008dfc, 789 SQ_CF_ALU_WORD0__ADDR_mask = 0x3fffff << 0, 790 SQ_CF_ALU_WORD0__ADDR_shift = 0, 791 KCACHE_BANK0_mask = 0x0f << 22, 792 KCACHE_BANK0_shift = 22, 793 KCACHE_BANK1_mask = 0x0f << 26, 794 KCACHE_BANK1_shift = 26, 795 KCACHE_MODE0_mask = 0x03 << 30, 796 KCACHE_MODE0_shift = 30, 797/* SQ_CF_KCACHE_NOP = 0x00, */ 798/* SQ_CF_KCACHE_LOCK_1 = 0x01, */ 799/* SQ_CF_KCACHE_LOCK_2 = 0x02, */ 800/* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ 801 SQ_MEM_GDS_WORD1 = 0x00008dfc, 802 SQ_MEM_GDS_WORD1__DST_GPR_mask = 0x7f << 0, 803 SQ_MEM_GDS_WORD1__DST_GPR_shift = 0, 804 DST_REL_MODE_mask = 0x03 << 7, 805 DST_REL_MODE_shift = 7, 806 SQ_REL_NONE = 0x00, 807 SQ_REL_LOOP = 0x01, 808 SQ_REL_GLOBAL = 0x02, 809 GDS_OP_mask = 0x3f << 9, 810 GDS_OP_shift = 9, 811 SQ_DS_INST_ADD = 0x00, 812 SQ_DS_INST_SUB = 0x01, 813 SQ_DS_INST_RSUB = 0x02, 814 SQ_DS_INST_INC = 0x03, 815 SQ_DS_INST_DEC = 0x04, 816 SQ_DS_INST_MIN_INT = 0x05, 817 SQ_DS_INST_MAX_INT = 0x06, 818 SQ_DS_INST_MIN_UINT = 0x07, 819 SQ_DS_INST_MAX_UINT = 0x08, 820 SQ_DS_INST_AND = 0x09, 821 SQ_DS_INST_OR = 0x0a, 822 SQ_DS_INST_XOR = 0x0b, 823 SQ_DS_INST_MSKOR = 0x0c, 824 SQ_DS_INST_WRITE = 0x0d, 825 SQ_DS_INST_WRITE_REL = 0x0e, 826 SQ_DS_INST_WRITE2 = 0x0f, 827 SQ_DS_INST_CMP_STORE = 0x10, 828 SQ_DS_INST_CMP_STORE_SPF = 0x11, 829 SQ_DS_INST_BYTE_WRITE = 0x12, 830 SQ_DS_INST_SHORT_WRITE = 0x13, 831 SQ_DS_INST_ADD_RET = 0x20, 832 SQ_DS_INST_SUB_RET = 0x21, 833 SQ_DS_INST_RSUB_RET = 0x22, 834 SQ_DS_INST_INC_RET = 0x23, 835 SQ_DS_INST_DEC_RET = 0x24, 836 SQ_DS_INST_MIN_INT_RET = 0x25, 837 SQ_DS_INST_MAX_INT_RET = 0x26, 838 SQ_DS_INST_MIN_UINT_RET = 0x27, 839 SQ_DS_INST_MAX_UINT_RET = 0x28, 840 SQ_DS_INST_AND_RET = 0x29, 841 SQ_DS_INST_OR_RET = 0x2a, 842 SQ_DS_INST_XOR_RET = 0x2b, 843 SQ_DS_INST_MSKOR_RET = 0x2c, 844 SQ_DS_INST_XCHG_RET = 0x2d, 845 SQ_DS_INST_XCHG_REL_RET = 0x2e, 846 SQ_DS_INST_XCHG2_RET = 0x2f, 847 SQ_DS_INST_CMP_XCHG_RET = 0x30, 848 SQ_DS_INST_CMP_XCHG_SPF_RET = 0x31, 849 SQ_DS_INST_READ_RET = 0x32, 850 SQ_DS_INST_READ_REL_RET = 0x33, 851 SQ_DS_INST_READ2_RET = 0x34, 852 SQ_DS_INST_READWRITE_RET = 0x35, 853 SQ_DS_INST_BYTE_READ_RET = 0x36, 854 SQ_DS_INST_UBYTE_READ_RET = 0x37, 855 SQ_DS_INST_SHORT_READ_RET = 0x38, 856 SQ_DS_INST_USHORT_READ_RET = 0x39, 857 SQ_DS_INST_ATOMIC_ORDERED_ALLOC_RET = 0x3f, 858 DS_OFFSET_mask = 0x7f << 16, 859 DS_OFFSET_shift = 16, 860 UAV_INDEX_MODE_mask = 0x03 << 24, 861 UAV_INDEX_MODE_shift = 24, 862/* SQ_CF_INDEX_NONE = 0x00, */ 863/* SQ_CF_INDEX_0 = 0x01, */ 864/* SQ_CF_INDEX_1 = 0x02, */ 865/* SQ_CF_INVALID = 0x03, */ 866 UAV_ID_mask = 0x0f << 26, 867 UAV_ID_shift = 26, 868 ALLOC_CONSUME_bit = 1 << 30, 869 BCAST_FIRST_REQ_bit = 1 << 31, 870 SQ_MEM_RD_WORD2 = 0x00008dfc, 871 ARRAY_BASE_mask = 0x1fff << 0, 872 ARRAY_BASE_shift = 0, 873 SQ_MEM_RD_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, 874 SQ_MEM_RD_WORD2__ENDIAN_SWAP_shift = 16, 875 SQ_ENDIAN_NONE = 0x00, 876 SQ_ENDIAN_8IN16 = 0x01, 877 SQ_ENDIAN_8IN32 = 0x02, 878 SQ_MEM_RD_WORD2__ARRAY_SIZE_mask = 0xfff << 20, 879 SQ_MEM_RD_WORD2__ARRAY_SIZE_shift = 20, 880 SQ_CF_ALU_WORD1_EXT = 0x00008dfc, 881 KCACHE_MODE3_mask = 0x03 << 0, 882 KCACHE_MODE3_shift = 0, 883/* SQ_CF_KCACHE_NOP = 0x00, */ 884/* SQ_CF_KCACHE_LOCK_1 = 0x01, */ 885/* SQ_CF_KCACHE_LOCK_2 = 0x02, */ 886/* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ 887 KCACHE_ADDR2_mask = 0xff << 2, 888 KCACHE_ADDR2_shift = 2, 889 KCACHE_ADDR3_mask = 0xff << 10, 890 KCACHE_ADDR3_shift = 10, 891 SQ_CF_ALU_WORD1_EXT__CF_INST_mask = 0x0f << 26, 892 SQ_CF_ALU_WORD1_EXT__CF_INST_shift = 26, 893/* SQ_CF_INST_ALU = 0x08, */ 894/* SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, */ 895/* SQ_CF_INST_ALU_POP_AFTER = 0x0a, */ 896/* SQ_CF_INST_ALU_POP2_AFTER = 0x0b, */ 897/* SQ_CF_INST_ALU_EXTENDED = 0x0c, */ 898/* SQ_CF_INST_ALU_CONTINUE = 0x0d, */ 899/* SQ_CF_INST_ALU_BREAK = 0x0e, */ 900/* SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, */ 901/* BARRIER_bit = 1 << 31, */ 902 SQ_CF_GWS_WORD0 = 0x00008dfc, 903 VALUE_mask = 0x3ff << 0, 904 VALUE_shift = 0, 905 RESOURCE_mask = 0x1f << 16, 906 RESOURCE_shift = 16, 907 SIGN_bit = 1 << 25, 908 VAL_INDEX_MODE_mask = 0x03 << 26, 909 VAL_INDEX_MODE_shift = 26, 910 SQ_GWS_INDEX_NONE = 0x00, 911 SQ_GWS_INDEX_0 = 0x01, 912 SQ_GWS_INDEX_1 = 0x02, 913 SQ_GWS_INDEX_MIX = 0x03, 914 RSRC_INDEX_MODE_mask = 0x03 << 28, 915 RSRC_INDEX_MODE_shift = 28, 916/* SQ_CF_INDEX_NONE = 0x00, */ 917/* SQ_CF_INDEX_0 = 0x01, */ 918/* SQ_CF_INDEX_1 = 0x02, */ 919/* SQ_CF_INVALID = 0x03, */ 920 GWS_OPCODE_mask = 0x03 << 30, 921 GWS_OPCODE_shift = 30, 922 SQ_GWS_SEMA_V = 0x00, 923 SQ_GWS_SEMA_P = 0x01, 924 SQ_GWS_BARRIER = 0x02, 925 SQ_GWS_INIT = 0x03, 926 SQ_VTX_WORD2 = 0x00008dfc, 927 SQ_VTX_WORD2__OFFSET_mask = 0xffff << 0, 928 SQ_VTX_WORD2__OFFSET_shift = 0, 929 SQ_VTX_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, 930 SQ_VTX_WORD2__ENDIAN_SWAP_shift = 16, 931/* SQ_ENDIAN_NONE = 0x00, */ 932/* SQ_ENDIAN_8IN16 = 0x01, */ 933/* SQ_ENDIAN_8IN32 = 0x02, */ 934 CONST_BUF_NO_STRIDE_bit = 1 << 18, 935 MEGA_FETCH_bit = 1 << 19, 936 SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20, 937 BUFFER_INDEX_MODE_mask = 0x03 << 21, 938 BUFFER_INDEX_MODE_shift = 21, 939/* SQ_CF_INDEX_NONE = 0x00, */ 940/* SQ_CF_INDEX_0 = 0x01, */ 941/* SQ_CF_INDEX_1 = 0x02, */ 942/* SQ_CF_INVALID = 0x03, */ 943 SQ_CF_ALLOC_EXPORT_WORD1_BUF = 0x00008dfc, 944 SQ_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_mask = 0xfff << 0, 945 SQ_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_shift = 0, 946 COMP_MASK_mask = 0x0f << 12, 947 COMP_MASK_shift = 12, 948 SQ_CF_WORD0 = 0x00008dfc, 949 SQ_CF_WORD0__ADDR_mask = 0xffffff << 0, 950 SQ_CF_WORD0__ADDR_shift = 0, 951 JUMPTABLE_SEL_mask = 0x07 << 24, 952 JUMPTABLE_SEL_shift = 24, 953 SQ_CF_JUMPTABLE_SEL_CONST_A = 0x00, 954 SQ_CF_JUMPTABLE_SEL_CONST_B = 0x01, 955 SQ_CF_JUMPTABLE_SEL_CONST_C = 0x02, 956 SQ_CF_JUMPTABLE_SEL_CONST_D = 0x03, 957 SQ_CF_JUMPTABLE_SEL_INDEX_0 = 0x04, 958 SQ_CF_JUMPTABLE_SEL_INDEX_1 = 0x05, 959 SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, 960/* ARRAY_BASE_mask = 0x1fff << 0, */ 961/* ARRAY_BASE_shift = 0, */ 962 SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x03 << 13, 963 SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13, 964/* SQ_EXPORT_PIXEL = 0x00, */ 965/* SQ_EXPORT_POS = 0x01, */ 966/* SQ_EXPORT_PARAM = 0x02, */ 967/* X_UNUSED_FOR_SX_EXPORTS = 0x03, */ 968/* RW_GPR_mask = 0x7f << 15, */ 969/* RW_GPR_shift = 15, */ 970/* RW_REL_bit = 1 << 22, */ 971/* INDEX_GPR_mask = 0x7f << 23, */ 972/* INDEX_GPR_shift = 23, */ 973 SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_mask = 0x03 << 30, 974 SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_shift = 30, 975 SQ_MEM_GDS_WORD0 = 0x00008dfc, 976/* MEM_INST_mask = 0x1f << 0, */ 977/* MEM_INST_shift = 0, */ 978/* SQ_MEM_INST_MEM = 0x02, */ 979/* MEM_OP_mask = 0x07 << 8, */ 980/* MEM_OP_shift = 8, */ 981/* SQ_MEM_OP_RD_SCRATCH = 0x00, */ 982/* SQ_MEM_OP_RD_SCATTER = 0x02, */ 983/* SQ_MEM_OP_GDS = 0x04, */ 984/* SQ_MEM_OP_TF_WRITE = 0x05, */ 985 SQ_MEM_GDS_WORD0__SRC_GPR_mask = 0x7f << 11, 986 SQ_MEM_GDS_WORD0__SRC_GPR_shift = 11, 987 SRC_REL_MODE_mask = 0x03 << 18, 988 SRC_REL_MODE_shift = 18, 989/* SQ_REL_NONE = 0x00, */ 990/* SQ_REL_LOOP = 0x01, */ 991/* SQ_REL_GLOBAL = 0x02, */ 992 SQ_MEM_GDS_WORD0__SRC_SEL_X_mask = 0x07 << 20, 993 SQ_MEM_GDS_WORD0__SRC_SEL_X_shift = 20, 994/* SQ_SEL_X = 0x00, */ 995/* SQ_SEL_Y = 0x01, */ 996/* SQ_SEL_Z = 0x02, */ 997/* SQ_SEL_W = 0x03, */ 998/* SQ_SEL_0 = 0x04, */ 999/* SQ_SEL_1 = 0x05, */ 1000/* SRC_SEL_Y_mask = 0x07 << 23, */ 1001/* SRC_SEL_Y_shift = 23, */ 1002/* SQ_SEL_X = 0x00, */ 1003/* SQ_SEL_Y = 0x01, */ 1004/* SQ_SEL_Z = 0x02, */ 1005/* SQ_SEL_W = 0x03, */ 1006/* SQ_SEL_0 = 0x04, */ 1007/* SQ_SEL_1 = 0x05, */ 1008/* SRC_SEL_Z_mask = 0x07 << 26, */ 1009/* SRC_SEL_Z_shift = 26, */ 1010/* SQ_SEL_X = 0x00, */ 1011/* SQ_SEL_Y = 0x01, */ 1012/* SQ_SEL_Z = 0x02, */ 1013/* SQ_SEL_W = 0x03, */ 1014/* SQ_SEL_0 = 0x04, */ 1015/* SQ_SEL_1 = 0x05, */ 1016 SQ_ALU_WORD1_LDS_DIRECT_LITERAL_HI = 0x00008dfc, 1017 OFFSET_B_mask = 0x1fff << 0, 1018 OFFSET_B_shift = 0, 1019 STRIDE_B_mask = 0x7f << 13, 1020 STRIDE_B_shift = 13, 1021 THREAD_REL_B_bit = 1 << 22, 1022 DIRECT_READ_32_bit = 1 << 31, 1023 SQ_VTX_WORD1 = 0x00008dfc, 1024 SQ_VTX_WORD1__DST_SEL_X_mask = 0x07 << 9, 1025 SQ_VTX_WORD1__DST_SEL_X_shift = 9, 1026/* SQ_SEL_X = 0x00, */ 1027/* SQ_SEL_Y = 0x01, */ 1028/* SQ_SEL_Z = 0x02, */ 1029/* SQ_SEL_W = 0x03, */ 1030/* SQ_SEL_0 = 0x04, */ 1031/* SQ_SEL_1 = 0x05, */ 1032/* SQ_SEL_MASK = 0x07, */ 1033 SQ_VTX_WORD1__DST_SEL_Y_mask = 0x07 << 12, 1034 SQ_VTX_WORD1__DST_SEL_Y_shift = 12, 1035/* SQ_SEL_X = 0x00, */ 1036/* SQ_SEL_Y = 0x01, */ 1037/* SQ_SEL_Z = 0x02, */ 1038/* SQ_SEL_W = 0x03, */ 1039/* SQ_SEL_0 = 0x04, */ 1040/* SQ_SEL_1 = 0x05, */ 1041/* SQ_SEL_MASK = 0x07, */ 1042 SQ_VTX_WORD1__DST_SEL_Z_mask = 0x07 << 15, 1043 SQ_VTX_WORD1__DST_SEL_Z_shift = 15, 1044/* SQ_SEL_X = 0x00, */ 1045/* SQ_SEL_Y = 0x01, */ 1046/* SQ_SEL_Z = 0x02, */ 1047/* SQ_SEL_W = 0x03, */ 1048/* SQ_SEL_0 = 0x04, */ 1049/* SQ_SEL_1 = 0x05, */ 1050/* SQ_SEL_MASK = 0x07, */ 1051 SQ_VTX_WORD1__DST_SEL_W_mask = 0x07 << 18, 1052 SQ_VTX_WORD1__DST_SEL_W_shift = 18, 1053/* SQ_SEL_X = 0x00, */ 1054/* SQ_SEL_Y = 0x01, */ 1055/* SQ_SEL_Z = 0x02, */ 1056/* SQ_SEL_W = 0x03, */ 1057/* SQ_SEL_0 = 0x04, */ 1058/* SQ_SEL_1 = 0x05, */ 1059/* SQ_SEL_MASK = 0x07, */ 1060 USE_CONST_FIELDS_bit = 1 << 21, 1061 SQ_VTX_WORD1__DATA_FORMAT_mask = 0x3f << 22, 1062 SQ_VTX_WORD1__DATA_FORMAT_shift = 22, 1063 SQ_VTX_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, 1064 SQ_VTX_WORD1__NUM_FORMAT_ALL_shift = 28, 1065 SQ_NUM_FORMAT_NORM = 0x00, 1066 SQ_NUM_FORMAT_INT = 0x01, 1067 SQ_NUM_FORMAT_SCALED = 0x02, 1068 SQ_VTX_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, 1069 SQ_VTX_WORD1__SRF_MODE_ALL_bit = 1 << 31, 1070 SQ_ALU_WORD1_OP2 = 0x00008dfc, 1071 SRC0_ABS_bit = 1 << 0, 1072 SRC1_ABS_bit = 1 << 1, 1073 UPDATE_EXECUTE_MASK_bit = 1 << 2, 1074 UPDATE_PRED_bit = 1 << 3, 1075 WRITE_MASK_bit = 1 << 4, 1076 OMOD_mask = 0x03 << 5, 1077 OMOD_shift = 5, 1078 SQ_ALU_OMOD_OFF = 0x00, 1079 SQ_ALU_OMOD_M2 = 0x01, 1080 SQ_ALU_OMOD_M4 = 0x02, 1081 SQ_ALU_OMOD_D2 = 0x03, 1082 SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x7ff << 7, 1083 SQ_ALU_WORD1_OP2__ALU_INST_shift = 7, 1084 SQ_OP2_INST_ADD = 0x00, 1085 SQ_OP2_INST_MUL = 0x01, 1086 SQ_OP2_INST_MUL_IEEE = 0x02, 1087 SQ_OP2_INST_MAX = 0x03, 1088 SQ_OP2_INST_MIN = 0x04, 1089 SQ_OP2_INST_MAX_DX10 = 0x05, 1090 SQ_OP2_INST_MIN_DX10 = 0x06, 1091 SQ_OP2_INST_SETE = 0x08, 1092 SQ_OP2_INST_SETGT = 0x09, 1093 SQ_OP2_INST_SETGE = 0x0a, 1094 SQ_OP2_INST_SETNE = 0x0b, 1095 SQ_OP2_INST_SETE_DX10 = 0x0c, 1096 SQ_OP2_INST_SETGT_DX10 = 0x0d, 1097 SQ_OP2_INST_SETGE_DX10 = 0x0e, 1098 SQ_OP2_INST_SETNE_DX10 = 0x0f, 1099 SQ_OP2_INST_FRACT = 0x10, 1100 SQ_OP2_INST_TRUNC = 0x11, 1101 SQ_OP2_INST_CEIL = 0x12, 1102 SQ_OP2_INST_RNDNE = 0x13, 1103 SQ_OP2_INST_FLOOR = 0x14, 1104 SQ_OP2_INST_ASHR_INT = 0x15, 1105 SQ_OP2_INST_LSHR_INT = 0x16, 1106 SQ_OP2_INST_LSHL_INT = 0x17, 1107 SQ_OP2_INST_MOV = 0x19, 1108 SQ_OP2_INST_NOP = 0x1a, 1109 SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, 1110 SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, 1111 SQ_OP2_INST_PRED_SETE = 0x20, 1112 SQ_OP2_INST_PRED_SETGT = 0x21, 1113 SQ_OP2_INST_PRED_SETGE = 0x22, 1114 SQ_OP2_INST_PRED_SETNE = 0x23, 1115 SQ_OP2_INST_PRED_SET_INV = 0x24, 1116 SQ_OP2_INST_PRED_SET_POP = 0x25, 1117 SQ_OP2_INST_PRED_SET_CLR = 0x26, 1118 SQ_OP2_INST_PRED_SET_RESTORE = 0x27, 1119 SQ_OP2_INST_PRED_SETE_PUSH = 0x28, 1120 SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, 1121 SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, 1122 SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, 1123 SQ_OP2_INST_KILLE = 0x2c, 1124 SQ_OP2_INST_KILLGT = 0x2d, 1125 SQ_OP2_INST_KILLGE = 0x2e, 1126 SQ_OP2_INST_KILLNE = 0x2f, 1127 SQ_OP2_INST_AND_INT = 0x30, 1128 SQ_OP2_INST_OR_INT = 0x31, 1129 SQ_OP2_INST_XOR_INT = 0x32, 1130 SQ_OP2_INST_NOT_INT = 0x33, 1131 SQ_OP2_INST_ADD_INT = 0x34, 1132 SQ_OP2_INST_SUB_INT = 0x35, 1133 SQ_OP2_INST_MAX_INT = 0x36, 1134 SQ_OP2_INST_MIN_INT = 0x37, 1135 SQ_OP2_INST_MAX_UINT = 0x38, 1136 SQ_OP2_INST_MIN_UINT = 0x39, 1137 SQ_OP2_INST_SETE_INT = 0x3a, 1138 SQ_OP2_INST_SETGT_INT = 0x3b, 1139 SQ_OP2_INST_SETGE_INT = 0x3c, 1140 SQ_OP2_INST_SETNE_INT = 0x3d, 1141 SQ_OP2_INST_SETGT_UINT = 0x3e, 1142 SQ_OP2_INST_SETGE_UINT = 0x3f, 1143 SQ_OP2_INST_KILLGT_UINT = 0x40, 1144 SQ_OP2_INST_KILLGE_UINT = 0x41, 1145 SQ_OP2_INST_PRED_SETE_INT = 0x42, 1146 SQ_OP2_INST_PRED_SETGT_INT = 0x43, 1147 SQ_OP2_INST_PRED_SETGE_INT = 0x44, 1148 SQ_OP2_INST_PRED_SETNE_INT = 0x45, 1149 SQ_OP2_INST_KILLE_INT = 0x46, 1150 SQ_OP2_INST_KILLGT_INT = 0x47, 1151 SQ_OP2_INST_KILLGE_INT = 0x48, 1152 SQ_OP2_INST_KILLNE_INT = 0x49, 1153 SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, 1154 SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, 1155 SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, 1156 SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, 1157 SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, 1158 SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, 1159 SQ_OP2_INST_FLT_TO_INT = 0x50, 1160 SQ_OP2_INST_BFREV_INT = 0x51, 1161 SQ_OP2_INST_ADDC_UINT = 0x52, 1162 SQ_OP2_INST_SUBB_UINT = 0x53, 1163 SQ_OP2_INST_GROUP_BARRIER = 0x54, 1164 SQ_OP2_INST_GROUP_SEQ_BEGIN = 0x55, 1165 SQ_OP2_INST_GROUP_SEQ_END = 0x56, 1166 SQ_OP2_INST_SET_MODE = 0x57, 1167 SQ_OP2_INST_SET_CF_IDX0 = 0x58, 1168 SQ_OP2_INST_SET_CF_IDX1 = 0x59, 1169 SQ_OP2_INST_SET_LDS_SIZE = 0x5a, 1170 SQ_OP2_INST_EXP_IEEE = 0x81, 1171 SQ_OP2_INST_LOG_CLAMPED = 0x82, 1172 SQ_OP2_INST_LOG_IEEE = 0x83, 1173 SQ_OP2_INST_RECIP_CLAMPED = 0x84, 1174 SQ_OP2_INST_RECIP_FF = 0x85, 1175 SQ_OP2_INST_RECIP_IEEE = 0x86, 1176 SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x87, 1177 SQ_OP2_INST_RECIPSQRT_FF = 0x88, 1178 SQ_OP2_INST_RECIPSQRT_IEEE = 0x89, 1179 SQ_OP2_INST_SQRT_IEEE = 0x8a, 1180 SQ_OP2_INST_SIN = 0x8d, 1181 SQ_OP2_INST_COS = 0x8e, 1182 SQ_OP2_INST_MULLO_INT = 0x8f, 1183 SQ_OP2_INST_MULHI_INT = 0x90, 1184 SQ_OP2_INST_MULLO_UINT = 0x91, 1185 SQ_OP2_INST_MULHI_UINT = 0x92, 1186 SQ_OP2_INST_RECIP_INT = 0x93, 1187 SQ_OP2_INST_RECIP_UINT = 0x94, 1188 SQ_OP2_INST_RECIP_64 = 0x95, 1189 SQ_OP2_INST_RECIP_CLAMPED_64 = 0x96, 1190 SQ_OP2_INST_RECIPSQRT_64 = 0x97, 1191 SQ_OP2_INST_RECIPSQRT_CLAMPED_64 = 0x98, 1192 SQ_OP2_INST_SQRT_64 = 0x99, 1193 SQ_OP2_INST_FLT_TO_UINT = 0x9a, 1194 SQ_OP2_INST_INT_TO_FLT = 0x9b, 1195 SQ_OP2_INST_UINT_TO_FLT = 0x9c, 1196 SQ_OP2_INST_BFM_INT = 0xa0, 1197 SQ_OP2_INST_FLT32_TO_FLT16 = 0xa2, 1198 SQ_OP2_INST_FLT16_TO_FLT32 = 0xa3, 1199 SQ_OP2_INST_UBYTE0_FLT = 0xa4, 1200 SQ_OP2_INST_UBYTE1_FLT = 0xa5, 1201 SQ_OP2_INST_UBYTE2_FLT = 0xa6, 1202 SQ_OP2_INST_UBYTE3_FLT = 0xa7, 1203 SQ_OP2_INST_BCNT_INT = 0xaa, 1204 SQ_OP2_INST_FFBH_UINT = 0xab, 1205 SQ_OP2_INST_FFBL_INT = 0xac, 1206 SQ_OP2_INST_FFBH_INT = 0xad, 1207 SQ_OP2_INST_FLT_TO_UINT4 = 0xae, 1208 SQ_OP2_INST_DOT_IEEE = 0xaf, 1209 SQ_OP2_INST_FLT_TO_INT_RPI = 0xb0, 1210 SQ_OP2_INST_FLT_TO_INT_FLOOR = 0xb1, 1211 SQ_OP2_INST_MULHI_UINT24 = 0xb2, 1212 SQ_OP2_INST_MBCNT_32HI_INT = 0xb3, 1213 SQ_OP2_INST_OFFSET_TO_FLT = 0xb4, 1214 SQ_OP2_INST_MUL_UINT24 = 0xb5, 1215 SQ_OP2_INST_BCNT_ACCUM_PREV_INT = 0xb6, 1216 SQ_OP2_INST_MBCNT_32LO_ACCUM_PREV_INT = 0xb7, 1217 SQ_OP2_INST_SETE_64 = 0xb8, 1218 SQ_OP2_INST_SETNE_64 = 0xb9, 1219 SQ_OP2_INST_SETGT_64 = 0xba, 1220 SQ_OP2_INST_SETGE_64 = 0xbb, 1221 SQ_OP2_INST_MIN_64 = 0xbc, 1222 SQ_OP2_INST_MAX_64 = 0xbd, 1223 SQ_OP2_INST_DOT4 = 0xbe, 1224 SQ_OP2_INST_DOT4_IEEE = 0xbf, 1225 SQ_OP2_INST_CUBE = 0xc0, 1226 SQ_OP2_INST_MAX4 = 0xc1, 1227 SQ_OP2_INST_FREXP_64 = 0xc4, 1228 SQ_OP2_INST_LDEXP_64 = 0xc5, 1229 SQ_OP2_INST_FRACT_64 = 0xc6, 1230 SQ_OP2_INST_PRED_SETGT_64 = 0xc7, 1231 SQ_OP2_INST_PRED_SETE_64 = 0xc8, 1232 SQ_OP2_INST_PRED_SETGE_64 = 0xc9, 1233 SQ_OP2_INST_MUL_64 = 0xca, 1234 SQ_OP2_INST_ADD_64 = 0xcb, 1235 SQ_OP2_INST_MOVA_INT = 0xcc, 1236 SQ_OP2_INST_FLT64_TO_FLT32 = 0xcd, 1237 SQ_OP2_INST_FLT32_TO_FLT64 = 0xce, 1238 SQ_OP2_INST_SAD_ACCUM_PREV_UINT = 0xcf, 1239 SQ_OP2_INST_DOT = 0xd0, 1240 SQ_OP2_INST_MUL_PREV = 0xd1, 1241 SQ_OP2_INST_MUL_IEEE_PREV = 0xd2, 1242 SQ_OP2_INST_ADD_PREV = 0xd3, 1243 SQ_OP2_INST_MULADD_PREV = 0xd4, 1244 SQ_OP2_INST_MULADD_IEEE_PREV = 0xd5, 1245 SQ_OP2_INST_INTERP_XY = 0xd6, 1246 SQ_OP2_INST_INTERP_ZW = 0xd7, 1247 SQ_OP2_INST_INTERP_X = 0xd8, 1248 SQ_OP2_INST_INTERP_Z = 0xd9, 1249 SQ_OP2_INST_STORE_FLAGS = 0xda, 1250 SQ_OP2_INST_LOAD_STORE_FLAGS = 0xdb, 1251 SQ_OP2_INST_INTERP_LOAD_P0 = 0xe0, 1252 SQ_OP2_INST_INTERP_LOAD_P10 = 0xe1, 1253 SQ_OP2_INST_INTERP_LOAD_P20 = 0xe2, 1254 SQ_CF_WORD1 = 0x00008dfc, 1255 POP_COUNT_mask = 0x07 << 0, 1256 POP_COUNT_shift = 0, 1257 CF_CONST_mask = 0x1f << 3, 1258 CF_CONST_shift = 3, 1259 COND_mask = 0x03 << 8, 1260 COND_shift = 8, 1261 SQ_CF_COND_ACTIVE = 0x00, 1262 SQ_CF_COND_FALSE = 0x01, 1263 SQ_CF_COND_BOOL = 0x02, 1264 SQ_CF_COND_NOT_BOOL = 0x03, 1265 SQ_CF_WORD1__COUNT_mask = 0x3f << 10, 1266 SQ_CF_WORD1__COUNT_shift = 10, 1267/* VALID_PIXEL_MODE_bit = 1 << 20, */ 1268/* END_OF_PROGRAM_bit = 1 << 21, */ 1269 SQ_CF_WORD1__CF_INST_mask = 0xff << 22, 1270 SQ_CF_WORD1__CF_INST_shift = 22, 1271 SQ_CF_INST_NOP = 0x00, 1272 SQ_CF_INST_TC = 0x01, 1273 SQ_CF_INST_VC = 0x02, 1274 SQ_CF_INST_GDS = 0x03, 1275 SQ_CF_INST_LOOP_START = 0x04, 1276 SQ_CF_INST_LOOP_END = 0x05, 1277 SQ_CF_INST_LOOP_START_DX10 = 0x06, 1278 SQ_CF_INST_LOOP_START_NO_AL = 0x07, 1279 SQ_CF_INST_LOOP_CONTINUE = 0x08, 1280 SQ_CF_INST_LOOP_BREAK = 0x09, 1281 SQ_CF_INST_JUMP = 0x0a, 1282 SQ_CF_INST_PUSH = 0x0b, 1283 SQ_CF_INST_ELSE = 0x0d, 1284 SQ_CF_INST_POP = 0x0e, 1285 SQ_CF_INST_CALL = 0x12, 1286 SQ_CF_INST_CALL_FS = 0x13, 1287 SQ_CF_INST_RETURN = 0x14, 1288 SQ_CF_INST_EMIT_VERTEX = 0x15, 1289 SQ_CF_INST_EMIT_CUT_VERTEX = 0x16, 1290 SQ_CF_INST_CUT_VERTEX = 0x17, 1291 SQ_CF_INST_KILL = 0x18, 1292 SQ_CF_INST_WAIT_ACK = 0x1a, 1293 SQ_CF_INST_TC_ACK = 0x1b, 1294 SQ_CF_INST_VC_ACK = 0x1c, 1295 SQ_CF_INST_JUMPTABLE = 0x1d, 1296 SQ_CF_INST_GLOBAL_WAVE_SYNC = 0x1e, 1297 SQ_CF_INST_HALT = 0x1f, 1298/* WHOLE_QUAD_MODE_bit = 1 << 30, */ 1299/* BARRIER_bit = 1 << 31, */ 1300 SQ_VTX_WORD1_SEM = 0x00008dfc, 1301 SEMANTIC_ID_mask = 0xff << 0, 1302 SEMANTIC_ID_shift = 0, 1303 SQ_TEX_WORD0 = 0x00008dfc, 1304 TEX_INST_mask = 0x1f << 0, 1305 TEX_INST_shift = 0, 1306 SQ_TEX_INST_LD = 0x03, 1307 SQ_TEX_INST_GET_TEXTURE_RESINFO = 0x04, 1308 SQ_TEX_INST_GET_NUMBER_OF_SAMPLES = 0x05, 1309 SQ_TEX_INST_GET_LOD = 0x06, 1310 SQ_TEX_INST_GET_GRADIENTS_H = 0x07, 1311 SQ_TEX_INST_GET_GRADIENTS_V = 0x08, 1312 SQ_TEX_INST_SET_TEXTURE_OFFSETS = 0x09, 1313 SQ_TEX_INST_KEEP_GRADIENTS = 0x0a, 1314 SQ_TEX_INST_SET_GRADIENTS_H = 0x0b, 1315 SQ_TEX_INST_SET_GRADIENTS_V = 0x0c, 1316 SQ_TEX_INST_PASS = 0x0d, 1317 SQ_TEX_INST_SAMPLE = 0x10, 1318 SQ_TEX_INST_SAMPLE_L = 0x11, 1319 SQ_TEX_INST_SAMPLE_LB = 0x12, 1320 SQ_TEX_INST_SAMPLE_LZ = 0x13, 1321 SQ_TEX_INST_SAMPLE_G = 0x14, 1322 SQ_TEX_INST_GATHER4 = 0x15, 1323 SQ_TEX_INST_SAMPLE_G_LB = 0x16, 1324 SQ_TEX_INST_GATHER4_O = 0x17, 1325 SQ_TEX_INST_SAMPLE_C = 0x18, 1326 SQ_TEX_INST_SAMPLE_C_L = 0x19, 1327 SQ_TEX_INST_SAMPLE_C_LB = 0x1a, 1328 SQ_TEX_INST_SAMPLE_C_LZ = 0x1b, 1329 SQ_TEX_INST_SAMPLE_C_G = 0x1c, 1330 SQ_TEX_INST_GATHER4_C = 0x1d, 1331 SQ_TEX_INST_SAMPLE_C_G_LB = 0x1e, 1332 SQ_TEX_INST_GATHER4_C_O = 0x1f, 1333 INST_MOD_mask = 0x03 << 5, 1334 INST_MOD_shift = 5, 1335/* FETCH_WHOLE_QUAD_bit = 1 << 7, */ 1336 RESOURCE_ID_mask = 0xff << 8, 1337 RESOURCE_ID_shift = 8, 1338 SQ_TEX_WORD0__SRC_GPR_mask = 0x7f << 16, 1339 SQ_TEX_WORD0__SRC_GPR_shift = 16, 1340/* SRC_REL_bit = 1 << 23, */ 1341 SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24, 1342 RESOURCE_INDEX_MODE_mask = 0x03 << 25, 1343 RESOURCE_INDEX_MODE_shift = 25, 1344/* SQ_CF_INDEX_NONE = 0x00, */ 1345/* SQ_CF_INDEX_0 = 0x01, */ 1346/* SQ_CF_INDEX_1 = 0x02, */ 1347/* SQ_CF_INVALID = 0x03, */ 1348 SAMPLER_INDEX_MODE_mask = 0x03 << 27, 1349 SAMPLER_INDEX_MODE_shift = 27, 1350/* SQ_CF_INDEX_NONE = 0x00, */ 1351/* SQ_CF_INDEX_0 = 0x01, */ 1352/* SQ_CF_INDEX_1 = 0x02, */ 1353/* SQ_CF_INVALID = 0x03, */ 1354 SQ_VTX_WORD1_GPR = 0x00008dfc, 1355 SQ_VTX_WORD1_GPR__DST_GPR_mask = 0x7f << 0, 1356 SQ_VTX_WORD1_GPR__DST_GPR_shift = 0, 1357 SQ_VTX_WORD1_GPR__DST_REL_bit = 1 << 7, 1358 SQ_ALU_WORD1_LDS_IDX_OP = 0x00008dfc, 1359/* SRC2_SEL_mask = 0x1ff << 0, */ 1360/* SRC2_SEL_shift = 0, */ 1361/* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ 1362/* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ 1363/* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ 1364/* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ 1365/* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ 1366/* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ 1367/* SQ_ALU_SRC_TIME_HI = 0xe3, */ 1368/* SQ_ALU_SRC_TIME_LO = 0xe4, */ 1369/* SQ_ALU_SRC_MASK_HI = 0xe5, */ 1370/* SQ_ALU_SRC_MASK_LO = 0xe6, */ 1371/* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ 1372/* SQ_ALU_SRC_SIMD_ID = 0xe8, */ 1373/* SQ_ALU_SRC_SE_ID = 0xe9, */ 1374/* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ 1375/* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ 1376/* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ 1377/* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ 1378/* SQ_ALU_SRC_LOOP_IDX = 0xee, */ 1379/* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ 1380/* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ 1381/* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ 1382/* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ 1383/* SQ_ALU_SRC_1_DBL_L = 0xf4, */ 1384/* SQ_ALU_SRC_1_DBL_M = 0xf5, */ 1385/* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ 1386/* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ 1387/* SQ_ALU_SRC_0 = 0xf8, */ 1388/* SQ_ALU_SRC_1 = 0xf9, */ 1389/* SQ_ALU_SRC_1_INT = 0xfa, */ 1390/* SQ_ALU_SRC_M_1_INT = 0xfb, */ 1391/* SQ_ALU_SRC_0_5 = 0xfc, */ 1392/* SQ_ALU_SRC_LITERAL = 0xfd, */ 1393/* SQ_ALU_SRC_PV = 0xfe, */ 1394/* SQ_ALU_SRC_PS = 0xff, */ 1395/* SRC2_REL_bit = 1 << 9, */ 1396/* SRC2_CHAN_mask = 0x03 << 10, */ 1397/* SRC2_CHAN_shift = 10, */ 1398/* SQ_CHAN_X = 0x00, */ 1399/* SQ_CHAN_Y = 0x01, */ 1400/* SQ_CHAN_Z = 0x02, */ 1401/* SQ_CHAN_W = 0x03, */ 1402 IDX_OFFSET_1_bit = 1 << 12, 1403 SQ_ALU_WORD1_LDS_IDX_OP__ALU_INST_mask = 0x1f << 13, 1404 SQ_ALU_WORD1_LDS_IDX_OP__ALU_INST_shift = 13, 1405/* SQ_OP3_INST_BFE_UINT = 0x04, */ 1406/* SQ_OP3_INST_BFE_INT = 0x05, */ 1407/* SQ_OP3_INST_BFI_INT = 0x06, */ 1408/* SQ_OP3_INST_FMA = 0x07, */ 1409/* SQ_OP3_INST_CNDNE_64 = 0x09, */ 1410/* SQ_OP3_INST_FMA_64 = 0x0a, */ 1411/* SQ_OP3_INST_LERP_UINT = 0x0b, */ 1412/* SQ_OP3_INST_BIT_ALIGN_INT = 0x0c, */ 1413/* SQ_OP3_INST_BYTE_ALIGN_INT = 0x0d, */ 1414/* SQ_OP3_INST_SAD_ACCUM_UINT = 0x0e, */ 1415/* SQ_OP3_INST_SAD_ACCUM_HI_UINT = 0x0f, */ 1416/* SQ_OP3_INST_MULADD_UINT24 = 0x10, */ 1417/* SQ_OP3_INST_LDS_IDX_OP = 0x11, */ 1418/* SQ_OP3_INST_MULADD = 0x14, */ 1419/* SQ_OP3_INST_MULADD_M2 = 0x15, */ 1420/* SQ_OP3_INST_MULADD_M4 = 0x16, */ 1421/* SQ_OP3_INST_MULADD_D2 = 0x17, */ 1422/* SQ_OP3_INST_MULADD_IEEE = 0x18, */ 1423/* SQ_OP3_INST_CNDE = 0x19, */ 1424/* SQ_OP3_INST_CNDGT = 0x1a, */ 1425/* SQ_OP3_INST_CNDGE = 0x1b, */ 1426/* SQ_OP3_INST_CNDE_INT = 0x1c, */ 1427/* SQ_OP3_INST_CNDGT_INT = 0x1d, */ 1428/* SQ_OP3_INST_CNDGE_INT = 0x1e, */ 1429/* SQ_OP3_INST_MUL_LIT = 0x1f, */ 1430/* BANK_SWIZZLE_mask = 0x07 << 18, */ 1431/* BANK_SWIZZLE_shift = 18, */ 1432/* SQ_ALU_VEC_012 = 0x00, */ 1433/* SQ_ALU_VEC_021 = 0x01, */ 1434/* SQ_ALU_VEC_120 = 0x02, */ 1435/* SQ_ALU_VEC_102 = 0x03, */ 1436/* SQ_ALU_VEC_201 = 0x04, */ 1437/* SQ_ALU_VEC_210 = 0x05, */ 1438 LDS_OP_mask = 0x3f << 21, 1439 LDS_OP_shift = 21, 1440/* SQ_DS_INST_ADD = 0x00, */ 1441/* SQ_DS_INST_SUB = 0x01, */ 1442/* SQ_DS_INST_RSUB = 0x02, */ 1443/* SQ_DS_INST_INC = 0x03, */ 1444/* SQ_DS_INST_DEC = 0x04, */ 1445/* SQ_DS_INST_MIN_INT = 0x05, */ 1446/* SQ_DS_INST_MAX_INT = 0x06, */ 1447/* SQ_DS_INST_MIN_UINT = 0x07, */ 1448/* SQ_DS_INST_MAX_UINT = 0x08, */ 1449/* SQ_DS_INST_AND = 0x09, */ 1450/* SQ_DS_INST_OR = 0x0a, */ 1451/* SQ_DS_INST_XOR = 0x0b, */ 1452/* SQ_DS_INST_MSKOR = 0x0c, */ 1453/* SQ_DS_INST_WRITE = 0x0d, */ 1454/* SQ_DS_INST_WRITE_REL = 0x0e, */ 1455/* SQ_DS_INST_WRITE2 = 0x0f, */ 1456/* SQ_DS_INST_CMP_STORE = 0x10, */ 1457/* SQ_DS_INST_CMP_STORE_SPF = 0x11, */ 1458/* SQ_DS_INST_BYTE_WRITE = 0x12, */ 1459/* SQ_DS_INST_SHORT_WRITE = 0x13, */ 1460/* SQ_DS_INST_ADD_RET = 0x20, */ 1461/* SQ_DS_INST_SUB_RET = 0x21, */ 1462/* SQ_DS_INST_RSUB_RET = 0x22, */ 1463/* SQ_DS_INST_INC_RET = 0x23, */ 1464/* SQ_DS_INST_DEC_RET = 0x24, */ 1465/* SQ_DS_INST_MIN_INT_RET = 0x25, */ 1466/* SQ_DS_INST_MAX_INT_RET = 0x26, */ 1467/* SQ_DS_INST_MIN_UINT_RET = 0x27, */ 1468/* SQ_DS_INST_MAX_UINT_RET = 0x28, */ 1469/* SQ_DS_INST_AND_RET = 0x29, */ 1470/* SQ_DS_INST_OR_RET = 0x2a, */ 1471/* SQ_DS_INST_XOR_RET = 0x2b, */ 1472/* SQ_DS_INST_MSKOR_RET = 0x2c, */ 1473/* SQ_DS_INST_XCHG_RET = 0x2d, */ 1474/* SQ_DS_INST_XCHG_REL_RET = 0x2e, */ 1475/* SQ_DS_INST_XCHG2_RET = 0x2f, */ 1476/* SQ_DS_INST_CMP_XCHG_RET = 0x30, */ 1477/* SQ_DS_INST_CMP_XCHG_SPF_RET = 0x31, */ 1478/* SQ_DS_INST_READ_RET = 0x32, */ 1479/* SQ_DS_INST_READ_REL_RET = 0x33, */ 1480/* SQ_DS_INST_READ2_RET = 0x34, */ 1481/* SQ_DS_INST_READWRITE_RET = 0x35, */ 1482/* SQ_DS_INST_BYTE_READ_RET = 0x36, */ 1483/* SQ_DS_INST_UBYTE_READ_RET = 0x37, */ 1484/* SQ_DS_INST_SHORT_READ_RET = 0x38, */ 1485/* SQ_DS_INST_USHORT_READ_RET = 0x39, */ 1486/* SQ_DS_INST_ATOMIC_ORDERED_ALLOC_RET = 0x3f, */ 1487 IDX_OFFSET_0_bit = 1 << 27, 1488 IDX_OFFSET_2_bit = 1 << 28, 1489/* DST_CHAN_mask = 0x03 << 29, */ 1490/* DST_CHAN_shift = 29, */ 1491/* CHAN_X = 0x00, */ 1492/* CHAN_Y = 0x01, */ 1493/* CHAN_Z = 0x02, */ 1494/* CHAN_W = 0x03, */ 1495 IDX_OFFSET_3_bit = 1 << 31, 1496 SQ_CF_ENCODING_WORD1 = 0x00008dfc, 1497 SQ_CF_ENCODING_WORD1__ENCODING_mask = 0x03 << 28, 1498 SQ_CF_ENCODING_WORD1__ENCODING_shift = 28, 1499 SQ_CF_ENCODING_INST_CF = 0x00, 1500 SQ_CF_ENCODING_INST_ALLOC_EXPORT = 0x01, 1501 SQ_CF_ENCODING_INST_ALU0 = 0x02, 1502 SQ_CF_ENCODING_INST_ALU1 = 0x03, 1503 SQ_ALU_WORD0 = 0x00008dfc, 1504/* SRC0_SEL_mask = 0x1ff << 0, */ 1505/* SRC0_SEL_shift = 0, */ 1506/* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ 1507/* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ 1508/* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ 1509/* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ 1510/* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ 1511/* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ 1512/* SQ_ALU_SRC_TIME_HI = 0xe3, */ 1513/* SQ_ALU_SRC_TIME_LO = 0xe4, */ 1514/* SQ_ALU_SRC_MASK_HI = 0xe5, */ 1515/* SQ_ALU_SRC_MASK_LO = 0xe6, */ 1516/* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ 1517/* SQ_ALU_SRC_SIMD_ID = 0xe8, */ 1518/* SQ_ALU_SRC_SE_ID = 0xe9, */ 1519/* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ 1520/* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ 1521/* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ 1522/* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ 1523/* SQ_ALU_SRC_LOOP_IDX = 0xee, */ 1524/* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ 1525/* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ 1526/* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ 1527/* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ 1528/* SQ_ALU_SRC_1_DBL_L = 0xf4, */ 1529/* SQ_ALU_SRC_1_DBL_M = 0xf5, */ 1530/* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ 1531/* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ 1532/* SQ_ALU_SRC_0 = 0xf8, */ 1533/* SQ_ALU_SRC_1 = 0xf9, */ 1534/* SQ_ALU_SRC_1_INT = 0xfa, */ 1535/* SQ_ALU_SRC_M_1_INT = 0xfb, */ 1536/* SQ_ALU_SRC_0_5 = 0xfc, */ 1537/* SQ_ALU_SRC_LITERAL = 0xfd, */ 1538/* SQ_ALU_SRC_PV = 0xfe, */ 1539/* SQ_ALU_SRC_PS = 0xff, */ 1540/* SRC0_REL_bit = 1 << 9, */ 1541/* SRC0_CHAN_mask = 0x03 << 10, */ 1542/* SRC0_CHAN_shift = 10, */ 1543/* SQ_CHAN_X = 0x00, */ 1544/* SQ_CHAN_Y = 0x01, */ 1545/* SQ_CHAN_Z = 0x02, */ 1546/* SQ_CHAN_W = 0x03, */ 1547 SRC0_NEG_bit = 1 << 12, 1548/* SRC1_SEL_mask = 0x1ff << 13, */ 1549/* SRC1_SEL_shift = 13, */ 1550/* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ 1551/* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ 1552/* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ 1553/* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ 1554/* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ 1555/* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ 1556/* SQ_ALU_SRC_TIME_HI = 0xe3, */ 1557/* SQ_ALU_SRC_TIME_LO = 0xe4, */ 1558/* SQ_ALU_SRC_MASK_HI = 0xe5, */ 1559/* SQ_ALU_SRC_MASK_LO = 0xe6, */ 1560/* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ 1561/* SQ_ALU_SRC_SIMD_ID = 0xe8, */ 1562/* SQ_ALU_SRC_SE_ID = 0xe9, */ 1563/* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ 1564/* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ 1565/* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ 1566/* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ 1567/* SQ_ALU_SRC_LOOP_IDX = 0xee, */ 1568/* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ 1569/* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ 1570/* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ 1571/* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ 1572/* SQ_ALU_SRC_1_DBL_L = 0xf4, */ 1573/* SQ_ALU_SRC_1_DBL_M = 0xf5, */ 1574/* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ 1575/* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ 1576/* SQ_ALU_SRC_0 = 0xf8, */ 1577/* SQ_ALU_SRC_1 = 0xf9, */ 1578/* SQ_ALU_SRC_1_INT = 0xfa, */ 1579/* SQ_ALU_SRC_M_1_INT = 0xfb, */ 1580/* SQ_ALU_SRC_0_5 = 0xfc, */ 1581/* SQ_ALU_SRC_LITERAL = 0xfd, */ 1582/* SQ_ALU_SRC_PV = 0xfe, */ 1583/* SQ_ALU_SRC_PS = 0xff, */ 1584/* SRC1_REL_bit = 1 << 22, */ 1585/* SRC1_CHAN_mask = 0x03 << 23, */ 1586/* SRC1_CHAN_shift = 23, */ 1587/* SQ_CHAN_X = 0x00, */ 1588/* SQ_CHAN_Y = 0x01, */ 1589/* SQ_CHAN_Z = 0x02, */ 1590/* SQ_CHAN_W = 0x03, */ 1591 SRC1_NEG_bit = 1 << 25, 1592/* INDEX_MODE_mask = 0x07 << 26, */ 1593/* INDEX_MODE_shift = 26, */ 1594/* SQ_INDEX_AR_X = 0x00, */ 1595/* SQ_INDEX_LOOP = 0x04, */ 1596/* SQ_INDEX_GLOBAL = 0x05, */ 1597/* SQ_INDEX_GLOBAL_AR_X = 0x06, */ 1598/* PRED_SEL_mask = 0x03 << 29, */ 1599/* PRED_SEL_shift = 29, */ 1600/* SQ_PRED_SEL_OFF = 0x00, */ 1601/* SQ_PRED_SEL_ZERO = 0x02, */ 1602/* SQ_PRED_SEL_ONE = 0x03, */ 1603/* LAST_bit = 1 << 31, */ 1604 SQ_MEM_RD_WORD1 = 0x00008dfc, 1605 SQ_MEM_RD_WORD1__DST_GPR_mask = 0x7f << 0, 1606 SQ_MEM_RD_WORD1__DST_GPR_shift = 0, 1607 SQ_MEM_RD_WORD1__DST_REL_bit = 1 << 7, 1608 SQ_MEM_RD_WORD1__DST_SEL_X_mask = 0x07 << 9, 1609 SQ_MEM_RD_WORD1__DST_SEL_X_shift = 9, 1610/* SQ_SEL_X = 0x00, */ 1611/* SQ_SEL_Y = 0x01, */ 1612/* SQ_SEL_Z = 0x02, */ 1613/* SQ_SEL_W = 0x03, */ 1614/* SQ_SEL_0 = 0x04, */ 1615/* SQ_SEL_1 = 0x05, */ 1616/* SQ_SEL_MASK = 0x07, */ 1617 SQ_MEM_RD_WORD1__DST_SEL_Y_mask = 0x07 << 12, 1618 SQ_MEM_RD_WORD1__DST_SEL_Y_shift = 12, 1619/* SQ_SEL_X = 0x00, */ 1620/* SQ_SEL_Y = 0x01, */ 1621/* SQ_SEL_Z = 0x02, */ 1622/* SQ_SEL_W = 0x03, */ 1623/* SQ_SEL_0 = 0x04, */ 1624/* SQ_SEL_1 = 0x05, */ 1625/* SQ_SEL_MASK = 0x07, */ 1626 SQ_MEM_RD_WORD1__DST_SEL_Z_mask = 0x07 << 15, 1627 SQ_MEM_RD_WORD1__DST_SEL_Z_shift = 15, 1628/* SQ_SEL_X = 0x00, */ 1629/* SQ_SEL_Y = 0x01, */ 1630/* SQ_SEL_Z = 0x02, */ 1631/* SQ_SEL_W = 0x03, */ 1632/* SQ_SEL_0 = 0x04, */ 1633/* SQ_SEL_1 = 0x05, */ 1634/* SQ_SEL_MASK = 0x07, */ 1635 SQ_MEM_RD_WORD1__DST_SEL_W_mask = 0x07 << 18, 1636 SQ_MEM_RD_WORD1__DST_SEL_W_shift = 18, 1637/* SQ_SEL_X = 0x00, */ 1638/* SQ_SEL_Y = 0x01, */ 1639/* SQ_SEL_Z = 0x02, */ 1640/* SQ_SEL_W = 0x03, */ 1641/* SQ_SEL_0 = 0x04, */ 1642/* SQ_SEL_1 = 0x05, */ 1643/* SQ_SEL_MASK = 0x07, */ 1644 SQ_MEM_RD_WORD1__DATA_FORMAT_mask = 0x3f << 22, 1645 SQ_MEM_RD_WORD1__DATA_FORMAT_shift = 22, 1646 SQ_MEM_RD_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, 1647 SQ_MEM_RD_WORD1__NUM_FORMAT_ALL_shift = 28, 1648/* SQ_NUM_FORMAT_NORM = 0x00, */ 1649/* SQ_NUM_FORMAT_INT = 0x01, */ 1650/* SQ_NUM_FORMAT_SCALED = 0x02, */ 1651 SQ_MEM_RD_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, 1652 SQ_MEM_RD_WORD1__SRF_MODE_ALL_bit = 1 << 31, 1653 SQ_LSTMP_RING_BASE = 0x00008e10, 1654 SQ_LSTMP_RING_SIZE = 0x00008e14, 1655 SQ_HSTMP_RING_BASE = 0x00008e18, 1656 SQ_HSTMP_RING_SIZE = 0x00008e1c, 1657 SX_EXPORT_BUFFER_SIZES = 0x0000900c, 1658 COLOR_BUFFER_SIZE_mask = 0xff << 0, 1659 COLOR_BUFFER_SIZE_shift = 0, 1660 POSITION_BUFFER_SIZE_mask = 0xff << 8, 1661 POSITION_BUFFER_SIZE_shift = 8, 1662 SMX_BUFFER_SIZE_mask = 0xff << 16, 1663 SMX_BUFFER_SIZE_shift = 16, 1664 SX_MEMORY_EXPORT_BASE = 0x00009010, 1665 SX_MEMORY_EXPORT_SIZE = 0x00009014, 1666 SPI_CONFIG_CNTL = 0x00009100, 1667 GPR_WRITE_PRIORITY_mask = 0x3ffff << 0, 1668 GPR_WRITE_PRIORITY_shift = 0, 1669 SPI_CONFIG_CNTL_1 = 0x0000913c, 1670 VTX_DONE_DELAY_mask = 0x0f << 0, 1671 VTX_DONE_DELAY_shift = 0, 1672 X_DELAY_14_CLKS = 0x00, 1673 X_DELAY_16_CLKS = 0x01, 1674 X_DELAY_18_CLKS = 0x02, 1675 X_DELAY_20_CLKS = 0x03, 1676 X_DELAY_22_CLKS = 0x04, 1677 X_DELAY_24_CLKS = 0x05, 1678 X_DELAY_26_CLKS = 0x06, 1679 X_DELAY_28_CLKS = 0x07, 1680 X_DELAY_30_CLKS = 0x08, 1681 X_DELAY_32_CLKS = 0x09, 1682 X_DELAY_34_CLKS = 0x0a, 1683 X_DELAY_4_CLKS = 0x0b, 1684 X_DELAY_6_CLKS = 0x0c, 1685 X_DELAY_8_CLKS = 0x0d, 1686 X_DELAY_10_CLKS = 0x0e, 1687 X_DELAY_12_CLKS = 0x0f, 1688 INTERP_ONE_PRIM_PER_ROW_bit = 1 << 4, 1689 BC_OPTIMIZE_DISABLE_bit = 1 << 5, 1690 PC_LIMIT_ENABLE_bit = 1 << 6, 1691 PC_LIMIT_STRICT_bit = 1 << 7, 1692 PC_LIMIT_SIZE_mask = 0xffff << 16, 1693 PC_LIMIT_SIZE_shift = 16, 1694 TD_CNTL = 0x00009494, 1695 SYNC_PHASE_SH_mask = 0x03 << 0, 1696 SYNC_PHASE_SH_shift = 0, 1697 PAD_STALL_EN_bit = 1 << 8, 1698 GATHER4_FLOAT_MODE_bit = 1 << 16, 1699 TD_STATUS = 0x00009498, 1700 BUSY_bit = 1 << 31, 1701 TA_CNTL_AUX = 0x00009508, 1702 TA_CNTL_AUX__DISABLE_CUBE_WRAP_bit = 1 << 0, 1703 DISABLE_CUBE_ANISO_bit = 1 << 1, 1704 GETLOD_SELECT_mask = 0x03 << 2, 1705 GETLOD_SELECT_shift = 2, 1706 X_SAMPLER_AND_RESOURCE_CLAMPED_LOD_IN_RESOURCE= 0x00, 1707 DISABLE_IDLE_STALL_bit = 1 << 4, 1708 TEX_COORD_PRECISION_bit = 1 << 28, 1709 LOD_LOG2_TRUNC_bit = 1 << 29, 1710 DB_ZPASS_COUNT_LOW = 0x00009870, 1711 DB_ZPASS_COUNT_HI = 0x00009874, 1712 COUNT_HI_mask = 0x7fffffff << 0, 1713 COUNT_HI_shift = 0, 1714 TD_PS_BORDER_COLOR_INDEX = 0x0000a400, 1715 INDEX_mask = 0x1f << 0, 1716 INDEX_shift = 0, 1717 TD_PS_BORDER_COLOR_RED = 0x0000a404, 1718 TD_PS_BORDER_COLOR_GREEN = 0x0000a408, 1719 TD_PS_BORDER_COLOR_BLUE = 0x0000a40c, 1720 TD_PS_BORDER_COLOR_ALPHA = 0x0000a410, 1721 TD_VS_BORDER_COLOR_INDEX = 0x0000a414, 1722/* INDEX_mask = 0x1f << 0, */ 1723/* INDEX_shift = 0, */ 1724 TD_VS_BORDER_COLOR_RED = 0x0000a418, 1725 TD_VS_BORDER_COLOR_GREEN = 0x0000a41c, 1726 TD_VS_BORDER_COLOR_BLUE = 0x0000a420, 1727 TD_VS_BORDER_COLOR_ALPHA = 0x0000a424, 1728 TD_GS_BORDER_COLOR_INDEX = 0x0000a428, 1729/* INDEX_mask = 0x1f << 0, */ 1730/* INDEX_shift = 0, */ 1731 TD_GS_BORDER_COLOR_RED = 0x0000a42c, 1732 TD_GS_BORDER_COLOR_GREEN = 0x0000a430, 1733 TD_GS_BORDER_COLOR_BLUE = 0x0000a434, 1734 TD_GS_BORDER_COLOR_ALPHA = 0x0000a438, 1735 TD_HS_BORDER_COLOR_INDEX = 0x0000a43c, 1736/* INDEX_mask = 0x1f << 0, */ 1737/* INDEX_shift = 0, */ 1738 TD_HS_BORDER_COLOR_RED = 0x0000a440, 1739 TD_HS_BORDER_COLOR_GREEN = 0x0000a444, 1740 TD_HS_BORDER_COLOR_BLUE = 0x0000a448, 1741 TD_HS_BORDER_COLOR_ALPHA = 0x0000a44c, 1742 TD_LS_BORDER_COLOR_INDEX = 0x0000a450, 1743/* INDEX_mask = 0x1f << 0, */ 1744/* INDEX_shift = 0, */ 1745 TD_LS_BORDER_COLOR_RED = 0x0000a454, 1746 TD_LS_BORDER_COLOR_GREEN = 0x0000a458, 1747 TD_LS_BORDER_COLOR_BLUE = 0x0000a45c, 1748 TD_LS_BORDER_COLOR_ALPHA = 0x0000a460, 1749 TD_CS_BORDER_COLOR_INDEX = 0x0000a464, 1750/* INDEX_mask = 0x1f << 0, */ 1751/* INDEX_shift = 0, */ 1752 TD_CS_BORDER_COLOR_RED = 0x0000a468, 1753 TD_CS_BORDER_COLOR_GREEN = 0x0000a46c, 1754 TD_CS_BORDER_COLOR_BLUE = 0x0000a470, 1755 TD_CS_BORDER_COLOR_ALPHA = 0x0000a474, 1756 DB_RENDER_CONTROL = 0x00028000, 1757 DEPTH_CLEAR_ENABLE_bit = 1 << 0, 1758 STENCIL_CLEAR_ENABLE_bit = 1 << 1, 1759 DEPTH_COPY_bit = 1 << 2, 1760 STENCIL_COPY_bit = 1 << 3, 1761 RESUMMARIZE_ENABLE_bit = 1 << 4, 1762 STENCIL_COMPRESS_DISABLE_bit = 1 << 5, 1763 DEPTH_COMPRESS_DISABLE_bit = 1 << 6, 1764 COPY_CENTROID_bit = 1 << 7, 1765 COPY_SAMPLE_mask = 0x07 << 8, 1766 COPY_SAMPLE_shift = 8, 1767 COLOR_DISABLE_bit = 1 << 12, 1768 DB_COUNT_CONTROL = 0x00028004, 1769 ZPASS_INCREMENT_DISABLE_bit = 1 << 0, 1770 PERFECT_ZPASS_COUNTS_bit = 1 << 1, 1771 DB_DEPTH_VIEW = 0x00028008, 1772 SLICE_START_mask = 0x7ff << 0, 1773 SLICE_START_shift = 0, 1774 SLICE_MAX_mask = 0x7ff << 13, 1775 SLICE_MAX_shift = 13, 1776 Z_READ_ONLY_bit = 1 << 24, 1777 STENCIL_READ_ONLY_bit = 1 << 25, 1778 DB_RENDER_OVERRIDE = 0x0002800c, 1779 FORCE_HIZ_ENABLE_mask = 0x03 << 0, 1780 FORCE_HIZ_ENABLE_shift = 0, 1781 FORCE_OFF = 0x00, 1782 FORCE_ENABLE = 0x01, 1783 FORCE_DISABLE = 0x02, 1784 FORCE_RESERVED = 0x03, 1785 FORCE_HIS_ENABLE0_mask = 0x03 << 2, 1786 FORCE_HIS_ENABLE0_shift = 2, 1787/* FORCE_OFF = 0x00, */ 1788/* FORCE_ENABLE = 0x01, */ 1789/* FORCE_DISABLE = 0x02, */ 1790/* FORCE_RESERVED = 0x03, */ 1791 FORCE_HIS_ENABLE1_mask = 0x03 << 4, 1792 FORCE_HIS_ENABLE1_shift = 4, 1793/* FORCE_OFF = 0x00, */ 1794/* FORCE_ENABLE = 0x01, */ 1795/* FORCE_DISABLE = 0x02, */ 1796/* FORCE_RESERVED = 0x03, */ 1797 FORCE_SHADER_Z_ORDER_bit = 1 << 6, 1798 FAST_Z_DISABLE_bit = 1 << 7, 1799 FAST_STENCIL_DISABLE_bit = 1 << 8, 1800 NOOP_CULL_DISABLE_bit = 1 << 9, 1801 FORCE_COLOR_KILL_bit = 1 << 10, 1802 FORCE_Z_READ_bit = 1 << 11, 1803 FORCE_STENCIL_READ_bit = 1 << 12, 1804 FORCE_FULL_Z_RANGE_mask = 0x03 << 13, 1805 FORCE_FULL_Z_RANGE_shift = 13, 1806/* FORCE_OFF = 0x00, */ 1807/* FORCE_ENABLE = 0x01, */ 1808/* FORCE_DISABLE = 0x02, */ 1809/* FORCE_RESERVED = 0x03, */ 1810 FORCE_QC_SMASK_CONFLICT_bit = 1 << 15, 1811 DISABLE_VIEWPORT_CLAMP_bit = 1 << 16, 1812 IGNORE_SC_ZRANGE_bit = 1 << 17, 1813 DISABLE_FULLY_COVERED_bit = 1 << 18, 1814 FORCE_Z_LIMIT_SUMM_mask = 0x03 << 19, 1815 FORCE_Z_LIMIT_SUMM_shift = 19, 1816 FORCE_SUMM_OFF = 0x00, 1817 FORCE_SUMM_MINZ = 0x01, 1818 FORCE_SUMM_MAXZ = 0x02, 1819 FORCE_SUMM_BOTH = 0x03, 1820 MAX_TILES_IN_DTT_mask = 0x1f << 21, 1821 MAX_TILES_IN_DTT_shift = 21, 1822 DISABLE_PIXEL_RATE_TILES_bit = 1 << 26, 1823 FORCE_Z_DIRTY_bit = 1 << 27, 1824 FORCE_STENCIL_DIRTY_bit = 1 << 28, 1825 FORCE_Z_VALID_bit = 1 << 29, 1826 FORCE_STENCIL_VALID_bit = 1 << 30, 1827 PRESERVE_COMPRESSION_bit = 1 << 31, 1828 DB_RENDER_OVERRIDE2 = 0x00028010, 1829 PARTIAL_SQUAD_LAUNCH_CONTROL_mask = 0x03 << 0, 1830 PARTIAL_SQUAD_LAUNCH_CONTROL_shift = 0, 1831 PSLC_AUTO = 0x00, 1832 PSLC_ON_HANG_ONLY = 0x01, 1833 PSLC_ASAP = 0x02, 1834 PSLC_COUNTDOWN = 0x03, 1835 PARTIAL_SQUAD_LAUNCH_COUNTDOWN_mask = 0x07 << 2, 1836 PARTIAL_SQUAD_LAUNCH_COUNTDOWN_shift = 2, 1837 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO_bit = 1 << 5, 1838 DB_HTILE_DATA_BASE = 0x00028014, 1839 DB_STENCIL_CLEAR = 0x00028028, 1840 DB_STENCIL_CLEAR__CLEAR_mask = 0xff << 0, 1841 DB_STENCIL_CLEAR__CLEAR_shift = 0, 1842 MIN_mask = 0xff << 16, 1843 MIN_shift = 16, 1844 DB_DEPTH_CLEAR = 0x0002802c, 1845 PA_SC_SCREEN_SCISSOR_TL = 0x00028030, 1846 PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0xffff << 0, 1847 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift = 0, 1848 PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0xffff << 16, 1849 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift = 16, 1850 PA_SC_SCREEN_SCISSOR_BR = 0x00028034, 1851 PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0xffff << 0, 1852 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift = 0, 1853 PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0xffff << 16, 1854 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift = 16, 1855 DB_Z_INFO = 0x00028040, 1856 DB_Z_INFO__FORMAT_mask = 0x03 << 0, 1857 DB_Z_INFO__FORMAT_shift = 0, 1858 Z_INVALID = 0x00, 1859 Z_16 = 0x01, 1860 Z_24 = 0x02, 1861 Z_32_FLOAT = 0x03, 1862 DB_Z_INFO__ARRAY_MODE_mask = 0x0f << 4, 1863 DB_Z_INFO__ARRAY_MODE_shift = 4, 1864 ARRAY_LINEAR_GENERAL = 0x00, 1865 ARRAY_LINEAR_ALIGNED = 0x01, 1866 ARRAY_1D_TILED_THIN1 = 0x02, 1867 ARRAY_2D_TILED_THIN1 = 0x04, 1868 DB_Z_INFO__TILE_SPLIT_mask = 0x07 << 8, 1869 DB_Z_INFO__TILE_SPLIT_shift = 8, 1870 ADDR_SURF_TILE_SPLIT_64B = 0x00, 1871 ADDR_SURF_TILE_SPLIT_128B = 0x01, 1872 ADDR_SURF_TILE_SPLIT_256B = 0x02, 1873 ADDR_SURF_TILE_SPLIT_512B = 0x03, 1874 ADDR_SURF_TILE_SPLIT_1KB = 0x04, 1875 ADDR_SURF_TILE_SPLIT_2KB = 0x05, 1876 ADDR_SURF_TILE_SPLIT_4KB = 0x06, 1877 DB_Z_INFO__NUM_BANKS_mask = 0x03 << 12, 1878 DB_Z_INFO__NUM_BANKS_shift = 12, 1879 ADDR_SURF_2_BANK = 0x00, 1880 ADDR_SURF_4_BANK = 0x01, 1881 ADDR_SURF_8_BANK = 0x02, 1882 ADDR_SURF_16_BANK = 0x03, 1883 DB_Z_INFO__BANK_WIDTH_mask = 0x03 << 16, 1884 DB_Z_INFO__BANK_WIDTH_shift = 16, 1885 ADDR_SURF_BANK_WIDTH_1 = 0x00, 1886 ADDR_SURF_BANK_WIDTH_2 = 0x01, 1887 ADDR_SURF_BANK_WIDTH_4 = 0x02, 1888 ADDR_SURF_BANK_WIDTH_8 = 0x03, 1889 DB_Z_INFO__BANK_HEIGHT_mask = 0x03 << 20, 1890 DB_Z_INFO__BANK_HEIGHT_shift = 20, 1891 ADDR_SURF_BANK_HEIGHT_1 = 0x00, 1892 ADDR_SURF_BANK_HEIGHT_2 = 0x01, 1893 ADDR_SURF_BANK_HEIGHT_4 = 0x02, 1894 ADDR_SURF_BANK_HEIGHT_8 = 0x03, 1895 DB_Z_INFO__MACRO_TILE_ASPECT_mask = 0x03 << 24, 1896 DB_Z_INFO__MACRO_TILE_ASPECT_shift = 24, 1897 ADDR_SURF_MACRO_ASPECT_1 = 0x00, 1898 ADDR_SURF_MACRO_ASPECT_2 = 0x01, 1899 ADDR_SURF_MACRO_ASPECT_4 = 0x02, 1900 ADDR_SURF_MACRO_ASPECT_8 = 0x03, 1901 ALLOW_EXPCLEAR_bit = 1 << 27, 1902 READ_SIZE_bit = 1 << 28, 1903 TILE_SURFACE_ENABLE_bit = 1 << 29, 1904 DB_Z_INFO__TILE_COMPACT_bit = 1 << 30, 1905 ZRANGE_PRECISION_bit = 1 << 31, 1906 DB_STENCIL_INFO = 0x00028044, 1907 DB_STENCIL_INFO__FORMAT_bit = 1 << 0, 1908 DB_STENCIL_INFO__TILE_SPLIT_mask = 0x07 << 8, 1909 DB_STENCIL_INFO__TILE_SPLIT_shift = 8, 1910/* ADDR_SURF_TILE_SPLIT_64B = 0x00, */ 1911/* ADDR_SURF_TILE_SPLIT_128B = 0x01, */ 1912/* ADDR_SURF_TILE_SPLIT_256B = 0x02, */ 1913/* ADDR_SURF_TILE_SPLIT_512B = 0x03, */ 1914/* ADDR_SURF_TILE_SPLIT_1KB = 0x04, */ 1915/* ADDR_SURF_TILE_SPLIT_2KB = 0x05, */ 1916/* ADDR_SURF_TILE_SPLIT_4KB = 0x06, */ 1917 DB_Z_READ_BASE = 0x00028048, 1918 DB_STENCIL_READ_BASE = 0x0002804c, 1919 DB_Z_WRITE_BASE = 0x00028050, 1920 DB_STENCIL_WRITE_BASE = 0x00028054, 1921 DB_DEPTH_SIZE = 0x00028058, 1922 PITCH_TILE_MAX_mask = 0x7ff << 0, 1923 PITCH_TILE_MAX_shift = 0, 1924 HEIGHT_TILE_MAX_mask = 0x7ff << 11, 1925 HEIGHT_TILE_MAX_shift = 11, 1926 DB_DEPTH_SLICE = 0x0002805c, 1927 SLICE_TILE_MAX_mask = 0x3fffff << 0, 1928 SLICE_TILE_MAX_shift = 0, 1929 SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x00028140, 1930 SQ_ALU_CONST_BUFFER_SIZE_PS_0_num = 16, 1931 SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_mask = 0x1ff << 0, 1932 SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_shift = 0, 1933 SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x00028180, 1934 SQ_ALU_CONST_BUFFER_SIZE_VS_0_num = 16, 1935 SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_mask = 0x1ff << 0, 1936 SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_shift = 0, 1937 SQ_ALU_CONST_BUFFER_SIZE_GS_0 = 0x000281c0, 1938 SQ_ALU_CONST_BUFFER_SIZE_GS_0_num = 16, 1939 SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_mask = 0x1ff << 0, 1940 SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_shift = 0, 1941 PA_SC_WINDOW_OFFSET = 0x00028200, 1942 WINDOW_X_OFFSET_mask = 0xffff << 0, 1943 WINDOW_X_OFFSET_shift = 0, 1944 WINDOW_Y_OFFSET_mask = 0xffff << 16, 1945 WINDOW_Y_OFFSET_shift = 16, 1946 PA_SC_WINDOW_SCISSOR_TL = 0x00028204, 1947 PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x7fff << 0, 1948 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift = 0, 1949 PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, 1950 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift = 16, 1951 WINDOW_OFFSET_DISABLE_bit = 1 << 31, 1952 PA_SC_WINDOW_SCISSOR_BR = 0x00028208, 1953 PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x7fff << 0, 1954 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift = 0, 1955 PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, 1956 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift = 16, 1957 PA_SC_CLIPRECT_RULE = 0x0002820c, 1958 CLIP_RULE_mask = 0xffff << 0, 1959 CLIP_RULE_shift = 0, 1960 PA_SC_CLIPRECT_0_TL = 0x00028210, 1961 PA_SC_CLIPRECT_0_TL_num = 4, 1962 PA_SC_CLIPRECT_0_TL_offset = 8, 1963 PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x7fff << 0, 1964 PA_SC_CLIPRECT_0_TL__TL_X_shift = 0, 1965 PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x7fff << 16, 1966 PA_SC_CLIPRECT_0_TL__TL_Y_shift = 16, 1967 PA_SC_CLIPRECT_0_BR = 0x00028214, 1968 PA_SC_CLIPRECT_0_BR_num = 4, 1969 PA_SC_CLIPRECT_0_BR_offset = 8, 1970 PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x7fff << 0, 1971 PA_SC_CLIPRECT_0_BR__BR_X_shift = 0, 1972 PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x7fff << 16, 1973 PA_SC_CLIPRECT_0_BR__BR_Y_shift = 16, 1974 PA_SC_EDGERULE = 0x00028230, 1975 ER_TRI_mask = 0x0f << 0, 1976 ER_TRI_shift = 0, 1977 ER_POINT_mask = 0x0f << 4, 1978 ER_POINT_shift = 4, 1979 ER_RECT_mask = 0x0f << 8, 1980 ER_RECT_shift = 8, 1981 ER_LINE_LR_mask = 0x3f << 12, 1982 ER_LINE_LR_shift = 12, 1983 ER_LINE_RL_mask = 0x3f << 18, 1984 ER_LINE_RL_shift = 18, 1985 ER_LINE_TB_mask = 0x0f << 24, 1986 ER_LINE_TB_shift = 24, 1987 ER_LINE_BT_mask = 0x0f << 28, 1988 ER_LINE_BT_shift = 28, 1989 PA_SU_HARDWARE_SCREEN_OFFSET = 0x00028234, 1990 HW_SCREEN_OFFSET_X_mask = 0x1f << 0, 1991 HW_SCREEN_OFFSET_X_shift = 0, 1992 HW_SCREEN_OFFSET_Y_mask = 0x1f << 8, 1993 HW_SCREEN_OFFSET_Y_shift = 8, 1994 CB_TARGET_MASK = 0x00028238, 1995 TARGET0_ENABLE_mask = 0x0f << 0, 1996 TARGET0_ENABLE_shift = 0, 1997 TARGET1_ENABLE_mask = 0x0f << 4, 1998 TARGET1_ENABLE_shift = 4, 1999 TARGET2_ENABLE_mask = 0x0f << 8, 2000 TARGET2_ENABLE_shift = 8, 2001 TARGET3_ENABLE_mask = 0x0f << 12, 2002 TARGET3_ENABLE_shift = 12, 2003 TARGET4_ENABLE_mask = 0x0f << 16, 2004 TARGET4_ENABLE_shift = 16, 2005 TARGET5_ENABLE_mask = 0x0f << 20, 2006 TARGET5_ENABLE_shift = 20, 2007 TARGET6_ENABLE_mask = 0x0f << 24, 2008 TARGET6_ENABLE_shift = 24, 2009 TARGET7_ENABLE_mask = 0x0f << 28, 2010 TARGET7_ENABLE_shift = 28, 2011 CB_SHADER_MASK = 0x0002823c, 2012 OUTPUT0_ENABLE_mask = 0x0f << 0, 2013 OUTPUT0_ENABLE_shift = 0, 2014 OUTPUT1_ENABLE_mask = 0x0f << 4, 2015 OUTPUT1_ENABLE_shift = 4, 2016 OUTPUT2_ENABLE_mask = 0x0f << 8, 2017 OUTPUT2_ENABLE_shift = 8, 2018 OUTPUT3_ENABLE_mask = 0x0f << 12, 2019 OUTPUT3_ENABLE_shift = 12, 2020 OUTPUT4_ENABLE_mask = 0x0f << 16, 2021 OUTPUT4_ENABLE_shift = 16, 2022 OUTPUT5_ENABLE_mask = 0x0f << 20, 2023 OUTPUT5_ENABLE_shift = 20, 2024 OUTPUT6_ENABLE_mask = 0x0f << 24, 2025 OUTPUT6_ENABLE_shift = 24, 2026 OUTPUT7_ENABLE_mask = 0x0f << 28, 2027 OUTPUT7_ENABLE_shift = 28, 2028 PA_SC_GENERIC_SCISSOR_TL = 0x00028240, 2029 PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x7fff << 0, 2030 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift = 0, 2031 PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, 2032 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift = 16, 2033/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ 2034 PA_SC_GENERIC_SCISSOR_BR = 0x00028244, 2035 PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x7fff << 0, 2036 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift = 0, 2037 PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, 2038 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift = 16, 2039 PA_SC_VPORT_SCISSOR_0_TL = 0x00028250, 2040 PA_SC_VPORT_SCISSOR_0_TL_num = 16, 2041 PA_SC_VPORT_SCISSOR_0_TL_offset = 8, 2042 PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x7fff << 0, 2043 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift = 0, 2044 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x7fff << 16, 2045 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift = 16, 2046/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ 2047 PA_SC_VPORT_SCISSOR_0_BR = 0x00028254, 2048 PA_SC_VPORT_SCISSOR_0_BR_num = 16, 2049 PA_SC_VPORT_SCISSOR_0_BR_offset = 8, 2050 PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x7fff << 0, 2051 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift = 0, 2052 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x7fff << 16, 2053 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift = 16, 2054 PA_SC_VPORT_ZMIN_0 = 0x000282d0, 2055 PA_SC_VPORT_ZMIN_0_num = 16, 2056 PA_SC_VPORT_ZMIN_0_offset = 8, 2057 PA_SC_VPORT_ZMAX_0 = 0x000282d4, 2058 PA_SC_VPORT_ZMAX_0_num = 16, 2059 PA_SC_VPORT_ZMAX_0_offset = 8, 2060 SX_MISC = 0x00028350, 2061 MULTIPASS_bit = 1 << 0, 2062 SQ_VTX_SEMANTIC_0 = 0x00028380, 2063 SQ_VTX_SEMANTIC_0_num = 32, 2064/* SEMANTIC_ID_mask = 0xff << 0, */ 2065/* SEMANTIC_ID_shift = 0, */ 2066 VGT_MAX_VTX_INDX = 0x00028400, 2067 VGT_MIN_VTX_INDX = 0x00028404, 2068 VGT_INDX_OFFSET = 0x00028408, 2069 VGT_MULTI_PRIM_IB_RESET_INDX = 0x0002840c, 2070 SX_ALPHA_TEST_CONTROL = 0x00028410, 2071 ALPHA_FUNC_mask = 0x07 << 0, 2072 ALPHA_FUNC_shift = 0, 2073 REF_NEVER = 0x00, 2074 REF_LESS = 0x01, 2075 REF_EQUAL = 0x02, 2076 REF_LEQUAL = 0x03, 2077 REF_GREATER = 0x04, 2078 REF_NOTEQUAL = 0x05, 2079 REF_GEQUAL = 0x06, 2080 REF_ALWAYS = 0x07, 2081 ALPHA_TEST_ENABLE_bit = 1 << 3, 2082 ALPHA_TEST_BYPASS_bit = 1 << 8, 2083 CB_BLEND_RED = 0x00028414, 2084 CB_BLEND_GREEN = 0x00028418, 2085 CB_BLEND_BLUE = 0x0002841c, 2086 CB_BLEND_ALPHA = 0x00028420, 2087 DB_STENCILREFMASK = 0x00028430, 2088 STENCILREF_mask = 0xff << 0, 2089 STENCILREF_shift = 0, 2090 STENCILMASK_mask = 0xff << 8, 2091 STENCILMASK_shift = 8, 2092 STENCILWRITEMASK_mask = 0xff << 16, 2093 STENCILWRITEMASK_shift = 16, 2094 DB_STENCILREFMASK_BF = 0x00028434, 2095 STENCILREF_BF_mask = 0xff << 0, 2096 STENCILREF_BF_shift = 0, 2097 STENCILMASK_BF_mask = 0xff << 8, 2098 STENCILMASK_BF_shift = 8, 2099 STENCILWRITEMASK_BF_mask = 0xff << 16, 2100 STENCILWRITEMASK_BF_shift = 16, 2101 SX_ALPHA_REF = 0x00028438, 2102 PA_CL_VPORT_XSCALE_0 = 0x0002843c, 2103 PA_CL_VPORT_XSCALE_0_num = 16, 2104 PA_CL_VPORT_XSCALE_0_offset = 24, 2105 PA_CL_VPORT_XOFFSET_0 = 0x00028440, 2106 PA_CL_VPORT_XOFFSET_0_num = 16, 2107 PA_CL_VPORT_XOFFSET_0_offset = 24, 2108 PA_CL_VPORT_YSCALE_0 = 0x00028444, 2109 PA_CL_VPORT_YSCALE_0_num = 16, 2110 PA_CL_VPORT_YSCALE_0_offset = 24, 2111 PA_CL_VPORT_YOFFSET_0 = 0x00028448, 2112 PA_CL_VPORT_YOFFSET_0_num = 16, 2113 PA_CL_VPORT_YOFFSET_0_offset = 24, 2114 PA_CL_VPORT_ZSCALE_0 = 0x0002844c, 2115 PA_CL_VPORT_ZSCALE_0_num = 16, 2116 PA_CL_VPORT_ZSCALE_0_offset = 24, 2117 PA_CL_VPORT_ZOFFSET_0 = 0x00028450, 2118 PA_CL_VPORT_ZOFFSET_0_num = 16, 2119 PA_CL_VPORT_ZOFFSET_0_offset = 24, 2120 PA_CL_UCP_0_X = 0x000285bc, 2121 PA_CL_UCP_0_X_num = 6, 2122 PA_CL_UCP_0_X_offset = 16, 2123 PA_CL_UCP_0_Y = 0x000285c0, 2124 PA_CL_UCP_0_Y_num = 6, 2125 PA_CL_UCP_0_Y_offset = 16, 2126 PA_CL_UCP_0_Z = 0x000285c4, 2127 PA_CL_UCP_0_Z_num = 6, 2128 PA_CL_UCP_0_Z_offset = 16, 2129 PA_CL_UCP_0_W = 0x000285c8, 2130 PA_CL_UCP_0_W_num = 6, 2131 PA_CL_UCP_0_W_offset = 16, 2132 SPI_VS_OUT_ID_0 = 0x0002861c, 2133 SPI_VS_OUT_ID_0_num = 10, 2134 SEMANTIC_0_mask = 0xff << 0, 2135 SEMANTIC_0_shift = 0, 2136 SEMANTIC_1_mask = 0xff << 8, 2137 SEMANTIC_1_shift = 8, 2138 SEMANTIC_2_mask = 0xff << 16, 2139 SEMANTIC_2_shift = 16, 2140 SEMANTIC_3_mask = 0xff << 24, 2141 SEMANTIC_3_shift = 24, 2142 SPI_PS_INPUT_CNTL_0 = 0x00028644, 2143 SPI_PS_INPUT_CNTL_0_num = 32, 2144 SEMANTIC_mask = 0xff << 0, 2145 SEMANTIC_shift = 0, 2146 DEFAULT_VAL_mask = 0x03 << 8, 2147 DEFAULT_VAL_shift = 8, 2148 X_0_0F = 0x00, 2149 FLAT_SHADE_bit = 1 << 10, 2150 CYL_WRAP_mask = 0x0f << 13, 2151 CYL_WRAP_shift = 13, 2152 PT_SPRITE_TEX_bit = 1 << 17, 2153 SPI_VS_OUT_CONFIG = 0x000286c4, 2154 VS_PER_COMPONENT_bit = 1 << 0, 2155 VS_EXPORT_COUNT_mask = 0x1f << 1, 2156 VS_EXPORT_COUNT_shift = 1, 2157 VS_EXPORTS_FOG_bit = 1 << 8, 2158 VS_OUT_FOG_VEC_ADDR_mask = 0x1f << 9, 2159 VS_OUT_FOG_VEC_ADDR_shift = 9, 2160 SPI_PS_IN_CONTROL_0 = 0x000286cc, 2161 NUM_INTERP_mask = 0x3f << 0, 2162 NUM_INTERP_shift = 0, 2163 POSITION_ENA_bit = 1 << 8, 2164 POSITION_CENTROID_bit = 1 << 9, 2165 POSITION_ADDR_mask = 0x1f << 10, 2166 POSITION_ADDR_shift = 10, 2167 PARAM_GEN_mask = 0x0f << 15, 2168 PARAM_GEN_shift = 15, 2169 PERSP_GRADIENT_ENA_bit = 1 << 28, 2170 LINEAR_GRADIENT_ENA_bit = 1 << 29, 2171 POSITION_SAMPLE_bit = 1 << 30, 2172 SPI_PS_IN_CONTROL_1 = 0x000286d0, 2173 FRONT_FACE_ENA_bit = 1 << 8, 2174 FRONT_FACE_ALL_BITS_bit = 1 << 11, 2175 FRONT_FACE_ADDR_mask = 0x1f << 12, 2176 FRONT_FACE_ADDR_shift = 12, 2177 FOG_ADDR_mask = 0x7f << 17, 2178 FOG_ADDR_shift = 17, 2179 FIXED_PT_POSITION_ENA_bit = 1 << 24, 2180 FIXED_PT_POSITION_ADDR_mask = 0x1f << 25, 2181 FIXED_PT_POSITION_ADDR_shift = 25, 2182 POSITION_ULC_bit = 1 << 30, 2183 SPI_INTERP_CONTROL_0 = 0x000286d4, 2184 FLAT_SHADE_ENA_bit = 1 << 0, 2185 PNT_SPRITE_ENA_bit = 1 << 1, 2186 PNT_SPRITE_OVRD_X_mask = 0x07 << 2, 2187 PNT_SPRITE_OVRD_X_shift = 2, 2188 SPI_PNT_SPRITE_SEL_0 = 0x00, 2189 SPI_PNT_SPRITE_SEL_1 = 0x01, 2190 SPI_PNT_SPRITE_SEL_S = 0x02, 2191 SPI_PNT_SPRITE_SEL_T = 0x03, 2192 SPI_PNT_SPRITE_SEL_NONE = 0x04, 2193 PNT_SPRITE_OVRD_Y_mask = 0x07 << 5, 2194 PNT_SPRITE_OVRD_Y_shift = 5, 2195/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ 2196/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ 2197/* SPI_PNT_SPRITE_SEL_S = 0x02, */ 2198/* SPI_PNT_SPRITE_SEL_T = 0x03, */ 2199/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ 2200 PNT_SPRITE_OVRD_Z_mask = 0x07 << 8, 2201 PNT_SPRITE_OVRD_Z_shift = 8, 2202/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ 2203/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ 2204/* SPI_PNT_SPRITE_SEL_S = 0x02, */ 2205/* SPI_PNT_SPRITE_SEL_T = 0x03, */ 2206/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ 2207 PNT_SPRITE_OVRD_W_mask = 0x07 << 11, 2208 PNT_SPRITE_OVRD_W_shift = 11, 2209/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ 2210/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ 2211/* SPI_PNT_SPRITE_SEL_S = 0x02, */ 2212/* SPI_PNT_SPRITE_SEL_T = 0x03, */ 2213/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ 2214 PNT_SPRITE_TOP_1_bit = 1 << 14, 2215 SPI_INPUT_Z = 0x000286d8, 2216 PROVIDE_Z_TO_SPI_bit = 1 << 0, 2217 SPI_FOG_CNTL = 0x000286dc, 2218 PASS_FOG_THROUGH_PS_bit = 1 << 0, 2219 SPI_BARYC_CNTL = 0x000286e0, 2220 PERSP_CENTER_ENA_mask = 0x03 << 0, 2221 PERSP_CENTER_ENA_shift = 0, 2222 X_OFF = 0x00, 2223 PERSP_CENTER_ENA__X_ON_AT_CENTER = 0x01, 2224 PERSP_CENTER_ENA__X_ON_AT_CENTROID = 0x02, 2225 PERSP_CENTROID_ENA_mask = 0x03 << 4, 2226 PERSP_CENTROID_ENA_shift = 4, 2227/* X_OFF = 0x00, */ 2228 PERSP_CENTROID_ENA__X_ON_AT_CENTROID = 0x01, 2229 PERSP_CENTROID_ENA__X_ON_AT_CENTER = 0x02, 2230 PERSP_SAMPLE_ENA_mask = 0x03 << 8, 2231 PERSP_SAMPLE_ENA_shift = 8, 2232/* X_OFF = 0x00, */ 2233 PERSP_PULL_MODEL_ENA_mask = 0x03 << 12, 2234 PERSP_PULL_MODEL_ENA_shift = 12, 2235/* X_OFF = 0x00, */ 2236 LINEAR_CENTER_ENA_mask = 0x03 << 16, 2237 LINEAR_CENTER_ENA_shift = 16, 2238/* X_OFF = 0x00, */ 2239 LINEAR_CENTER_ENA__X_ON_AT_CENTER = 0x01, 2240 LINEAR_CENTER_ENA__X_ON_AT_CENTROID = 0x02, 2241 LINEAR_CENTROID_ENA_mask = 0x03 << 20, 2242 LINEAR_CENTROID_ENA_shift = 20, 2243/* X_OFF = 0x00, */ 2244 LINEAR_CENTROID_ENA__X_ON_AT_CENTROID = 0x01, 2245 LINEAR_CENTROID_ENA__X_ON_AT_CENTER = 0x02, 2246 LINEAR_SAMPLE_ENA_mask = 0x03 << 24, 2247 LINEAR_SAMPLE_ENA_shift = 24, 2248/* X_OFF = 0x00, */ 2249 SPI_PS_IN_CONTROL_2 = 0x000286e4, 2250 LINE_STIPPLE_TEX_ADDR_mask = 0xff << 0, 2251 LINE_STIPPLE_TEX_ADDR_shift = 0, 2252 LINE_STIPPLE_TEX_ENA_bit = 1 << 8, 2253 CB_BLEND0_CONTROL = 0x00028780, 2254 CB_BLEND0_CONTROL_num = 8, 2255 COLOR_SRCBLEND_mask = 0x1f << 0, 2256 COLOR_SRCBLEND_shift = 0, 2257 BLEND_ZERO = 0x00, 2258 BLEND_ONE = 0x01, 2259 BLEND_SRC_COLOR = 0x02, 2260 BLEND_ONE_MINUS_SRC_COLOR = 0x03, 2261 BLEND_SRC_ALPHA = 0x04, 2262 BLEND_ONE_MINUS_SRC_ALPHA = 0x05, 2263 BLEND_DST_ALPHA = 0x06, 2264 BLEND_ONE_MINUS_DST_ALPHA = 0x07, 2265 BLEND_DST_COLOR = 0x08, 2266 BLEND_ONE_MINUS_DST_COLOR = 0x09, 2267 BLEND_SRC_ALPHA_SATURATE = 0x0a, 2268 BLEND_BOTH_SRC_ALPHA = 0x0b, 2269 BLEND_BOTH_INV_SRC_ALPHA = 0x0c, 2270 BLEND_CONSTANT_COLOR = 0x0d, 2271 BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, 2272 BLEND_SRC1_COLOR = 0x0f, 2273 BLEND_INV_SRC1_COLOR = 0x10, 2274 BLEND_SRC1_ALPHA = 0x11, 2275 BLEND_INV_SRC1_ALPHA = 0x12, 2276 BLEND_CONSTANT_ALPHA = 0x13, 2277 BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, 2278 COLOR_COMB_FCN_mask = 0x07 << 5, 2279 COLOR_COMB_FCN_shift = 5, 2280 COMB_DST_PLUS_SRC = 0x00, 2281 COMB_SRC_MINUS_DST = 0x01, 2282 COMB_MIN_DST_SRC = 0x02, 2283 COMB_MAX_DST_SRC = 0x03, 2284 COMB_DST_MINUS_SRC = 0x04, 2285 COLOR_DESTBLEND_mask = 0x1f << 8, 2286 COLOR_DESTBLEND_shift = 8, 2287/* BLEND_ZERO = 0x00, */ 2288/* BLEND_ONE = 0x01, */ 2289/* BLEND_SRC_COLOR = 0x02, */ 2290/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ 2291/* BLEND_SRC_ALPHA = 0x04, */ 2292/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ 2293/* BLEND_DST_ALPHA = 0x06, */ 2294/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ 2295/* BLEND_DST_COLOR = 0x08, */ 2296/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ 2297/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ 2298/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ 2299/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ 2300/* BLEND_CONSTANT_COLOR = 0x0d, */ 2301/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ 2302/* BLEND_SRC1_COLOR = 0x0f, */ 2303/* BLEND_INV_SRC1_COLOR = 0x10, */ 2304/* BLEND_SRC1_ALPHA = 0x11, */ 2305/* BLEND_INV_SRC1_ALPHA = 0x12, */ 2306/* BLEND_CONSTANT_ALPHA = 0x13, */ 2307/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ 2308 ALPHA_SRCBLEND_mask = 0x1f << 16, 2309 ALPHA_SRCBLEND_shift = 16, 2310/* BLEND_ZERO = 0x00, */ 2311/* BLEND_ONE = 0x01, */ 2312/* BLEND_SRC_COLOR = 0x02, */ 2313/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ 2314/* BLEND_SRC_ALPHA = 0x04, */ 2315/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ 2316/* BLEND_DST_ALPHA = 0x06, */ 2317/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ 2318/* BLEND_DST_COLOR = 0x08, */ 2319/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ 2320/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ 2321/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ 2322/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ 2323/* BLEND_CONSTANT_COLOR = 0x0d, */ 2324/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ 2325/* BLEND_SRC1_COLOR = 0x0f, */ 2326/* BLEND_INV_SRC1_COLOR = 0x10, */ 2327/* BLEND_SRC1_ALPHA = 0x11, */ 2328/* BLEND_INV_SRC1_ALPHA = 0x12, */ 2329/* BLEND_CONSTANT_ALPHA = 0x13, */ 2330/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ 2331 ALPHA_COMB_FCN_mask = 0x07 << 21, 2332 ALPHA_COMB_FCN_shift = 21, 2333/* COMB_DST_PLUS_SRC = 0x00, */ 2334/* COMB_SRC_MINUS_DST = 0x01, */ 2335/* COMB_MIN_DST_SRC = 0x02, */ 2336/* COMB_MAX_DST_SRC = 0x03, */ 2337/* COMB_DST_MINUS_SRC = 0x04, */ 2338 ALPHA_DESTBLEND_mask = 0x1f << 24, 2339 ALPHA_DESTBLEND_shift = 24, 2340/* BLEND_ZERO = 0x00, */ 2341/* BLEND_ONE = 0x01, */ 2342/* BLEND_SRC_COLOR = 0x02, */ 2343/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ 2344/* BLEND_SRC_ALPHA = 0x04, */ 2345/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ 2346/* BLEND_DST_ALPHA = 0x06, */ 2347/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ 2348/* BLEND_DST_COLOR = 0x08, */ 2349/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ 2350/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ 2351/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ 2352/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ 2353/* BLEND_CONSTANT_COLOR = 0x0d, */ 2354/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ 2355/* BLEND_SRC1_COLOR = 0x0f, */ 2356/* BLEND_INV_SRC1_COLOR = 0x10, */ 2357/* BLEND_SRC1_ALPHA = 0x11, */ 2358/* BLEND_INV_SRC1_ALPHA = 0x12, */ 2359/* BLEND_CONSTANT_ALPHA = 0x13, */ 2360/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ 2361 SEPARATE_ALPHA_BLEND_bit = 1 << 29, 2362 CB_BLEND0_CONTROL__ENABLE_bit = 1 << 30, 2363 PA_CL_POINT_X_RAD = 0x000287d4, 2364 PA_CL_POINT_Y_RAD = 0x000287d8, 2365 PA_CL_POINT_SIZE = 0x000287dc, 2366 PA_CL_POINT_CULL_RAD = 0x000287e0, 2367 VGT_DMA_BASE_HI = 0x000287e4, 2368 VGT_DMA_BASE_HI__BASE_ADDR_mask = 0xff << 0, 2369 VGT_DMA_BASE_HI__BASE_ADDR_shift = 0, 2370 VGT_DMA_BASE = 0x000287e8, 2371 VGT_DRAW_INITIATOR = 0x000287f0, 2372 SOURCE_SELECT_mask = 0x03 << 0, 2373 SOURCE_SELECT_shift = 0, 2374 DI_SRC_SEL_DMA = 0x00, 2375 DI_SRC_SEL_IMMEDIATE = 0x01, 2376 DI_SRC_SEL_AUTO_INDEX = 0x02, 2377 DI_SRC_SEL_RESERVED = 0x03, 2378 MAJOR_MODE_mask = 0x03 << 2, 2379 MAJOR_MODE_shift = 2, 2380 DI_MAJOR_MODE_0 = 0x00, 2381 DI_MAJOR_MODE_1 = 0x01, 2382 NOT_EOP_bit = 1 << 5, 2383 USE_OPAQUE_bit = 1 << 6, 2384 VGT_IMMED_DATA = 0x000287f4, 2385 VGT_EVENT_ADDRESS_REG = 0x000287f8, 2386 ADDRESS_LOW_mask = 0xfffffff << 0, 2387 ADDRESS_LOW_shift = 0, 2388 DB_DEPTH_CONTROL = 0x00028800, 2389 STENCIL_ENABLE_bit = 1 << 0, 2390 Z_ENABLE_bit = 1 << 1, 2391 Z_WRITE_ENABLE_bit = 1 << 2, 2392 ZFUNC_mask = 0x07 << 4, 2393 ZFUNC_shift = 4, 2394 FRAG_NEVER = 0x00, 2395 FRAG_LESS = 0x01, 2396 FRAG_EQUAL = 0x02, 2397 FRAG_LEQUAL = 0x03, 2398 FRAG_GREATER = 0x04, 2399 FRAG_NOTEQUAL = 0x05, 2400 FRAG_GEQUAL = 0x06, 2401 FRAG_ALWAYS = 0x07, 2402 BACKFACE_ENABLE_bit = 1 << 7, 2403 STENCILFUNC_mask = 0x07 << 8, 2404 STENCILFUNC_shift = 8, 2405/* REF_NEVER = 0x00, */ 2406/* REF_LESS = 0x01, */ 2407/* REF_EQUAL = 0x02, */ 2408/* REF_LEQUAL = 0x03, */ 2409/* REF_GREATER = 0x04, */ 2410/* REF_NOTEQUAL = 0x05, */ 2411/* REF_GEQUAL = 0x06, */ 2412/* REF_ALWAYS = 0x07, */ 2413 STENCILFAIL_mask = 0x07 << 11, 2414 STENCILFAIL_shift = 11, 2415 STENCIL_KEEP = 0x00, 2416 STENCIL_ZERO = 0x01, 2417 STENCIL_REPLACE = 0x02, 2418 STENCIL_INCR_CLAMP = 0x03, 2419 STENCIL_DECR_CLAMP = 0x04, 2420 STENCIL_INVERT = 0x05, 2421 STENCIL_INCR_WRAP = 0x06, 2422 STENCIL_DECR_WRAP = 0x07, 2423 STENCILZPASS_mask = 0x07 << 14, 2424 STENCILZPASS_shift = 14, 2425/* STENCIL_KEEP = 0x00, */ 2426/* STENCIL_ZERO = 0x01, */ 2427/* STENCIL_REPLACE = 0x02, */ 2428/* STENCIL_INCR_CLAMP = 0x03, */ 2429/* STENCIL_DECR_CLAMP = 0x04, */ 2430/* STENCIL_INVERT = 0x05, */ 2431/* STENCIL_INCR_WRAP = 0x06, */ 2432/* STENCIL_DECR_WRAP = 0x07, */ 2433 STENCILZFAIL_mask = 0x07 << 17, 2434 STENCILZFAIL_shift = 17, 2435/* STENCIL_KEEP = 0x00, */ 2436/* STENCIL_ZERO = 0x01, */ 2437/* STENCIL_REPLACE = 0x02, */ 2438/* STENCIL_INCR_CLAMP = 0x03, */ 2439/* STENCIL_DECR_CLAMP = 0x04, */ 2440/* STENCIL_INVERT = 0x05, */ 2441/* STENCIL_INCR_WRAP = 0x06, */ 2442/* STENCIL_DECR_WRAP = 0x07, */ 2443 STENCILFUNC_BF_mask = 0x07 << 20, 2444 STENCILFUNC_BF_shift = 20, 2445/* REF_NEVER = 0x00, */ 2446/* REF_LESS = 0x01, */ 2447/* REF_EQUAL = 0x02, */ 2448/* REF_LEQUAL = 0x03, */ 2449/* REF_GREATER = 0x04, */ 2450/* REF_NOTEQUAL = 0x05, */ 2451/* REF_GEQUAL = 0x06, */ 2452/* REF_ALWAYS = 0x07, */ 2453 STENCILFAIL_BF_mask = 0x07 << 23, 2454 STENCILFAIL_BF_shift = 23, 2455/* STENCIL_KEEP = 0x00, */ 2456/* STENCIL_ZERO = 0x01, */ 2457/* STENCIL_REPLACE = 0x02, */ 2458/* STENCIL_INCR_CLAMP = 0x03, */ 2459/* STENCIL_DECR_CLAMP = 0x04, */ 2460/* STENCIL_INVERT = 0x05, */ 2461/* STENCIL_INCR_WRAP = 0x06, */ 2462/* STENCIL_DECR_WRAP = 0x07, */ 2463 STENCILZPASS_BF_mask = 0x07 << 26, 2464 STENCILZPASS_BF_shift = 26, 2465/* STENCIL_KEEP = 0x00, */ 2466/* STENCIL_ZERO = 0x01, */ 2467/* STENCIL_REPLACE = 0x02, */ 2468/* STENCIL_INCR_CLAMP = 0x03, */ 2469/* STENCIL_DECR_CLAMP = 0x04, */ 2470/* STENCIL_INVERT = 0x05, */ 2471/* STENCIL_INCR_WRAP = 0x06, */ 2472/* STENCIL_DECR_WRAP = 0x07, */ 2473 STENCILZFAIL_BF_mask = 0x07 << 29, 2474 STENCILZFAIL_BF_shift = 29, 2475/* STENCIL_KEEP = 0x00, */ 2476/* STENCIL_ZERO = 0x01, */ 2477/* STENCIL_REPLACE = 0x02, */ 2478/* STENCIL_INCR_CLAMP = 0x03, */ 2479/* STENCIL_DECR_CLAMP = 0x04, */ 2480/* STENCIL_INVERT = 0x05, */ 2481/* STENCIL_INCR_WRAP = 0x06, */ 2482/* STENCIL_DECR_WRAP = 0x07, */ 2483 CB_COLOR_CONTROL = 0x00028808, 2484 DEGAMMA_ENABLE_bit = 1 << 3, 2485 CB_COLOR_CONTROL__MODE_mask = 0x07 << 4, 2486 CB_COLOR_CONTROL__MODE_shift = 4, 2487 CB_DISABLE = 0x00, 2488 CB_NORMAL = 0x01, 2489 CB_ELIMINATE_FAST_CLEAR = 0x02, 2490 CB_RESOLVE = 0x03, 2491 CB_DECOMPRESS = 0x04, 2492 CB_FMASK_DECOMPRESS = 0x05, 2493 ROP3_mask = 0xff << 16, 2494 ROP3_shift = 16, 2495 DB_SHADER_CONTROL = 0x0002880c, 2496 Z_EXPORT_ENABLE_bit = 1 << 0, 2497 STENCIL_REF_EXPORT_ENABLE_bit = 1 << 1, 2498 Z_ORDER_mask = 0x03 << 4, 2499 Z_ORDER_shift = 4, 2500 LATE_Z = 0x00, 2501 EARLY_Z_THEN_LATE_Z = 0x01, 2502 RE_Z = 0x02, 2503 EARLY_Z_THEN_RE_Z = 0x03, 2504 KILL_ENABLE_bit = 1 << 6, 2505 COVERAGE_TO_MASK_ENABLE_bit = 1 << 7, 2506 MASK_EXPORT_ENABLE_bit = 1 << 8, 2507 DUAL_EXPORT_ENABLE_bit = 1 << 9, 2508 EXEC_ON_HIER_FAIL_bit = 1 << 10, 2509 EXEC_ON_NOOP_bit = 1 << 11, 2510 ALPHA_TO_MASK_DISABLE_bit = 1 << 12, 2511 DB_SOURCE_FORMAT_mask = 0x03 << 13, 2512 DB_SOURCE_FORMAT_shift = 13, 2513 EXPORT_DB_FULL = 0x00, 2514 EXPORT_DB_FOUR16 = 0x01, 2515 EXPORT_DB_TWO = 0x02, 2516 DEPTH_BEFORE_SHADER_bit = 1 << 15, 2517 CONSERVATIVE_Z_EXPORT_mask = 0x03 << 16, 2518 CONSERVATIVE_Z_EXPORT_shift = 16, 2519 EXPORT_ANY_Z = 0x00, 2520 EXPORT_LESS_THAN_Z = 0x01, 2521 EXPORT_GREATER_THAN_Z = 0x02, 2522 EXPORT_RESERVED = 0x03, 2523 PA_CL_CLIP_CNTL = 0x00028810, 2524 UCP_ENA_0_bit = 1 << 0, 2525 UCP_ENA_1_bit = 1 << 1, 2526 UCP_ENA_2_bit = 1 << 2, 2527 UCP_ENA_3_bit = 1 << 3, 2528 UCP_ENA_4_bit = 1 << 4, 2529 UCP_ENA_5_bit = 1 << 5, 2530 PS_UCP_Y_SCALE_NEG_bit = 1 << 13, 2531 PS_UCP_MODE_mask = 0x03 << 14, 2532 PS_UCP_MODE_shift = 14, 2533 CLIP_DISABLE_bit = 1 << 16, 2534 UCP_CULL_ONLY_ENA_bit = 1 << 17, 2535 BOUNDARY_EDGE_FLAG_ENA_bit = 1 << 18, 2536 DX_CLIP_SPACE_DEF_bit = 1 << 19, 2537 DIS_CLIP_ERR_DETECT_bit = 1 << 20, 2538 VTX_KILL_OR_bit = 1 << 21, 2539 DX_RASTERIZATION_KILL_bit = 1 << 22, 2540 DX_LINEAR_ATTR_CLIP_ENA_bit = 1 << 24, 2541 VTE_VPORT_PROVOKE_DISABLE_bit = 1 << 25, 2542 ZCLIP_NEAR_DISABLE_bit = 1 << 26, 2543 ZCLIP_FAR_DISABLE_bit = 1 << 27, 2544 PA_SU_SC_MODE_CNTL = 0x00028814, 2545 CULL_FRONT_bit = 1 << 0, 2546 CULL_BACK_bit = 1 << 1, 2547 FACE_bit = 1 << 2, 2548 POLY_MODE_mask = 0x03 << 3, 2549 POLY_MODE_shift = 3, 2550 X_DISABLE_POLY_MODE = 0x00, 2551 X_DUAL_MODE = 0x01, 2552 POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, 2553 POLYMODE_FRONT_PTYPE_shift = 5, 2554 X_DRAW_POINTS = 0x00, 2555 X_DRAW_LINES = 0x01, 2556 X_DRAW_TRIANGLES = 0x02, 2557 POLYMODE_BACK_PTYPE_mask = 0x07 << 8, 2558 POLYMODE_BACK_PTYPE_shift = 8, 2559/* X_DRAW_POINTS = 0x00, */ 2560/* X_DRAW_LINES = 0x01, */ 2561/* X_DRAW_TRIANGLES = 0x02, */ 2562 POLY_OFFSET_FRONT_ENABLE_bit = 1 << 11, 2563 POLY_OFFSET_BACK_ENABLE_bit = 1 << 12, 2564 POLY_OFFSET_PARA_ENABLE_bit = 1 << 13, 2565 VTX_WINDOW_OFFSET_ENABLE_bit = 1 << 16, 2566 PROVOKING_VTX_LAST_bit = 1 << 19, 2567 PERSP_CORR_DIS_bit = 1 << 20, 2568 MULTI_PRIM_IB_ENA_bit = 1 << 21, 2569 PA_CL_VTE_CNTL = 0x00028818, 2570 VPORT_X_SCALE_ENA_bit = 1 << 0, 2571 VPORT_X_OFFSET_ENA_bit = 1 << 1, 2572 VPORT_Y_SCALE_ENA_bit = 1 << 2, 2573 VPORT_Y_OFFSET_ENA_bit = 1 << 3, 2574 VPORT_Z_SCALE_ENA_bit = 1 << 4, 2575 VPORT_Z_OFFSET_ENA_bit = 1 << 5, 2576 VTX_XY_FMT_bit = 1 << 8, 2577 VTX_Z_FMT_bit = 1 << 9, 2578 VTX_W0_FMT_bit = 1 << 10, 2579 PA_CL_VS_OUT_CNTL = 0x0002881c, 2580 CLIP_DIST_ENA_0_bit = 1 << 0, 2581 CLIP_DIST_ENA_1_bit = 1 << 1, 2582 CLIP_DIST_ENA_2_bit = 1 << 2, 2583 CLIP_DIST_ENA_3_bit = 1 << 3, 2584 CLIP_DIST_ENA_4_bit = 1 << 4, 2585 CLIP_DIST_ENA_5_bit = 1 << 5, 2586 CLIP_DIST_ENA_6_bit = 1 << 6, 2587 CLIP_DIST_ENA_7_bit = 1 << 7, 2588 CULL_DIST_ENA_0_bit = 1 << 8, 2589 CULL_DIST_ENA_1_bit = 1 << 9, 2590 CULL_DIST_ENA_2_bit = 1 << 10, 2591 CULL_DIST_ENA_3_bit = 1 << 11, 2592 CULL_DIST_ENA_4_bit = 1 << 12, 2593 CULL_DIST_ENA_5_bit = 1 << 13, 2594 CULL_DIST_ENA_6_bit = 1 << 14, 2595 CULL_DIST_ENA_7_bit = 1 << 15, 2596 USE_VTX_POINT_SIZE_bit = 1 << 16, 2597 USE_VTX_EDGE_FLAG_bit = 1 << 17, 2598 USE_VTX_RENDER_TARGET_INDX_bit = 1 << 18, 2599 USE_VTX_VIEWPORT_INDX_bit = 1 << 19, 2600 USE_VTX_KILL_FLAG_bit = 1 << 20, 2601 VS_OUT_MISC_VEC_ENA_bit = 1 << 21, 2602 VS_OUT_CCDIST0_VEC_ENA_bit = 1 << 22, 2603 VS_OUT_CCDIST1_VEC_ENA_bit = 1 << 23, 2604 PA_CL_NANINF_CNTL = 0x00028820, 2605 VTE_XY_INF_DISCARD_bit = 1 << 0, 2606 VTE_Z_INF_DISCARD_bit = 1 << 1, 2607 VTE_W_INF_DISCARD_bit = 1 << 2, 2608 VTE_0XNANINF_IS_0_bit = 1 << 3, 2609 VTE_XY_NAN_RETAIN_bit = 1 << 4, 2610 VTE_Z_NAN_RETAIN_bit = 1 << 5, 2611 VTE_W_NAN_RETAIN_bit = 1 << 6, 2612 VTE_W_RECIP_NAN_IS_0_bit = 1 << 7, 2613 VS_XY_NAN_TO_INF_bit = 1 << 8, 2614 VS_XY_INF_RETAIN_bit = 1 << 9, 2615 VS_Z_NAN_TO_INF_bit = 1 << 10, 2616 VS_Z_INF_RETAIN_bit = 1 << 11, 2617 VS_W_NAN_TO_INF_bit = 1 << 12, 2618 VS_W_INF_RETAIN_bit = 1 << 13, 2619 VS_CLIP_DIST_INF_DISCARD_bit = 1 << 14, 2620 VTE_NO_OUTPUT_NEG_0_bit = 1 << 20, 2621 PA_SU_LINE_STIPPLE_CNTL = 0x00028824, 2622 LINE_STIPPLE_RESET_mask = 0x03 << 0, 2623 LINE_STIPPLE_RESET_shift = 0, 2624 EXPAND_FULL_LENGTH_bit = 1 << 2, 2625 FRACTIONAL_ACCUM_bit = 1 << 3, 2626 DIAMOND_ADJUST_bit = 1 << 4, 2627 PA_SU_LINE_STIPPLE_SCALE = 0x00028828, 2628 PA_SU_PRIM_FILTER_CNTL = 0x0002882c, 2629 TRIANGLE_FILTER_DISABLE_bit = 1 << 0, 2630 LINE_FILTER_DISABLE_bit = 1 << 1, 2631 POINT_FILTER_DISABLE_bit = 1 << 2, 2632 RECTANGLE_FILTER_DISABLE_bit = 1 << 3, 2633 TRIANGLE_EXPAND_ENA_bit = 1 << 4, 2634 LINE_EXPAND_ENA_bit = 1 << 5, 2635 POINT_EXPAND_ENA_bit = 1 << 6, 2636 RECTANGLE_EXPAND_ENA_bit = 1 << 7, 2637 PRIM_EXPAND_CONSTANT_mask = 0xff << 8, 2638 PRIM_EXPAND_CONSTANT_shift = 8, 2639 SQ_LSTMP_RING_ITEMSIZE = 0x00028830, 2640 ITEMSIZE_mask = 0x7fff << 0, 2641 ITEMSIZE_shift = 0, 2642 SQ_HSTMP_RING_ITEMSIZE = 0x00028834, 2643/* ITEMSIZE_mask = 0x7fff << 0, */ 2644/* ITEMSIZE_shift = 0, */ 2645 SQ_PGM_START_PS = 0x00028840, 2646 SQ_PGM_RESOURCES_PS = 0x00028844, 2647 NUM_GPRS_mask = 0xff << 0, 2648 NUM_GPRS_shift = 0, 2649 STACK_SIZE_mask = 0xff << 8, 2650 STACK_SIZE_shift = 8, 2651 DX10_CLAMP_bit = 1 << 21, 2652 UNCACHED_FIRST_INST_bit = 1 << 28, 2653 CLAMP_CONSTS_bit = 1 << 31, 2654 SQ_PGM_RESOURCES_2_PS = 0x00028848, 2655 SINGLE_ROUND_mask = 0x03 << 0, 2656 SINGLE_ROUND_shift = 0, 2657 SQ_ROUND_NEAREST_EVEN = 0x00, 2658 SQ_ROUND_PLUS_INFINITY = 0x01, 2659 SQ_ROUND_MINUS_INFINITY = 0x02, 2660 SQ_ROUND_TO_ZERO = 0x03, 2661 DOUBLE_ROUND_mask = 0x03 << 2, 2662 DOUBLE_ROUND_shift = 2, 2663/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2664/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2665/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2666/* SQ_ROUND_TO_ZERO = 0x03, */ 2667 ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, 2668 ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, 2669 ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, 2670 ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, 2671 SQ_PGM_EXPORTS_PS = 0x0002884c, 2672 EXPORT_MODE_mask = 0x1f << 0, 2673 EXPORT_MODE_shift = 0, 2674 SQ_PGM_START_VS = 0x0002885c, 2675 SQ_PGM_RESOURCES_VS = 0x00028860, 2676/* NUM_GPRS_mask = 0xff << 0, */ 2677/* NUM_GPRS_shift = 0, */ 2678/* STACK_SIZE_mask = 0xff << 8, */ 2679/* STACK_SIZE_shift = 8, */ 2680/* DX10_CLAMP_bit = 1 << 21, */ 2681/* UNCACHED_FIRST_INST_bit = 1 << 28, */ 2682 SQ_PGM_RESOURCES_2_VS = 0x00028864, 2683/* SINGLE_ROUND_mask = 0x03 << 0, */ 2684/* SINGLE_ROUND_shift = 0, */ 2685/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2686/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2687/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2688/* SQ_ROUND_TO_ZERO = 0x03, */ 2689/* DOUBLE_ROUND_mask = 0x03 << 2, */ 2690/* DOUBLE_ROUND_shift = 2, */ 2691/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2692/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2693/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2694/* SQ_ROUND_TO_ZERO = 0x03, */ 2695/* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ 2696/* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ 2697/* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ 2698/* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ 2699 SQ_PGM_START_GS = 0x00028874, 2700 SQ_PGM_RESOURCES_GS = 0x00028878, 2701/* NUM_GPRS_mask = 0xff << 0, */ 2702/* NUM_GPRS_shift = 0, */ 2703/* STACK_SIZE_mask = 0xff << 8, */ 2704/* STACK_SIZE_shift = 8, */ 2705/* DX10_CLAMP_bit = 1 << 21, */ 2706/* UNCACHED_FIRST_INST_bit = 1 << 28, */ 2707 SQ_PGM_RESOURCES_2_GS = 0x0002887c, 2708/* SINGLE_ROUND_mask = 0x03 << 0, */ 2709/* SINGLE_ROUND_shift = 0, */ 2710/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2711/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2712/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2713/* SQ_ROUND_TO_ZERO = 0x03, */ 2714/* DOUBLE_ROUND_mask = 0x03 << 2, */ 2715/* DOUBLE_ROUND_shift = 2, */ 2716/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2717/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2718/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2719/* SQ_ROUND_TO_ZERO = 0x03, */ 2720/* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ 2721/* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ 2722/* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ 2723/* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ 2724 SQ_PGM_START_ES = 0x0002888c, 2725 SQ_PGM_RESOURCES_ES = 0x00028890, 2726/* NUM_GPRS_mask = 0xff << 0, */ 2727/* NUM_GPRS_shift = 0, */ 2728/* STACK_SIZE_mask = 0xff << 8, */ 2729/* STACK_SIZE_shift = 8, */ 2730/* DX10_CLAMP_bit = 1 << 21, */ 2731/* UNCACHED_FIRST_INST_bit = 1 << 28, */ 2732 SQ_PGM_RESOURCES_2_ES = 0x00028894, 2733/* SINGLE_ROUND_mask = 0x03 << 0, */ 2734/* SINGLE_ROUND_shift = 0, */ 2735/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2736/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2737/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2738/* SQ_ROUND_TO_ZERO = 0x03, */ 2739/* DOUBLE_ROUND_mask = 0x03 << 2, */ 2740/* DOUBLE_ROUND_shift = 2, */ 2741/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2742/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2743/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2744/* SQ_ROUND_TO_ZERO = 0x03, */ 2745/* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ 2746/* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ 2747/* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ 2748/* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ 2749 SQ_PGM_START_FS = 0x000288a4, 2750 SQ_PGM_RESOURCES_FS = 0x000288a8, 2751/* NUM_GPRS_mask = 0xff << 0, */ 2752/* NUM_GPRS_shift = 0, */ 2753/* STACK_SIZE_mask = 0xff << 8, */ 2754/* STACK_SIZE_shift = 8, */ 2755/* DX10_CLAMP_bit = 1 << 21, */ 2756 SQ_PGM_START_HS = 0x000288b8, 2757 SQ_PGM_RESOURCES_HS = 0x000288bc, 2758/* NUM_GPRS_mask = 0xff << 0, */ 2759/* NUM_GPRS_shift = 0, */ 2760/* STACK_SIZE_mask = 0xff << 8, */ 2761/* STACK_SIZE_shift = 8, */ 2762/* DX10_CLAMP_bit = 1 << 21, */ 2763/* UNCACHED_FIRST_INST_bit = 1 << 28, */ 2764 SQ_PGM_RESOURCES_2_HS = 0x000288c0, 2765/* SINGLE_ROUND_mask = 0x03 << 0, */ 2766/* SINGLE_ROUND_shift = 0, */ 2767/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2768/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2769/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2770/* SQ_ROUND_TO_ZERO = 0x03, */ 2771/* DOUBLE_ROUND_mask = 0x03 << 2, */ 2772/* DOUBLE_ROUND_shift = 2, */ 2773/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2774/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2775/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2776/* SQ_ROUND_TO_ZERO = 0x03, */ 2777/* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ 2778/* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ 2779/* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ 2780/* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ 2781 SQ_PGM_START_LS = 0x000288d0, 2782 SQ_PGM_RESOURCES_LS = 0x000288d4, 2783/* NUM_GPRS_mask = 0xff << 0, */ 2784/* NUM_GPRS_shift = 0, */ 2785/* STACK_SIZE_mask = 0xff << 8, */ 2786/* STACK_SIZE_shift = 8, */ 2787/* DX10_CLAMP_bit = 1 << 21, */ 2788/* UNCACHED_FIRST_INST_bit = 1 << 28, */ 2789 SQ_PGM_RESOURCES_2_LS = 0x000288d8, 2790/* SINGLE_ROUND_mask = 0x03 << 0, */ 2791/* SINGLE_ROUND_shift = 0, */ 2792/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2793/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2794/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2795/* SQ_ROUND_TO_ZERO = 0x03, */ 2796/* DOUBLE_ROUND_mask = 0x03 << 2, */ 2797/* DOUBLE_ROUND_shift = 2, */ 2798/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2799/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2800/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2801/* SQ_ROUND_TO_ZERO = 0x03, */ 2802/* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ 2803/* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ 2804/* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ 2805/* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ 2806 SQ_VTX_SEMANTIC_CLEAR = 0x000288f0, 2807 SQ_ESGS_RING_ITEMSIZE = 0x00028900, 2808/* ITEMSIZE_mask = 0x7fff << 0, */ 2809/* ITEMSIZE_shift = 0, */ 2810 SQ_GSVS_RING_ITEMSIZE = 0x00028904, 2811/* ITEMSIZE_mask = 0x7fff << 0, */ 2812/* ITEMSIZE_shift = 0, */ 2813 SQ_ESTMP_RING_ITEMSIZE = 0x00028908, 2814/* ITEMSIZE_mask = 0x7fff << 0, */ 2815/* ITEMSIZE_shift = 0, */ 2816 SQ_GSTMP_RING_ITEMSIZE = 0x0002890c, 2817/* ITEMSIZE_mask = 0x7fff << 0, */ 2818/* ITEMSIZE_shift = 0, */ 2819 SQ_VSTMP_RING_ITEMSIZE = 0x00028910, 2820/* ITEMSIZE_mask = 0x7fff << 0, */ 2821/* ITEMSIZE_shift = 0, */ 2822 SQ_PSTMP_RING_ITEMSIZE = 0x00028914, 2823/* ITEMSIZE_mask = 0x7fff << 0, */ 2824/* ITEMSIZE_shift = 0, */ 2825 SQ_GS_VERT_ITEMSIZE = 0x0002891c, 2826/* ITEMSIZE_mask = 0x7fff << 0, */ 2827/* ITEMSIZE_shift = 0, */ 2828 SQ_GS_VERT_ITEMSIZE_1 = 0x00028920, 2829/* ITEMSIZE_mask = 0x7fff << 0, */ 2830/* ITEMSIZE_shift = 0, */ 2831 SQ_GS_VERT_ITEMSIZE_2 = 0x00028924, 2832/* ITEMSIZE_mask = 0x7fff << 0, */ 2833/* ITEMSIZE_shift = 0, */ 2834 SQ_GS_VERT_ITEMSIZE_3 = 0x00028928, 2835/* ITEMSIZE_mask = 0x7fff << 0, */ 2836/* ITEMSIZE_shift = 0, */ 2837 SQ_GSVS_RING_OFFSET_1 = 0x0002892c, 2838 SQ_GSVS_RING_OFFSET_1__OFFSET_mask = 0x7fff << 0, 2839 SQ_GSVS_RING_OFFSET_1__OFFSET_shift = 0, 2840 SQ_GSVS_RING_OFFSET_2 = 0x00028930, 2841 SQ_GSVS_RING_OFFSET_2__OFFSET_mask = 0x7fff << 0, 2842 SQ_GSVS_RING_OFFSET_2__OFFSET_shift = 0, 2843 SQ_GSVS_RING_OFFSET_3 = 0x00028934, 2844 SQ_GSVS_RING_OFFSET_3__OFFSET_mask = 0x7fff << 0, 2845 SQ_GSVS_RING_OFFSET_3__OFFSET_shift = 0, 2846 SQ_ALU_CONST_CACHE_PS_0 = 0x00028940, 2847 SQ_ALU_CONST_CACHE_PS_0_num = 16, 2848 SQ_ALU_CONST_CACHE_VS_0 = 0x00028980, 2849 SQ_ALU_CONST_CACHE_VS_0_num = 16, 2850 SQ_ALU_CONST_CACHE_GS_0 = 0x000289c0, 2851 SQ_ALU_CONST_CACHE_GS_0_num = 16, 2852 PA_SU_POINT_SIZE = 0x00028a00, 2853 HEIGHT_mask = 0xffff << 0, 2854 HEIGHT_shift = 0, 2855 PA_SU_POINT_SIZE__WIDTH_mask = 0xffff << 16, 2856 PA_SU_POINT_SIZE__WIDTH_shift = 16, 2857 PA_SU_POINT_MINMAX = 0x00028a04, 2858 MIN_SIZE_mask = 0xffff << 0, 2859 MIN_SIZE_shift = 0, 2860 PA_SU_POINT_MINMAX__MAX_SIZE_mask = 0xffff << 16, 2861 PA_SU_POINT_MINMAX__MAX_SIZE_shift = 16, 2862 PA_SU_LINE_CNTL = 0x00028a08, 2863 PA_SU_LINE_CNTL__WIDTH_mask = 0xffff << 0, 2864 PA_SU_LINE_CNTL__WIDTH_shift = 0, 2865 PA_SC_LINE_STIPPLE = 0x00028a0c, 2866 LINE_PATTERN_mask = 0xffff << 0, 2867 LINE_PATTERN_shift = 0, 2868 REPEAT_COUNT_mask = 0xff << 16, 2869 REPEAT_COUNT_shift = 16, 2870 PATTERN_BIT_ORDER_bit = 1 << 28, 2871 AUTO_RESET_CNTL_mask = 0x03 << 29, 2872 AUTO_RESET_CNTL_shift = 29, 2873 VGT_OUTPUT_PATH_CNTL = 0x00028a10, 2874 PATH_SELECT_mask = 0x07 << 0, 2875 PATH_SELECT_shift = 0, 2876 VGT_OUTPATH_VTX_REUSE = 0x00, 2877 VGT_OUTPATH_TESS_EN = 0x01, 2878 VGT_OUTPATH_PASSTHRU = 0x02, 2879 VGT_OUTPATH_GS_BLOCK = 0x03, 2880 VGT_OUTPATH_HS_BLOCK = 0x04, 2881 VGT_HOS_CNTL = 0x00028a14, 2882 TESS_MODE_mask = 0x03 << 0, 2883 TESS_MODE_shift = 0, 2884 VGT_HOS_MAX_TESS_LEVEL = 0x00028a18, 2885 VGT_HOS_MIN_TESS_LEVEL = 0x00028a1c, 2886 VGT_HOS_REUSE_DEPTH = 0x00028a20, 2887 REUSE_DEPTH_mask = 0xff << 0, 2888 REUSE_DEPTH_shift = 0, 2889 VGT_GROUP_PRIM_TYPE = 0x00028a24, 2890 VGT_GROUP_PRIM_TYPE__PRIM_TYPE_mask = 0x1f << 0, 2891 VGT_GROUP_PRIM_TYPE__PRIM_TYPE_shift = 0, 2892 VGT_GRP_3D_POINT = 0x00, 2893 VGT_GRP_3D_LINE = 0x01, 2894 VGT_GRP_3D_TRI = 0x02, 2895 VGT_GRP_3D_RECT = 0x03, 2896 VGT_GRP_3D_QUAD = 0x04, 2897 VGT_GRP_2D_COPY_RECT_V0 = 0x05, 2898 VGT_GRP_2D_COPY_RECT_V1 = 0x06, 2899 VGT_GRP_2D_COPY_RECT_V2 = 0x07, 2900 VGT_GRP_2D_COPY_RECT_V3 = 0x08, 2901 VGT_GRP_2D_FILL_RECT = 0x09, 2902 VGT_GRP_2D_LINE = 0x0a, 2903 VGT_GRP_2D_TRI = 0x0b, 2904 VGT_GRP_PRIM_INDEX_LINE = 0x0c, 2905 VGT_GRP_PRIM_INDEX_TRI = 0x0d, 2906 VGT_GRP_PRIM_INDEX_QUAD = 0x0e, 2907 VGT_GRP_3D_LINE_ADJ = 0x0f, 2908 VGT_GRP_3D_TRI_ADJ = 0x10, 2909 VGT_GRP_3D_PATCH = 0x11, 2910 RETAIN_ORDER_bit = 1 << 14, 2911 RETAIN_QUADS_bit = 1 << 15, 2912 PRIM_ORDER_mask = 0x07 << 16, 2913 PRIM_ORDER_shift = 16, 2914 VGT_GRP_LIST = 0x00, 2915 VGT_GRP_STRIP = 0x01, 2916 VGT_GRP_FAN = 0x02, 2917 VGT_GRP_LOOP = 0x03, 2918 VGT_GRP_POLYGON = 0x04, 2919 VGT_GROUP_FIRST_DECR = 0x00028a28, 2920 FIRST_DECR_mask = 0x0f << 0, 2921 FIRST_DECR_shift = 0, 2922 VGT_GROUP_DECR = 0x00028a2c, 2923 DECR_mask = 0x0f << 0, 2924 DECR_shift = 0, 2925 VGT_GROUP_VECT_0_CNTL = 0x00028a30, 2926 COMP_X_EN_bit = 1 << 0, 2927 COMP_Y_EN_bit = 1 << 1, 2928 COMP_Z_EN_bit = 1 << 2, 2929 COMP_W_EN_bit = 1 << 3, 2930 VGT_GROUP_VECT_0_CNTL__STRIDE_mask = 0xff << 8, 2931 VGT_GROUP_VECT_0_CNTL__STRIDE_shift = 8, 2932 SHIFT_mask = 0xff << 16, 2933 SHIFT_shift = 16, 2934 VGT_GROUP_VECT_1_CNTL = 0x00028a34, 2935/* COMP_X_EN_bit = 1 << 0, */ 2936/* COMP_Y_EN_bit = 1 << 1, */ 2937/* COMP_Z_EN_bit = 1 << 2, */ 2938/* COMP_W_EN_bit = 1 << 3, */ 2939 VGT_GROUP_VECT_1_CNTL__STRIDE_mask = 0xff << 8, 2940 VGT_GROUP_VECT_1_CNTL__STRIDE_shift = 8, 2941/* SHIFT_mask = 0xff << 16, */ 2942/* SHIFT_shift = 16, */ 2943 VGT_GROUP_VECT_0_FMT_CNTL = 0x00028a38, 2944 X_CONV_mask = 0x0f << 0, 2945 X_CONV_shift = 0, 2946 VGT_GRP_INDEX_16 = 0x00, 2947 VGT_GRP_INDEX_32 = 0x01, 2948 VGT_GRP_UINT_16 = 0x02, 2949 VGT_GRP_UINT_32 = 0x03, 2950 VGT_GRP_SINT_16 = 0x04, 2951 VGT_GRP_SINT_32 = 0x05, 2952 VGT_GRP_FLOAT_32 = 0x06, 2953 VGT_GRP_AUTO_PRIM = 0x07, 2954 VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, 2955 X_OFFSET_mask = 0x0f << 4, 2956 X_OFFSET_shift = 4, 2957 Y_CONV_mask = 0x0f << 8, 2958 Y_CONV_shift = 8, 2959/* VGT_GRP_INDEX_16 = 0x00, */ 2960/* VGT_GRP_INDEX_32 = 0x01, */ 2961/* VGT_GRP_UINT_16 = 0x02, */ 2962/* VGT_GRP_UINT_32 = 0x03, */ 2963/* VGT_GRP_SINT_16 = 0x04, */ 2964/* VGT_GRP_SINT_32 = 0x05, */ 2965/* VGT_GRP_FLOAT_32 = 0x06, */ 2966/* VGT_GRP_AUTO_PRIM = 0x07, */ 2967/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 2968 Y_OFFSET_mask = 0x0f << 12, 2969 Y_OFFSET_shift = 12, 2970 Z_CONV_mask = 0x0f << 16, 2971 Z_CONV_shift = 16, 2972/* VGT_GRP_INDEX_16 = 0x00, */ 2973/* VGT_GRP_INDEX_32 = 0x01, */ 2974/* VGT_GRP_UINT_16 = 0x02, */ 2975/* VGT_GRP_UINT_32 = 0x03, */ 2976/* VGT_GRP_SINT_16 = 0x04, */ 2977/* VGT_GRP_SINT_32 = 0x05, */ 2978/* VGT_GRP_FLOAT_32 = 0x06, */ 2979/* VGT_GRP_AUTO_PRIM = 0x07, */ 2980/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 2981 Z_OFFSET_mask = 0x0f << 20, 2982 Z_OFFSET_shift = 20, 2983 W_CONV_mask = 0x0f << 24, 2984 W_CONV_shift = 24, 2985/* VGT_GRP_INDEX_16 = 0x00, */ 2986/* VGT_GRP_INDEX_32 = 0x01, */ 2987/* VGT_GRP_UINT_16 = 0x02, */ 2988/* VGT_GRP_UINT_32 = 0x03, */ 2989/* VGT_GRP_SINT_16 = 0x04, */ 2990/* VGT_GRP_SINT_32 = 0x05, */ 2991/* VGT_GRP_FLOAT_32 = 0x06, */ 2992/* VGT_GRP_AUTO_PRIM = 0x07, */ 2993/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 2994 W_OFFSET_mask = 0x0f << 28, 2995 W_OFFSET_shift = 28, 2996 VGT_GROUP_VECT_1_FMT_CNTL = 0x00028a3c, 2997/* X_CONV_mask = 0x0f << 0, */ 2998/* X_CONV_shift = 0, */ 2999/* VGT_GRP_INDEX_16 = 0x00, */ 3000/* VGT_GRP_INDEX_32 = 0x01, */ 3001/* VGT_GRP_UINT_16 = 0x02, */ 3002/* VGT_GRP_UINT_32 = 0x03, */ 3003/* VGT_GRP_SINT_16 = 0x04, */ 3004/* VGT_GRP_SINT_32 = 0x05, */ 3005/* VGT_GRP_FLOAT_32 = 0x06, */ 3006/* VGT_GRP_AUTO_PRIM = 0x07, */ 3007/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3008/* X_OFFSET_mask = 0x0f << 4, */ 3009/* X_OFFSET_shift = 4, */ 3010/* Y_CONV_mask = 0x0f << 8, */ 3011/* Y_CONV_shift = 8, */ 3012/* VGT_GRP_INDEX_16 = 0x00, */ 3013/* VGT_GRP_INDEX_32 = 0x01, */ 3014/* VGT_GRP_UINT_16 = 0x02, */ 3015/* VGT_GRP_UINT_32 = 0x03, */ 3016/* VGT_GRP_SINT_16 = 0x04, */ 3017/* VGT_GRP_SINT_32 = 0x05, */ 3018/* VGT_GRP_FLOAT_32 = 0x06, */ 3019/* VGT_GRP_AUTO_PRIM = 0x07, */ 3020/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3021/* Y_OFFSET_mask = 0x0f << 12, */ 3022/* Y_OFFSET_shift = 12, */ 3023/* Z_CONV_mask = 0x0f << 16, */ 3024/* Z_CONV_shift = 16, */ 3025/* VGT_GRP_INDEX_16 = 0x00, */ 3026/* VGT_GRP_INDEX_32 = 0x01, */ 3027/* VGT_GRP_UINT_16 = 0x02, */ 3028/* VGT_GRP_UINT_32 = 0x03, */ 3029/* VGT_GRP_SINT_16 = 0x04, */ 3030/* VGT_GRP_SINT_32 = 0x05, */ 3031/* VGT_GRP_FLOAT_32 = 0x06, */ 3032/* VGT_GRP_AUTO_PRIM = 0x07, */ 3033/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3034/* Z_OFFSET_mask = 0x0f << 20, */ 3035/* Z_OFFSET_shift = 20, */ 3036/* W_CONV_mask = 0x0f << 24, */ 3037/* W_CONV_shift = 24, */ 3038/* VGT_GRP_INDEX_16 = 0x00, */ 3039/* VGT_GRP_INDEX_32 = 0x01, */ 3040/* VGT_GRP_UINT_16 = 0x02, */ 3041/* VGT_GRP_UINT_32 = 0x03, */ 3042/* VGT_GRP_SINT_16 = 0x04, */ 3043/* VGT_GRP_SINT_32 = 0x05, */ 3044/* VGT_GRP_FLOAT_32 = 0x06, */ 3045/* VGT_GRP_AUTO_PRIM = 0x07, */ 3046/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3047/* W_OFFSET_mask = 0x0f << 28, */ 3048/* W_OFFSET_shift = 28, */ 3049 VGT_GS_MODE = 0x00028a40, 3050 VGT_GS_MODE__MODE_mask = 0x03 << 0, 3051 VGT_GS_MODE__MODE_shift = 0, 3052 GS_OFF = 0x00, 3053 GS_SCENARIO_A = 0x01, 3054 GS_SCENARIO_B = 0x02, 3055 GS_SCENARIO_G = 0x03, 3056 GS_SCENARIO_C = 0x04, 3057 SPRITE_EN = 0x05, 3058 ES_PASSTHRU_bit = 1 << 2, 3059 CUT_MODE_mask = 0x03 << 3, 3060 CUT_MODE_shift = 3, 3061 GS_CUT_1024 = 0x00, 3062 GS_CUT_512 = 0x01, 3063 GS_CUT_256 = 0x02, 3064 GS_CUT_128 = 0x03, 3065 MODE_HI_bit = 1 << 8, 3066 PA_SC_MODE_CNTL_0 = 0x00028a48, 3067 MSAA_ENABLE_bit = 1 << 0, 3068 VPORT_SCISSOR_ENABLE_bit = 1 << 1, 3069 LINE_STIPPLE_ENABLE_bit = 1 << 2, 3070 VGT_ENHANCE = 0x00028a50, 3071 VGT_GS_PER_ES = 0x00028a54, 3072 GS_PER_ES_mask = 0x7ff << 0, 3073 GS_PER_ES_shift = 0, 3074 VGT_ES_PER_GS = 0x00028a58, 3075 ES_PER_GS_mask = 0x7ff << 0, 3076 ES_PER_GS_shift = 0, 3077 VGT_GS_PER_VS = 0x00028a5c, 3078 GS_PER_VS_mask = 0x0f << 0, 3079 GS_PER_VS_shift = 0, 3080 VGT_GS_OUT_PRIM_TYPE = 0x00028a6c, 3081 OUTPRIM_TYPE_mask = 0x3f << 0, 3082 OUTPRIM_TYPE_shift = 0, 3083 POINTLIST = 0x00, 3084 LINESTRIP = 0x01, 3085 TRISTRIP = 0x02, 3086 VGT_DMA_SIZE = 0x00028a74, 3087 VGT_DMA_MAX_SIZE = 0x00028a78, 3088 VGT_DMA_INDEX_TYPE = 0x00028a7c, 3089/* INDEX_TYPE_mask = 0x03 << 0, */ 3090/* INDEX_TYPE_shift = 0, */ 3091 VGT_INDEX_16 = 0x00, 3092 VGT_INDEX_32 = 0x01, 3093 SWAP_MODE_mask = 0x03 << 2, 3094 SWAP_MODE_shift = 2, 3095 VGT_DMA_SWAP_NONE = 0x00, 3096 VGT_DMA_SWAP_16_BIT = 0x01, 3097 VGT_DMA_SWAP_32_BIT = 0x02, 3098 VGT_DMA_SWAP_WORD = 0x03, 3099 VGT_PRIMITIVEID_EN = 0x00028a84, 3100 PRIMITIVEID_EN_bit = 1 << 0, 3101 VGT_DMA_NUM_INSTANCES = 0x00028a88, 3102 VGT_EVENT_INITIATOR = 0x00028a90, 3103 EVENT_TYPE_mask = 0x3f << 0, 3104 EVENT_TYPE_shift = 0, 3105 SAMPLE_STREAMOUTSTATS1 = 0x01, 3106 SAMPLE_STREAMOUTSTATS2 = 0x02, 3107 SAMPLE_STREAMOUTSTATS3 = 0x03, 3108 CACHE_FLUSH_TS = 0x04, 3109 CONTEXT_DONE = 0x05, 3110 CACHE_FLUSH = 0x06, 3111 CS_PARTIAL_FLUSH = 0x07, 3112 RST_PIX_CNT = 0x0d, 3113 VS_PARTIAL_FLUSH = 0x0f, 3114 PS_PARTIAL_FLUSH = 0x10, 3115 FLUSH_HS_OUTPUT = 0x11, 3116 FLUSH_LS_OUTPUT = 0x12, 3117 CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, 3118 ZPASS_DONE = 0x15, 3119 CACHE_FLUSH_AND_INV_EVENT = 0x16, 3120 PERFCOUNTER_START = 0x17, 3121 PERFCOUNTER_STOP = 0x18, 3122 PIPELINESTAT_START = 0x19, 3123 PIPELINESTAT_STOP = 0x1a, 3124 PERFCOUNTER_SAMPLE = 0x1b, 3125 FLUSH_ES_OUTPUT = 0x1c, 3126 FLUSH_GS_OUTPUT = 0x1d, 3127 SAMPLE_PIPELINESTAT = 0x1e, 3128 SO_VGTSTREAMOUT_FLUSH = 0x1f, 3129 SAMPLE_STREAMOUTSTATS = 0x20, 3130 RESET_VTX_CNT = 0x21, 3131 BLOCK_CONTEXT_DONE = 0x22, 3132 CS_CONTEXT_DONE = 0x23, 3133 VGT_FLUSH = 0x24, 3134 SQ_NON_EVENT = 0x26, 3135 SC_SEND_DB_VPZ = 0x27, 3136 BOTTOM_OF_PIPE_TS = 0x28, 3137 FLUSH_SX_TS = 0x29, 3138 DB_CACHE_FLUSH_AND_INV = 0x2a, 3139 FLUSH_AND_INV_DB_DATA_TS = 0x2b, 3140 FLUSH_AND_INV_DB_META = 0x2c, 3141 FLUSH_AND_INV_CB_DATA_TS = 0x2d, 3142 FLUSH_AND_INV_CB_META = 0x2e, 3143 CS_DONE = 0x2f, 3144 PS_DONE = 0x30, 3145 FLUSH_AND_INV_CB_PIXEL_DATA = 0x31, 3146 ADDRESS_HI_mask = 0xff << 19, 3147 ADDRESS_HI_shift = 19, 3148 EXTENDED_EVENT_bit = 1 << 27, 3149 VGT_MULTI_PRIM_IB_RESET_EN = 0x00028a94, 3150 RESET_EN_bit = 1 << 0, 3151 VGT_INSTANCE_STEP_RATE_0 = 0x00028aa0, 3152 VGT_INSTANCE_STEP_RATE_1 = 0x00028aa4, 3153 VGT_REUSE_OFF = 0x00028ab4, 3154 REUSE_OFF_bit = 1 << 0, 3155 VGT_VTX_CNT_EN = 0x00028ab8, 3156 VTX_CNT_EN_bit = 1 << 0, 3157 DB_HTILE_SURFACE = 0x00028abc, 3158 HTILE_WIDTH_bit = 1 << 0, 3159 HTILE_HEIGHT_bit = 1 << 1, 3160 LINEAR_bit = 1 << 2, 3161 FULL_CACHE_bit = 1 << 3, 3162 HTILE_USES_PRELOAD_WIN_bit = 1 << 4, 3163 PRELOAD_bit = 1 << 5, 3164 PREFETCH_WIDTH_mask = 0x3f << 6, 3165 PREFETCH_WIDTH_shift = 6, 3166 PREFETCH_HEIGHT_mask = 0x3f << 12, 3167 PREFETCH_HEIGHT_shift = 12, 3168 DB_SRESULTS_COMPARE_STATE0 = 0x00028ac0, 3169 COMPAREFUNC0_mask = 0x07 << 0, 3170 COMPAREFUNC0_shift = 0, 3171/* REF_NEVER = 0x00, */ 3172/* REF_LESS = 0x01, */ 3173/* REF_EQUAL = 0x02, */ 3174/* REF_LEQUAL = 0x03, */ 3175/* REF_GREATER = 0x04, */ 3176/* REF_NOTEQUAL = 0x05, */ 3177/* REF_GEQUAL = 0x06, */ 3178/* REF_ALWAYS = 0x07, */ 3179 COMPAREVALUE0_mask = 0xff << 4, 3180 COMPAREVALUE0_shift = 4, 3181 COMPAREMASK0_mask = 0xff << 12, 3182 COMPAREMASK0_shift = 12, 3183 ENABLE0_bit = 1 << 24, 3184 DB_SRESULTS_COMPARE_STATE1 = 0x00028ac4, 3185 COMPAREFUNC1_mask = 0x07 << 0, 3186 COMPAREFUNC1_shift = 0, 3187/* REF_NEVER = 0x00, */ 3188/* REF_LESS = 0x01, */ 3189/* REF_EQUAL = 0x02, */ 3190/* REF_LEQUAL = 0x03, */ 3191/* REF_GREATER = 0x04, */ 3192/* REF_NOTEQUAL = 0x05, */ 3193/* REF_GEQUAL = 0x06, */ 3194/* REF_ALWAYS = 0x07, */ 3195 COMPAREVALUE1_mask = 0xff << 4, 3196 COMPAREVALUE1_shift = 4, 3197 COMPAREMASK1_mask = 0xff << 12, 3198 COMPAREMASK1_shift = 12, 3199 ENABLE1_bit = 1 << 24, 3200 DB_PRELOAD_CONTROL = 0x00028ac8, 3201 START_X_mask = 0xff << 0, 3202 START_X_shift = 0, 3203 START_Y_mask = 0xff << 8, 3204 START_Y_shift = 8, 3205 MAX_X_mask = 0xff << 16, 3206 MAX_X_shift = 16, 3207 MAX_Y_mask = 0xff << 24, 3208 MAX_Y_shift = 24, 3209 VGT_STRMOUT_BUFFER_SIZE_0 = 0x00028ad0, 3210 VGT_STRMOUT_VTX_STRIDE_0 = 0x00028ad4, 3211 VGT_STRMOUT_VTX_STRIDE_0__STRIDE_mask = 0x3ff << 0, 3212 VGT_STRMOUT_VTX_STRIDE_0__STRIDE_shift = 0, 3213 VGT_STRMOUT_BUFFER_BASE_0 = 0x00028ad8, 3214 VGT_STRMOUT_BUFFER_OFFSET_0 = 0x00028adc, 3215 VGT_STRMOUT_BUFFER_SIZE_1 = 0x00028ae0, 3216 VGT_STRMOUT_VTX_STRIDE_1 = 0x00028ae4, 3217 VGT_STRMOUT_VTX_STRIDE_1__STRIDE_mask = 0x3ff << 0, 3218 VGT_STRMOUT_VTX_STRIDE_1__STRIDE_shift = 0, 3219 VGT_STRMOUT_BUFFER_BASE_1 = 0x00028ae8, 3220 VGT_STRMOUT_BUFFER_OFFSET_1 = 0x00028aec, 3221 VGT_STRMOUT_BUFFER_SIZE_2 = 0x00028af0, 3222 VGT_STRMOUT_VTX_STRIDE_2 = 0x00028af4, 3223 VGT_STRMOUT_VTX_STRIDE_2__STRIDE_mask = 0x3ff << 0, 3224 VGT_STRMOUT_VTX_STRIDE_2__STRIDE_shift = 0, 3225 VGT_STRMOUT_BUFFER_BASE_2 = 0x00028af8, 3226 VGT_STRMOUT_BUFFER_OFFSET_2 = 0x00028afc, 3227 VGT_STRMOUT_BUFFER_SIZE_3 = 0x00028b00, 3228 VGT_STRMOUT_VTX_STRIDE_3 = 0x00028b04, 3229 VGT_STRMOUT_VTX_STRIDE_3__STRIDE_mask = 0x3ff << 0, 3230 VGT_STRMOUT_VTX_STRIDE_3__STRIDE_shift = 0, 3231 VGT_STRMOUT_BUFFER_BASE_3 = 0x00028b08, 3232 VGT_STRMOUT_BUFFER_OFFSET_3 = 0x00028b0c, 3233 VGT_STRMOUT_BASE_OFFSET_0 = 0x00028b10, 3234 VGT_STRMOUT_BASE_OFFSET_1 = 0x00028b14, 3235 VGT_STRMOUT_BASE_OFFSET_2 = 0x00028b18, 3236 VGT_STRMOUT_BASE_OFFSET_3 = 0x00028b1c, 3237 VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x00028b28, 3238 VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x00028b2c, 3239 VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x00028b30, 3240 VERTEX_STRIDE_mask = 0x1ff << 0, 3241 VERTEX_STRIDE_shift = 0, 3242 VGT_GS_MAX_VERT_OUT = 0x00028b38, 3243 MAX_VERT_OUT_mask = 0x7ff << 0, 3244 MAX_VERT_OUT_shift = 0, 3245 VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x00028b44, 3246 VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_mask = 0x3f << 0, 3247 VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_shift = 0, 3248 VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x00028b48, 3249 VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_mask = 0x3f << 0, 3250 VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_shift = 0, 3251 VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x00028b4c, 3252 VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_mask = 0x3f << 0, 3253 VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_shift = 0, 3254 VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x00028b50, 3255 VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_mask = 0x3f << 0, 3256 VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_shift = 0, 3257 VGT_SHADER_STAGES_EN = 0x00028b54, 3258 LS_EN_mask = 0x03 << 0, 3259 LS_EN_shift = 0, 3260 LS_STAGE_OFF = 0x00, 3261 LS_STAGE_ON = 0x01, 3262 CS_STAGE_ON = 0x02, 3263 HS_EN_bit = 1 << 2, 3264 ES_EN_mask = 0x03 << 3, 3265 ES_EN_shift = 3, 3266 ES_STAGE_OFF = 0x00, 3267 ES_STAGE_DS = 0x01, 3268 ES_STAGE_REAL = 0x02, 3269 GS_EN_bit = 1 << 5, 3270 VS_EN_mask = 0x03 << 6, 3271 VS_EN_shift = 6, 3272 VS_STAGE_REAL = 0x00, 3273 VS_STAGE_DS = 0x01, 3274 VS_STAGE_COPY_SHADER = 0x02, 3275 VGT_LS_HS_CONFIG = 0x00028b58, 3276 NUM_PATCHES_mask = 0xff << 0, 3277 NUM_PATCHES_shift = 0, 3278 HS_NUM_INPUT_CP_mask = 0x3f << 8, 3279 HS_NUM_INPUT_CP_shift = 8, 3280 HS_NUM_OUTPUT_CP_mask = 0x3f << 14, 3281 HS_NUM_OUTPUT_CP_shift = 14, 3282 VGT_LS_SIZE = 0x00028b5c, 3283 VGT_LS_SIZE__SIZE_mask = 0xff << 0, 3284 VGT_LS_SIZE__SIZE_shift = 0, 3285 PATCH_CP_SIZE_mask = 0x1fff << 8, 3286 PATCH_CP_SIZE_shift = 8, 3287 VGT_HS_SIZE = 0x00028b60, 3288 VGT_HS_SIZE__SIZE_mask = 0xff << 0, 3289 VGT_HS_SIZE__SIZE_shift = 0, 3290/* PATCH_CP_SIZE_mask = 0x1fff << 8, */ 3291/* PATCH_CP_SIZE_shift = 8, */ 3292 VGT_LS_HS_ALLOC = 0x00028b64, 3293 HS_TOTAL_OUTPUT_mask = 0x1fff << 0, 3294 HS_TOTAL_OUTPUT_shift = 0, 3295 LS_HS_TOTAL_OUTPUT_mask = 0x1fff << 13, 3296 LS_HS_TOTAL_OUTPUT_shift = 13, 3297 VGT_HS_PATCH_CONST = 0x00028b68, 3298 VGT_HS_PATCH_CONST__SIZE_mask = 0x1fff << 0, 3299 VGT_HS_PATCH_CONST__SIZE_shift = 0, 3300 VGT_HS_PATCH_CONST__STRIDE_mask = 0x1fff << 13, 3301 VGT_HS_PATCH_CONST__STRIDE_shift = 13, 3302 DB_ALPHA_TO_MASK = 0x00028b70, 3303 ALPHA_TO_MASK_ENABLE_bit = 1 << 0, 3304 ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, 3305 ALPHA_TO_MASK_OFFSET0_shift = 8, 3306 ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10, 3307 ALPHA_TO_MASK_OFFSET1_shift = 10, 3308 ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12, 3309 ALPHA_TO_MASK_OFFSET2_shift = 12, 3310 ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14, 3311 ALPHA_TO_MASK_OFFSET3_shift = 14, 3312 OFFSET_ROUND_bit = 1 << 16, 3313 PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x00028b78, 3314 POLY_OFFSET_NEG_NUM_DB_BITS_mask = 0xff << 0, 3315 POLY_OFFSET_NEG_NUM_DB_BITS_shift = 0, 3316 POLY_OFFSET_DB_IS_FLOAT_FMT_bit = 1 << 8, 3317 PA_SU_POLY_OFFSET_CLAMP = 0x00028b7c, 3318 PA_SU_POLY_OFFSET_FRONT_SCALE = 0x00028b80, 3319 PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x00028b84, 3320 PA_SU_POLY_OFFSET_BACK_SCALE = 0x00028b88, 3321 PA_SU_POLY_OFFSET_BACK_OFFSET = 0x00028b8c, 3322 VGT_GS_INSTANCE_CNT = 0x00028b90, 3323 VGT_GS_INSTANCE_CNT__ENABLE_bit = 1 << 0, 3324 CNT_mask = 0x7f << 2, 3325 CNT_shift = 2, 3326 VGT_STRMOUT_CONFIG = 0x00028b94, 3327 STREAMOUT_0_EN_bit = 1 << 0, 3328 STREAMOUT_1_EN_bit = 1 << 1, 3329 STREAMOUT_2_EN_bit = 1 << 2, 3330 STREAMOUT_3_EN_bit = 1 << 3, 3331 RAST_STREAM_mask = 0x07 << 4, 3332 RAST_STREAM_shift = 4, 3333 VGT_STRMOUT_BUFFER_CONFIG = 0x00028b98, 3334 STREAM_0_BUFFER_EN_mask = 0x0f << 0, 3335 STREAM_0_BUFFER_EN_shift = 0, 3336 STREAM_1_BUFFER_EN_mask = 0x0f << 4, 3337 STREAM_1_BUFFER_EN_shift = 4, 3338 STREAM_2_BUFFER_EN_mask = 0x0f << 8, 3339 STREAM_2_BUFFER_EN_shift = 8, 3340 STREAM_3_BUFFER_EN_mask = 0x0f << 12, 3341 STREAM_3_BUFFER_EN_shift = 12, 3342 CB_IMMED0_BASE = 0x00028b9c, 3343 CB_IMMED0_BASE_num = 12, 3344 PA_SC_LINE_CNTL = 0x00028c00, 3345 EXPAND_LINE_WIDTH_bit = 1 << 9, 3346 LAST_PIXEL_bit = 1 << 10, 3347 PERPENDICULAR_ENDCAP_ENA_bit = 1 << 11, 3348 DX10_DIAMOND_TEST_ENA_bit = 1 << 12, 3349 PA_SC_AA_CONFIG = 0x00028c04, 3350 MSAA_NUM_SAMPLES_mask = 0x03 << 0, 3351 MSAA_NUM_SAMPLES_shift = 0, 3352 AA_MASK_CENTROID_DTMN_bit = 1 << 4, 3353 MAX_SAMPLE_DIST_mask = 0x0f << 13, 3354 MAX_SAMPLE_DIST_shift = 13, 3355 PA_SU_VTX_CNTL = 0x00028c08, 3356 PIX_CENTER_bit = 1 << 0, 3357 PA_SU_VTX_CNTL__ROUND_MODE_mask = 0x03 << 1, 3358 PA_SU_VTX_CNTL__ROUND_MODE_shift = 1, 3359 X_TRUNCATE = 0x00, 3360 X_ROUND = 0x01, 3361 X_ROUND_TO_EVEN = 0x02, 3362 X_ROUND_TO_ODD = 0x03, 3363 QUANT_MODE_mask = 0x07 << 3, 3364 QUANT_MODE_shift = 3, 3365 X_1_16TH = 0x00, 3366 X_1_8TH = 0x01, 3367 X_1_4TH = 0x02, 3368 X_1_2 = 0x03, 3369 X_1 = 0x04, 3370 X_1_256TH = 0x05, 3371 X_1_1024TH = 0x06, 3372 X_1_4096TH = 0x07, 3373 PA_CL_GB_VERT_CLIP_ADJ = 0x00028c0c, 3374 PA_CL_GB_VERT_DISC_ADJ = 0x00028c10, 3375 PA_CL_GB_HORZ_CLIP_ADJ = 0x00028c14, 3376 PA_CL_GB_HORZ_DISC_ADJ = 0x00028c18, 3377 PA_SC_AA_SAMPLE_LOCS_0 = 0x00028c1c, 3378 S0_X_mask = 0x0f << 0, 3379 S0_X_shift = 0, 3380 S0_Y_mask = 0x0f << 4, 3381 S0_Y_shift = 4, 3382 S1_X_mask = 0x0f << 8, 3383 S1_X_shift = 8, 3384 S1_Y_mask = 0x0f << 12, 3385 S1_Y_shift = 12, 3386 S2_X_mask = 0x0f << 16, 3387 S2_X_shift = 16, 3388 S2_Y_mask = 0x0f << 20, 3389 S2_Y_shift = 20, 3390 S3_X_mask = 0x0f << 24, 3391 S3_X_shift = 24, 3392 S3_Y_mask = 0x0f << 28, 3393 S3_Y_shift = 28, 3394 PA_SC_AA_SAMPLE_LOCS_1 = 0x00028c20, 3395/* S0_X_mask = 0x0f << 0, */ 3396/* S0_X_shift = 0, */ 3397/* S0_Y_mask = 0x0f << 4, */ 3398/* S0_Y_shift = 4, */ 3399/* S1_X_mask = 0x0f << 8, */ 3400/* S1_X_shift = 8, */ 3401/* S1_Y_mask = 0x0f << 12, */ 3402/* S1_Y_shift = 12, */ 3403/* S2_X_mask = 0x0f << 16, */ 3404/* S2_X_shift = 16, */ 3405/* S2_Y_mask = 0x0f << 20, */ 3406/* S2_Y_shift = 20, */ 3407/* S3_X_mask = 0x0f << 24, */ 3408/* S3_X_shift = 24, */ 3409/* S3_Y_mask = 0x0f << 28, */ 3410/* S3_Y_shift = 28, */ 3411 PA_SC_AA_SAMPLE_LOCS_2 = 0x00028c24, 3412/* S0_X_mask = 0x0f << 0, */ 3413/* S0_X_shift = 0, */ 3414/* S0_Y_mask = 0x0f << 4, */ 3415/* S0_Y_shift = 4, */ 3416/* S1_X_mask = 0x0f << 8, */ 3417/* S1_X_shift = 8, */ 3418/* S1_Y_mask = 0x0f << 12, */ 3419/* S1_Y_shift = 12, */ 3420/* S2_X_mask = 0x0f << 16, */ 3421/* S2_X_shift = 16, */ 3422/* S2_Y_mask = 0x0f << 20, */ 3423/* S2_Y_shift = 20, */ 3424/* S3_X_mask = 0x0f << 24, */ 3425/* S3_X_shift = 24, */ 3426/* S3_Y_mask = 0x0f << 28, */ 3427/* S3_Y_shift = 28, */ 3428 PA_SC_AA_SAMPLE_LOCS_3 = 0x00028c28, 3429/* S0_X_mask = 0x0f << 0, */ 3430/* S0_X_shift = 0, */ 3431/* S0_Y_mask = 0x0f << 4, */ 3432/* S0_Y_shift = 4, */ 3433/* S1_X_mask = 0x0f << 8, */ 3434/* S1_X_shift = 8, */ 3435/* S1_Y_mask = 0x0f << 12, */ 3436/* S1_Y_shift = 12, */ 3437/* S2_X_mask = 0x0f << 16, */ 3438/* S2_X_shift = 16, */ 3439/* S2_Y_mask = 0x0f << 20, */ 3440/* S2_Y_shift = 20, */ 3441/* S3_X_mask = 0x0f << 24, */ 3442/* S3_X_shift = 24, */ 3443/* S3_Y_mask = 0x0f << 28, */ 3444/* S3_Y_shift = 28, */ 3445 PA_SC_AA_SAMPLE_LOCS_4 = 0x00028c2c, 3446/* S0_X_mask = 0x0f << 0, */ 3447/* S0_X_shift = 0, */ 3448/* S0_Y_mask = 0x0f << 4, */ 3449/* S0_Y_shift = 4, */ 3450/* S1_X_mask = 0x0f << 8, */ 3451/* S1_X_shift = 8, */ 3452/* S1_Y_mask = 0x0f << 12, */ 3453/* S1_Y_shift = 12, */ 3454/* S2_X_mask = 0x0f << 16, */ 3455/* S2_X_shift = 16, */ 3456/* S2_Y_mask = 0x0f << 20, */ 3457/* S2_Y_shift = 20, */ 3458/* S3_X_mask = 0x0f << 24, */ 3459/* S3_X_shift = 24, */ 3460/* S3_Y_mask = 0x0f << 28, */ 3461/* S3_Y_shift = 28, */ 3462 PA_SC_AA_SAMPLE_LOCS_5 = 0x00028c30, 3463/* S0_X_mask = 0x0f << 0, */ 3464/* S0_X_shift = 0, */ 3465/* S0_Y_mask = 0x0f << 4, */ 3466/* S0_Y_shift = 4, */ 3467/* S1_X_mask = 0x0f << 8, */ 3468/* S1_X_shift = 8, */ 3469/* S1_Y_mask = 0x0f << 12, */ 3470/* S1_Y_shift = 12, */ 3471/* S2_X_mask = 0x0f << 16, */ 3472/* S2_X_shift = 16, */ 3473/* S2_Y_mask = 0x0f << 20, */ 3474/* S2_Y_shift = 20, */ 3475/* S3_X_mask = 0x0f << 24, */ 3476/* S3_X_shift = 24, */ 3477/* S3_Y_mask = 0x0f << 28, */ 3478/* S3_Y_shift = 28, */ 3479 PA_SC_AA_SAMPLE_LOCS_6 = 0x00028c34, 3480/* S0_X_mask = 0x0f << 0, */ 3481/* S0_X_shift = 0, */ 3482/* S0_Y_mask = 0x0f << 4, */ 3483/* S0_Y_shift = 4, */ 3484/* S1_X_mask = 0x0f << 8, */ 3485/* S1_X_shift = 8, */ 3486/* S1_Y_mask = 0x0f << 12, */ 3487/* S1_Y_shift = 12, */ 3488/* S2_X_mask = 0x0f << 16, */ 3489/* S2_X_shift = 16, */ 3490/* S2_Y_mask = 0x0f << 20, */ 3491/* S2_Y_shift = 20, */ 3492/* S3_X_mask = 0x0f << 24, */ 3493/* S3_X_shift = 24, */ 3494/* S3_Y_mask = 0x0f << 28, */ 3495/* S3_Y_shift = 28, */ 3496 PA_SC_AA_SAMPLE_LOCS_7 = 0x00028c38, 3497/* S0_X_mask = 0x0f << 0, */ 3498/* S0_X_shift = 0, */ 3499/* S0_Y_mask = 0x0f << 4, */ 3500/* S0_Y_shift = 4, */ 3501/* S1_X_mask = 0x0f << 8, */ 3502/* S1_X_shift = 8, */ 3503/* S1_Y_mask = 0x0f << 12, */ 3504/* S1_Y_shift = 12, */ 3505/* S2_X_mask = 0x0f << 16, */ 3506/* S2_X_shift = 16, */ 3507/* S2_Y_mask = 0x0f << 20, */ 3508/* S2_Y_shift = 20, */ 3509/* S3_X_mask = 0x0f << 24, */ 3510/* S3_X_shift = 24, */ 3511/* S3_Y_mask = 0x0f << 28, */ 3512/* S3_Y_shift = 28, */ 3513 PA_SC_AA_MASK = 0x00028c3c, 3514 VGT_VERTEX_REUSE_BLOCK_CNTL = 0x00028c58, 3515 VTX_REUSE_DEPTH_mask = 0xff << 0, 3516 VTX_REUSE_DEPTH_shift = 0, 3517 VGT_OUT_DEALLOC_CNTL = 0x00028c5c, 3518 DEALLOC_DIST_mask = 0x7f << 0, 3519 DEALLOC_DIST_shift = 0, 3520 CB_COLOR0_BASE = 0x00028c60, 3521 CB_COLOR0_BASE_num = 12, 3522 CB_COLOR0_BASE_offset = 51, 3523 CB_COLOR0_PITCH = 0x00028c64, 3524 CB_COLOR0_PITCH_num = 12, 3525 CB_COLOR0_PITCH_offset = 51, 3526 CB_COLOR0_PITCH__TILE_MAX_mask = 0x7ff << 0, 3527 CB_COLOR0_PITCH__TILE_MAX_shift = 0, 3528 CB_COLOR0_SLICE = 0x00028c68, 3529 CB_COLOR0_SLICE_num = 12, 3530 CB_COLOR0_SLICE_offset = 51, 3531 CB_COLOR0_SLICE__TILE_MAX_mask = 0x3fffff << 0, 3532 CB_COLOR0_SLICE__TILE_MAX_shift = 0, 3533 CB_COLOR0_VIEW = 0x00028c6c, 3534 CB_COLOR0_VIEW_num = 12, 3535 CB_COLOR0_VIEW_offset = 51, 3536/* SLICE_START_mask = 0x7ff << 0, */ 3537/* SLICE_START_shift = 0, */ 3538/* SLICE_MAX_mask = 0x7ff << 13, */ 3539/* SLICE_MAX_shift = 13, */ 3540 CB_COLOR0_INFO = 0x00028c70, 3541 CB_COLOR0_INFO_num = 12, 3542 CB_COLOR0_INFO_offset = 51, 3543 ENDIAN_mask = 0x03 << 0, 3544 ENDIAN_shift = 0, 3545 ENDIAN_NONE = 0x00, 3546 ENDIAN_8IN16 = 0x01, 3547 ENDIAN_8IN32 = 0x02, 3548 ENDIAN_8IN64 = 0x03, 3549 CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2, 3550 CB_COLOR0_INFO__FORMAT_shift = 2, 3551 COLOR_INVALID = 0x00, 3552 COLOR_8 = 0x01, 3553 COLOR_16 = 0x05, 3554 COLOR_16_FLOAT = 0x06, 3555 COLOR_8_8 = 0x07, 3556 COLOR_5_6_5 = 0x08, 3557 COLOR_1_5_5_5 = 0x0a, 3558 COLOR_4_4_4_4 = 0x0b, 3559 COLOR_5_5_5_1 = 0x0c, 3560 COLOR_32 = 0x0d, 3561 COLOR_32_FLOAT = 0x0e, 3562 COLOR_16_16 = 0x0f, 3563 COLOR_16_16_FLOAT = 0x10, 3564 COLOR_8_24 = 0x11, 3565 COLOR_24_8 = 0x13, 3566 COLOR_10_11_11 = 0x15, 3567 COLOR_10_11_11_FLOAT = 0x16, 3568 COLOR_2_10_10_10 = 0x19, 3569 COLOR_8_8_8_8 = 0x1a, 3570 COLOR_10_10_10_2 = 0x1b, 3571 COLOR_X24_8_32_FLOAT = 0x1c, 3572 COLOR_32_32 = 0x1d, 3573 COLOR_32_32_FLOAT = 0x1e, 3574 COLOR_16_16_16_16 = 0x1f, 3575 COLOR_16_16_16_16_FLOAT = 0x20, 3576 COLOR_32_32_32_32 = 0x22, 3577 COLOR_32_32_32_32_FLOAT = 0x23, 3578 CB_COLOR0_INFO__ARRAY_MODE_mask = 0x0f << 8, 3579 CB_COLOR0_INFO__ARRAY_MODE_shift = 8, 3580/* ARRAY_LINEAR_GENERAL = 0x00, */ 3581/* ARRAY_LINEAR_ALIGNED = 0x01, */ 3582/* ARRAY_1D_TILED_THIN1 = 0x02, */ 3583/* ARRAY_2D_TILED_THIN1 = 0x04, */ 3584 NUMBER_TYPE_mask = 0x07 << 12, 3585 NUMBER_TYPE_shift = 12, 3586 NUMBER_UNORM = 0x00, 3587 NUMBER_SNORM = 0x01, 3588 NUMBER_UINT = 0x04, 3589 NUMBER_SINT = 0x05, 3590 NUMBER_SRGB = 0x06, 3591 NUMBER_FLOAT = 0x07, 3592 COMP_SWAP_mask = 0x03 << 15, 3593 COMP_SWAP_shift = 15, 3594 SWAP_STD = 0x00, 3595 SWAP_ALT = 0x01, 3596 SWAP_STD_REV = 0x02, 3597 SWAP_ALT_REV = 0x03, 3598 FAST_CLEAR_bit = 1 << 17, 3599 COMPRESSION_bit = 1 << 18, 3600 BLEND_CLAMP_bit = 1 << 19, 3601 BLEND_BYPASS_bit = 1 << 20, 3602 SIMPLE_FLOAT_bit = 1 << 21, 3603 CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 22, 3604 CB_COLOR0_INFO__TILE_COMPACT_bit = 1 << 23, 3605 SOURCE_FORMAT_mask = 0x03 << 24, 3606 SOURCE_FORMAT_shift = 24, 3607 EXPORT_4C_32BPC = 0x00, 3608 EXPORT_4C_16BPC = 0x01, 3609 RAT_bit = 1 << 26, 3610 RESOURCE_TYPE_mask = 0x07 << 27, 3611 RESOURCE_TYPE_shift = 27, 3612 BUFFER = 0x00, 3613 TEXTURE1D = 0x01, 3614 TEXTURE1DARRAY = 0x02, 3615 TEXTURE2D = 0x03, 3616 TEXTURE2DARRAY = 0x04, 3617 TEXTURE3D = 0x05, 3618 CB_COLOR0_ATTRIB = 0x00028c74, 3619 CB_COLOR0_ATTRIB_num = 12, 3620 CB_COLOR0_ATTRIB_offset = 51, 3621 IGNORE_SHADER_ENGINE_TILING_bit = 1 << 3, 3622 CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit = 1 << 4, 3623 CB_COLOR0_ATTRIB__TILE_SPLIT_mask = 0x0f << 5, 3624 CB_COLOR0_ATTRIB__TILE_SPLIT_shift = 5, 3625/* ADDR_SURF_TILE_SPLIT_64B = 0x00, */ 3626/* ADDR_SURF_TILE_SPLIT_128B = 0x01, */ 3627/* ADDR_SURF_TILE_SPLIT_256B = 0x02, */ 3628/* ADDR_SURF_TILE_SPLIT_512B = 0x03, */ 3629/* ADDR_SURF_TILE_SPLIT_1KB = 0x04, */ 3630/* ADDR_SURF_TILE_SPLIT_2KB = 0x05, */ 3631/* ADDR_SURF_TILE_SPLIT_4KB = 0x06, */ 3632 CB_COLOR0_ATTRIB__NUM_BANKS_mask = 0x03 << 10, 3633 CB_COLOR0_ATTRIB__NUM_BANKS_shift = 10, 3634/* ADDR_SURF_2_BANK = 0x00, */ 3635/* ADDR_SURF_4_BANK = 0x01, */ 3636/* ADDR_SURF_8_BANK = 0x02, */ 3637/* ADDR_SURF_16_BANK = 0x03, */ 3638 CB_COLOR0_ATTRIB__BANK_WIDTH_mask = 0x03 << 13, 3639 CB_COLOR0_ATTRIB__BANK_WIDTH_shift = 13, 3640/* ADDR_SURF_BANK_WIDTH_1 = 0x00, */ 3641/* ADDR_SURF_BANK_WIDTH_2 = 0x01, */ 3642/* ADDR_SURF_BANK_WIDTH_4 = 0x02, */ 3643/* ADDR_SURF_BANK_WIDTH_8 = 0x03, */ 3644 CB_COLOR0_ATTRIB__BANK_HEIGHT_mask = 0x03 << 16, 3645 CB_COLOR0_ATTRIB__BANK_HEIGHT_shift = 16, 3646/* ADDR_SURF_BANK_HEIGHT_1 = 0x00, */ 3647/* ADDR_SURF_BANK_HEIGHT_2 = 0x01, */ 3648/* ADDR_SURF_BANK_HEIGHT_4 = 0x02, */ 3649/* ADDR_SURF_BANK_HEIGHT_8 = 0x03, */ 3650 CB_COLOR0_ATTRIB__MACRO_TILE_ASPECT_mask = 0x03 << 19, 3651 CB_COLOR0_ATTRIB__MACRO_TILE_ASPECT_shift = 19, 3652/* ADDR_SURF_MACRO_ASPECT_1 = 0x00, */ 3653/* ADDR_SURF_MACRO_ASPECT_2 = 0x01, */ 3654/* ADDR_SURF_MACRO_ASPECT_4 = 0x02, */ 3655/* ADDR_SURF_MACRO_ASPECT_8 = 0x03, */ 3656 FMASK_BANK_HEIGHT_mask = 0x03 << 22, 3657 FMASK_BANK_HEIGHT_shift = 22, 3658/* ADDR_SURF_BANK_HEIGHT_1 = 0x00, */ 3659/* ADDR_SURF_BANK_HEIGHT_2 = 0x01, */ 3660/* ADDR_SURF_BANK_HEIGHT_4 = 0x02, */ 3661/* ADDR_SURF_BANK_HEIGHT_8 = 0x03, */ 3662 CB_COLOR0_DIM = 0x00028c78, 3663 CB_COLOR0_DIM_num = 12, 3664 CB_COLOR0_DIM_offset = 51, 3665 WIDTH_MAX_mask = 0xffff << 0, 3666 WIDTH_MAX_shift = 0, 3667 HEIGHT_MAX_mask = 0xffff << 16, 3668 HEIGHT_MAX_shift = 16, 3669 CB_COLOR0_CMASK = 0x00028c7c, 3670 CB_COLOR0_CMASK_num = 8, 3671 CB_COLOR0_CMASK_offset = 60, 3672 CB_COLOR0_CMASK_SLICE = 0x00028c80, 3673 CB_COLOR0_CMASK_SLICE_num = 8, 3674 CB_COLOR0_CMASK_SLICE_offset = 60, 3675 CB_COLOR0_CMASK_SLICE__TILE_MAX_mask = 0x3fff << 0, 3676 CB_COLOR0_CMASK_SLICE__TILE_MAX_shift = 0, 3677 CB_COLOR0_FMASK = 0x00028c84, 3678 CB_COLOR0_FMASK_num = 8, 3679 CB_COLOR0_FMASK_offset = 60, 3680 CB_COLOR0_FMASK_SLICE = 0x00028c88, 3681 CB_COLOR0_FMASK_SLICE_num = 8, 3682 CB_COLOR0_FMASK_SLICE_offset = 60, 3683 CB_COLOR0_FMASK_SLICE__TILE_MAX_mask = 0x3fffff << 0, 3684 CB_COLOR0_FMASK_SLICE__TILE_MAX_shift = 0, 3685 CB_COLOR0_CLEAR_WORD0 = 0x00028c8c, 3686 CB_COLOR0_CLEAR_WORD0_num = 8, 3687 CB_COLOR0_CLEAR_WORD0_offset = 60, 3688 CB_COLOR0_CLEAR_WORD1 = 0x00028c90, 3689 CB_COLOR0_CLEAR_WORD1_num = 8, 3690 CB_COLOR0_CLEAR_WORD1_offset = 60, 3691 CB_COLOR0_CLEAR_WORD2 = 0x00028c94, 3692 CB_COLOR0_CLEAR_WORD2_num = 8, 3693 CB_COLOR0_CLEAR_WORD2_offset = 60, 3694 CB_COLOR0_CLEAR_WORD3 = 0x00028c98, 3695 CB_COLOR0_CLEAR_WORD3_num = 8, 3696 CB_COLOR0_CLEAR_WORD3_offset = 60, 3697 SQ_ALU_CONST_CACHE_HS_0 = 0x00028f00, 3698 SQ_ALU_CONST_CACHE_HS_0_num = 16, 3699 SQ_ALU_CONST_CACHE_LS_0 = 0x00028f40, 3700 SQ_ALU_CONST_CACHE_LS_0_num = 16, 3701 SQ_ALU_CONST_BUFFER_SIZE_HS_0 = 0x00028f80, 3702 SQ_ALU_CONST_BUFFER_SIZE_HS_0_num = 16, 3703 SQ_ALU_CONST_BUFFER_SIZE_HS_0__DATA_mask = 0x1ff << 0, 3704 SQ_ALU_CONST_BUFFER_SIZE_HS_0__DATA_shift = 0, 3705 SQ_ALU_CONST_BUFFER_SIZE_LS_0 = 0x00028fc0, 3706 SQ_ALU_CONST_BUFFER_SIZE_LS_0_num = 16, 3707 SQ_ALU_CONST_BUFFER_SIZE_LS_0__DATA_mask = 0x1ff << 0, 3708 SQ_ALU_CONST_BUFFER_SIZE_LS_0__DATA_shift = 0, 3709 SQ_VTX_CONSTANT_WORD0_0 = 0x00030000, 3710 SQ_TEX_RESOURCE_WORD0_0 = 0x00030000, 3711 DIM_mask = 0x07 << 0, 3712 DIM_shift = 0, 3713 SQ_TEX_DIM_1D = 0x00, 3714 SQ_TEX_DIM_2D = 0x01, 3715 SQ_TEX_DIM_3D = 0x02, 3716 SQ_TEX_DIM_CUBEMAP = 0x03, 3717 SQ_TEX_DIM_1D_ARRAY = 0x04, 3718 SQ_TEX_DIM_2D_ARRAY = 0x05, 3719 SQ_TEX_DIM_2D_MSAA = 0x06, 3720 SQ_TEX_DIM_2D_ARRAY_MSAA = 0x07, 3721/* IGNORE_SHADER_ENGINE_TILING_bit = 1 << 3, */ 3722 SQ_TEX_RESOURCE_WORD0_0__NON_DISP_TILING_ORDER_bit= 1 << 5, 3723 PITCH_mask = 0xfff << 6, 3724 PITCH_shift = 6, 3725 TEX_WIDTH_mask = 0x3fff << 18, 3726 TEX_WIDTH_shift = 18, 3727 SQ_VTX_CONSTANT_WORD1_0 = 0x00030004, 3728 SQ_TEX_RESOURCE_WORD1_0 = 0x00030004, 3729 TEX_HEIGHT_mask = 0x3fff << 0, 3730 TEX_HEIGHT_shift = 0, 3731 TEX_DEPTH_mask = 0x1fff << 14, 3732 TEX_DEPTH_shift = 14, 3733 SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask = 0x0f << 28, 3734 SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift = 28, 3735 SQ_VTX_CONSTANT_WORD2_0 = 0x00030008, 3736 BASE_ADDRESS_HI_mask = 0xff << 0, 3737 BASE_ADDRESS_HI_shift = 0, 3738 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask = 0x7ff << 8, 3739 SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift = 8, 3740 SQ_VTX_CONSTANT_WORD2_0__CLAMP_X_bit = 1 << 19, 3741 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, 3742 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift = 20, 3743 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask = 0x03 << 26, 3744 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift = 26, 3745/* SQ_NUM_FORMAT_NORM = 0x00, */ 3746/* SQ_NUM_FORMAT_INT = 0x01, */ 3747/* SQ_NUM_FORMAT_SCALED = 0x02, */ 3748 SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit = 1 << 28, 3749 SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit = 1 << 29, 3750 SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask = 0x03 << 30, 3751 SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift = 30, 3752/* SQ_ENDIAN_NONE = 0x00, */ 3753/* SQ_ENDIAN_8IN16 = 0x01, */ 3754/* SQ_ENDIAN_8IN32 = 0x02, */ 3755 SQ_TEX_RESOURCE_WORD2_0 = 0x00030008, 3756 SQ_VTX_CONSTANT_WORD3_0 = 0x0003000c, 3757 SQ_VTX_CONSTANT_WORD3_0__UNCACHED_bit = 1 << 2, 3758 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask = 0x07 << 3, 3759 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift = 3, 3760/* SQ_SEL_X = 0x00, */ 3761/* SQ_SEL_Y = 0x01, */ 3762/* SQ_SEL_Z = 0x02, */ 3763/* SQ_SEL_W = 0x03, */ 3764/* SQ_SEL_0 = 0x04, */ 3765/* SQ_SEL_1 = 0x05, */ 3766 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask = 0x07 << 6, 3767 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift = 6, 3768/* SQ_SEL_X = 0x00, */ 3769/* SQ_SEL_Y = 0x01, */ 3770/* SQ_SEL_Z = 0x02, */ 3771/* SQ_SEL_W = 0x03, */ 3772/* SQ_SEL_0 = 0x04, */ 3773/* SQ_SEL_1 = 0x05, */ 3774 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask = 0x07 << 9, 3775 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift = 9, 3776/* SQ_SEL_X = 0x00, */ 3777/* SQ_SEL_Y = 0x01, */ 3778/* SQ_SEL_Z = 0x02, */ 3779/* SQ_SEL_W = 0x03, */ 3780/* SQ_SEL_0 = 0x04, */ 3781/* SQ_SEL_1 = 0x05, */ 3782 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask = 0x07 << 12, 3783 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift = 12, 3784/* SQ_SEL_X = 0x00, */ 3785/* SQ_SEL_Y = 0x01, */ 3786/* SQ_SEL_Z = 0x02, */ 3787/* SQ_SEL_W = 0x03, */ 3788/* SQ_SEL_0 = 0x04, */ 3789/* SQ_SEL_1 = 0x05, */ 3790 SQ_TEX_RESOURCE_WORD3_0 = 0x0003000c, 3791 SQ_TEX_RESOURCE_WORD4_0 = 0x00030010, 3792 FORMAT_COMP_X_mask = 0x03 << 0, 3793 FORMAT_COMP_X_shift = 0, 3794 SQ_FORMAT_COMP_UNSIGNED = 0x00, 3795 SQ_FORMAT_COMP_SIGNED = 0x01, 3796 SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, 3797 FORMAT_COMP_Y_mask = 0x03 << 2, 3798 FORMAT_COMP_Y_shift = 2, 3799/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ 3800/* SQ_FORMAT_COMP_SIGNED = 0x01, */ 3801/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ 3802 FORMAT_COMP_Z_mask = 0x03 << 4, 3803 FORMAT_COMP_Z_shift = 4, 3804/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ 3805/* SQ_FORMAT_COMP_SIGNED = 0x01, */ 3806/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ 3807 FORMAT_COMP_W_mask = 0x03 << 6, 3808 FORMAT_COMP_W_shift = 6, 3809/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ 3810/* SQ_FORMAT_COMP_SIGNED = 0x01, */ 3811/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ 3812 SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask = 0x03 << 8, 3813 SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift = 8, 3814/* SQ_NUM_FORMAT_NORM = 0x00, */ 3815/* SQ_NUM_FORMAT_INT = 0x01, */ 3816/* SQ_NUM_FORMAT_SCALED = 0x02, */ 3817 SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit = 1 << 10, 3818 SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit = 1 << 11, 3819 SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask = 0x03 << 12, 3820 SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift = 12, 3821/* SQ_ENDIAN_NONE = 0x00, */ 3822/* SQ_ENDIAN_8IN16 = 0x01, */ 3823/* SQ_ENDIAN_8IN32 = 0x02, */ 3824 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask = 0x07 << 16, 3825 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift = 16, 3826/* SQ_SEL_X = 0x00, */ 3827/* SQ_SEL_Y = 0x01, */ 3828/* SQ_SEL_Z = 0x02, */ 3829/* SQ_SEL_W = 0x03, */ 3830/* SQ_SEL_0 = 0x04, */ 3831/* SQ_SEL_1 = 0x05, */ 3832 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask = 0x07 << 19, 3833 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift = 19, 3834/* SQ_SEL_X = 0x00, */ 3835/* SQ_SEL_Y = 0x01, */ 3836/* SQ_SEL_Z = 0x02, */ 3837/* SQ_SEL_W = 0x03, */ 3838/* SQ_SEL_0 = 0x04, */ 3839/* SQ_SEL_1 = 0x05, */ 3840 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask = 0x07 << 22, 3841 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift = 22, 3842/* SQ_SEL_X = 0x00, */ 3843/* SQ_SEL_Y = 0x01, */ 3844/* SQ_SEL_Z = 0x02, */ 3845/* SQ_SEL_W = 0x03, */ 3846/* SQ_SEL_0 = 0x04, */ 3847/* SQ_SEL_1 = 0x05, */ 3848 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask = 0x07 << 25, 3849 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift = 25, 3850/* SQ_SEL_X = 0x00, */ 3851/* SQ_SEL_Y = 0x01, */ 3852/* SQ_SEL_Z = 0x02, */ 3853/* SQ_SEL_W = 0x03, */ 3854/* SQ_SEL_0 = 0x04, */ 3855/* SQ_SEL_1 = 0x05, */ 3856 BASE_LEVEL_mask = 0x0f << 28, 3857 BASE_LEVEL_shift = 28, 3858 SQ_VTX_CONSTANT_WORD4_0 = 0x00030010, 3859 SQ_TEX_RESOURCE_WORD5_0 = 0x00030014, 3860 LAST_LEVEL_mask = 0x0f << 0, 3861 LAST_LEVEL_shift = 0, 3862 BASE_ARRAY_mask = 0x1fff << 4, 3863 BASE_ARRAY_shift = 4, 3864 LAST_ARRAY_mask = 0x1fff << 17, 3865 LAST_ARRAY_shift = 17, 3866 SQ_TEX_RESOURCE_WORD6_0 = 0x00030018, 3867 PERF_MODULATION_mask = 0x07 << 3, 3868 PERF_MODULATION_shift = 3, 3869 INTERLACED_bit = 1 << 6, 3870 SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_mask = 0xfff << 8, 3871 SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_shift = 8, 3872 SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_mask = 0x07 << 29, 3873 SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_shift = 29, 3874 SQ_ADDR_SURF_TILE_SPLIT_64B = 0x00, 3875 SQ_ADDR_SURF_TILE_SPLIT_128B = 0x01, 3876 SQ_ADDR_SURF_TILE_SPLIT_256B = 0x02, 3877 SQ_ADDR_SURF_TILE_SPLIT_512B = 0x03, 3878 SQ_ADDR_SURF_TILE_SPLIT_1KB = 0x04, 3879 SQ_ADDR_SURF_TILE_SPLIT_2KB = 0x05, 3880 SQ_ADDR_SURF_TILE_SPLIT_4KB = 0x06, 3881 SQ_VTX_CONSTANT_WORD7_0 = 0x0003001c, 3882 SQ_VTX_CONSTANT_WORD7_0__TYPE_mask = 0x03 << 30, 3883 SQ_VTX_CONSTANT_WORD7_0__TYPE_shift = 30, 3884 SQ_TEX_VTX_INVALID_TEXTURE = 0x00, 3885 SQ_TEX_VTX_INVALID_BUFFER = 0x01, 3886 SQ_TEX_VTX_VALID_TEXTURE = 0x02, 3887 SQ_TEX_VTX_VALID_BUFFER = 0x03, 3888 SQ_TEX_RESOURCE_WORD7_0 = 0x0003001c, 3889 SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask = 0x3f << 0, 3890 SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift = 0, 3891 SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_mask = 0x03 << 6, 3892 SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_shift = 6, 3893 SQ_ADDR_SURF_MACRO_ASPECT_1 = 0x00, 3894 SQ_ADDR_SURF_MACRO_ASPECT_2 = 0x01, 3895 SQ_ADDR_SURF_MACRO_ASPECT_4 = 0x02, 3896 SQ_ADDR_SURF_MACRO_ASPECT_8 = 0x03, 3897 SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_mask = 0x03 << 8, 3898 SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_shift = 8, 3899 SQ_ADDR_SURF_BANK_WH_1 = 0x00, 3900 SQ_ADDR_SURF_BANK_WH_2 = 0x01, 3901 SQ_ADDR_SURF_BANK_WH_4 = 0x02, 3902 SQ_ADDR_SURF_BANK_WH_8 = 0x03, 3903 SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_mask = 0x03 << 10, 3904 SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_shift = 10, 3905/* SQ_ADDR_SURF_BANK_WH_1 = 0x00, */ 3906/* SQ_ADDR_SURF_BANK_WH_2 = 0x01, */ 3907/* SQ_ADDR_SURF_BANK_WH_4 = 0x02, */ 3908/* SQ_ADDR_SURF_BANK_WH_8 = 0x03, */ 3909 DEPTH_SAMPLE_ORDER_bit = 1 << 15, 3910 SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_mask = 0x03 << 16, 3911 SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_shift = 16, 3912 SQ_ADDR_SURF_2_BANK = 0x00, 3913 SQ_ADDR_SURF_4_BANK = 0x01, 3914 SQ_ADDR_SURF_8_BANK = 0x02, 3915 SQ_ADDR_SURF_16_BANK = 0x03, 3916 SQ_TEX_RESOURCE_WORD7_0__TYPE_mask = 0x03 << 30, 3917 SQ_TEX_RESOURCE_WORD7_0__TYPE_shift = 30, 3918/* SQ_TEX_VTX_INVALID_TEXTURE = 0x00, */ 3919/* SQ_TEX_VTX_INVALID_BUFFER = 0x01, */ 3920/* SQ_TEX_VTX_VALID_TEXTURE = 0x02, */ 3921/* SQ_TEX_VTX_VALID_BUFFER = 0x03, */ 3922 SQ_LOOP_CONST_DX10_0 = 0x0003a200, 3923 SQ_LOOP_CONST_0 = 0x0003a200, 3924 SQ_LOOP_CONST_0__COUNT_mask = 0xfff << 0, 3925 SQ_LOOP_CONST_0__COUNT_shift = 0, 3926 INIT_mask = 0xfff << 12, 3927 INIT_shift = 12, 3928 INC_mask = 0xff << 24, 3929 INC_shift = 24, 3930 SQ_JUMPTABLE_CONST_0 = 0x0003a200, 3931 CONST_A_mask = 0xff << 0, 3932 CONST_A_shift = 0, 3933 CONST_B_mask = 0xff << 8, 3934 CONST_B_shift = 8, 3935 CONST_C_mask = 0xff << 16, 3936 CONST_C_shift = 16, 3937 CONST_D_mask = 0xff << 24, 3938 CONST_D_shift = 24, 3939 SQ_BOOL_CONST_0 = 0x0003a500, 3940 SQ_BOOL_CONST_0_num = 6, 3941 SQ_TEX_SAMPLER_WORD0_0 = 0x0003c000, 3942 SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x07 << 0, 3943 SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0, 3944 SQ_TEX_WRAP = 0x00, 3945 SQ_TEX_MIRROR = 0x01, 3946 SQ_TEX_CLAMP_LAST_TEXEL = 0x02, 3947 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, 3948 SQ_TEX_CLAMP_HALF_BORDER = 0x04, 3949 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, 3950 SQ_TEX_CLAMP_BORDER = 0x06, 3951 SQ_TEX_MIRROR_ONCE_BORDER = 0x07, 3952 CLAMP_Y_mask = 0x07 << 3, 3953 CLAMP_Y_shift = 3, 3954/* SQ_TEX_WRAP = 0x00, */ 3955/* SQ_TEX_MIRROR = 0x01, */ 3956/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ 3957/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ 3958/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ 3959/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ 3960/* SQ_TEX_CLAMP_BORDER = 0x06, */ 3961/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ 3962 CLAMP_Z_mask = 0x07 << 6, 3963 CLAMP_Z_shift = 6, 3964/* SQ_TEX_WRAP = 0x00, */ 3965/* SQ_TEX_MIRROR = 0x01, */ 3966/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ 3967/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ 3968/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ 3969/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ 3970/* SQ_TEX_CLAMP_BORDER = 0x06, */ 3971/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ 3972 XY_MAG_FILTER_mask = 0x03 << 9, 3973 XY_MAG_FILTER_shift = 9, 3974 SQ_TEX_XY_FILTER_POINT = 0x00, 3975 SQ_TEX_XY_FILTER_BILINEAR = 0x01, 3976 XY_MIN_FILTER_mask = 0x03 << 11, 3977 XY_MIN_FILTER_shift = 11, 3978/* SQ_TEX_XY_FILTER_POINT = 0x00, */ 3979/* SQ_TEX_XY_FILTER_BILINEAR = 0x01, */ 3980 Z_FILTER_mask = 0x03 << 13, 3981 Z_FILTER_shift = 13, 3982 SQ_TEX_Z_FILTER_NONE = 0x00, 3983 SQ_TEX_Z_FILTER_POINT = 0x01, 3984 SQ_TEX_Z_FILTER_LINEAR = 0x02, 3985 MIP_FILTER_mask = 0x03 << 15, 3986 MIP_FILTER_shift = 15, 3987/* SQ_TEX_Z_FILTER_NONE = 0x00, */ 3988/* SQ_TEX_Z_FILTER_POINT = 0x01, */ 3989/* SQ_TEX_Z_FILTER_LINEAR = 0x02, */ 3990 BORDER_COLOR_TYPE_mask = 0x03 << 20, 3991 BORDER_COLOR_TYPE_shift = 20, 3992 SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00, 3993 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x01, 3994 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x02, 3995 SQ_TEX_BORDER_COLOR_REGISTER = 0x03, 3996 DEPTH_COMPARE_FUNCTION_mask = 0x07 << 22, 3997 DEPTH_COMPARE_FUNCTION_shift = 22, 3998 SQ_TEX_DEPTH_COMPARE_NEVER = 0x00, 3999 SQ_TEX_DEPTH_COMPARE_LESS = 0x01, 4000 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x02, 4001 SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x03, 4002 SQ_TEX_DEPTH_COMPARE_GREATER = 0x04, 4003 SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x05, 4004 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x06, 4005 SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x07, 4006 CHROMA_KEY_mask = 0x03 << 25, 4007 CHROMA_KEY_shift = 25, 4008 SQ_TEX_CHROMA_KEY_DISABLED = 0x00, 4009 SQ_TEX_CHROMA_KEY_KILL = 0x01, 4010 SQ_TEX_CHROMA_KEY_BLEND = 0x02, 4011 SQ_TEX_SAMPLER_WORD1_0 = 0x0003c004, 4012 SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask = 0xfff << 0, 4013 SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift = 0, 4014 MAX_LOD_mask = 0xfff << 12, 4015 MAX_LOD_shift = 12, 4016 PERF_MIP_mask = 0x0f << 24, 4017 PERF_MIP_shift = 24, 4018 PERF_Z_mask = 0x0f << 28, 4019 PERF_Z_shift = 28, 4020 SQ_TEX_SAMPLER_WORD2_0 = 0x0003c008, 4021 SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask = 0x3fff << 0, 4022 SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift = 0, 4023 LOD_BIAS_SEC_mask = 0x3f << 14, 4024 LOD_BIAS_SEC_shift = 14, 4025 MC_COORD_TRUNCATE_bit = 1 << 20, 4026 SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 21, 4027 TRUNCATE_COORD_bit = 1 << 28, 4028 SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_bit = 1 << 29, 4029 SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31, 4030 SQ_VTX_BASE_VTX_LOC = 0x0003cff0, 4031 SQ_VTX_START_INST_LOC = 0x0003cff4, 4032 SQ_TEX_SAMPLER_CLEAR = 0x0003ff00, 4033 SQ_TEX_RESOURCE_CLEAR = 0x0003ff04, 4034 SQ_LOOP_BOOL_CLEAR = 0x0003ff08, 4035 4036} ; 4037 4038#endif /* _EVERGREEN_REG_AUTO_H */ 4039 4040