1de2362d3Smrg/* 2de2362d3Smrg * RadeonHD R6xx, R7xx Register documentation 3de2362d3Smrg * 4de2362d3Smrg * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. 5de2362d3Smrg * Copyright (C) 2008-2009 Matthias Hopf 6de2362d3Smrg * 7de2362d3Smrg * Permission is hereby granted, free of charge, to any person obtaining a 8de2362d3Smrg * copy of this software and associated documentation files (the "Software"), 9de2362d3Smrg * to deal in the Software without restriction, including without limitation 10de2362d3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11de2362d3Smrg * and/or sell copies of the Software, and to permit persons to whom the 12de2362d3Smrg * Software is furnished to do so, subject to the following conditions: 13de2362d3Smrg * 14de2362d3Smrg * The above copyright notice and this permission notice shall be included 15de2362d3Smrg * in all copies or substantial portions of the Software. 16de2362d3Smrg * 17de2362d3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18de2362d3Smrg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19de2362d3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20de2362d3Smrg * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 21de2362d3Smrg * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22de2362d3Smrg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23de2362d3Smrg */ 24de2362d3Smrg 25de2362d3Smrg#ifndef _R600_REG_R6xx_H_ 26de2362d3Smrg#define _R600_REG_R6xx_H_ 27de2362d3Smrg 28de2362d3Smrg/* 29de2362d3Smrg * Registers for R6xx chips that are not documented yet 30de2362d3Smrg */ 31de2362d3Smrg 32de2362d3Smrgenum { 33de2362d3Smrg 34de2362d3Smrg MM_INDEX = 0x0000, 35de2362d3Smrg MM_DATA = 0x0004, 36de2362d3Smrg 37de2362d3Smrg SRBM_STATUS = 0x0e50, 38de2362d3Smrg RLC_RQ_PENDING_bit = 1 << 3, 39de2362d3Smrg RCU_RQ_PENDING_bit = 1 << 4, 40de2362d3Smrg GRBM_RQ_PENDING_bit = 1 << 5, 41de2362d3Smrg HI_RQ_PENDING_bit = 1 << 6, 42de2362d3Smrg IO_EXTERN_SIGNAL_bit = 1 << 7, 43de2362d3Smrg VMC_BUSY_bit = 1 << 8, 44de2362d3Smrg MCB_BUSY_bit = 1 << 9, 45de2362d3Smrg MCDZ_BUSY_bit = 1 << 10, 46de2362d3Smrg MCDY_BUSY_bit = 1 << 11, 47de2362d3Smrg MCDX_BUSY_bit = 1 << 12, 48de2362d3Smrg MCDW_BUSY_bit = 1 << 13, 49de2362d3Smrg SEM_BUSY_bit = 1 << 14, 50de2362d3Smrg SRBM_STATUS__RLC_BUSY_bit = 1 << 15, 51de2362d3Smrg PDMA_BUSY_bit = 1 << 16, 52de2362d3Smrg IH_BUSY_bit = 1 << 17, 53de2362d3Smrg CSC_BUSY_bit = 1 << 20, 54de2362d3Smrg CMC7_BUSY_bit = 1 << 21, 55de2362d3Smrg CMC6_BUSY_bit = 1 << 22, 56de2362d3Smrg CMC5_BUSY_bit = 1 << 23, 57de2362d3Smrg CMC4_BUSY_bit = 1 << 24, 58de2362d3Smrg CMC3_BUSY_bit = 1 << 25, 59de2362d3Smrg CMC2_BUSY_bit = 1 << 26, 60de2362d3Smrg CMC1_BUSY_bit = 1 << 27, 61de2362d3Smrg CMC0_BUSY_bit = 1 << 28, 62de2362d3Smrg BIF_BUSY_bit = 1 << 29, 63de2362d3Smrg IDCT_BUSY_bit = 1 << 30, 64de2362d3Smrg 65de2362d3Smrg SRBM_READ_ERROR = 0x0e98, 66de2362d3Smrg READ_ADDRESS_mask = 0xffff << 2, 67de2362d3Smrg READ_ADDRESS_shift = 2, 68de2362d3Smrg READ_REQUESTER_HI_bit = 1 << 24, 69de2362d3Smrg READ_REQUESTER_GRBM_bit = 1 << 25, 70de2362d3Smrg READ_REQUESTER_RCU_bit = 1 << 26, 71de2362d3Smrg READ_REQUESTER_RLC_bit = 1 << 27, 72de2362d3Smrg READ_ERROR_bit = 1 << 31, 73de2362d3Smrg 74de2362d3Smrg SRBM_INT_STATUS = 0x0ea4, 75de2362d3Smrg RDERR_INT_STAT_bit = 1 << 0, 76de2362d3Smrg GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1, 77de2362d3Smrg SRBM_INT_ACK = 0x0ea8, 78de2362d3Smrg RDERR_INT_ACK_bit = 1 << 0, 79de2362d3Smrg GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1, 80de2362d3Smrg 81de2362d3Smrg R6XX_MC_VM_FB_LOCATION = 0x2180, 82de2362d3Smrg 83de2362d3Smrg VENDOR_DEVICE_ID = 0x4000, 84de2362d3Smrg 85de2362d3Smrg HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480, 86de2362d3Smrg 87de2362d3Smrg D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, 88de2362d3Smrg D1GRPH_PITCH = 0x6120, 89de2362d3Smrg D1GRPH_Y_END = 0x6138, 90de2362d3Smrg 91de2362d3Smrg GRBM_STATUS = 0x8010, 92de2362d3Smrg CMDFIFO_AVAIL_mask = 0x1f << 0, 93de2362d3Smrg CMDFIFO_AVAIL_shift = 0, 94de2362d3Smrg SRBM_RQ_PENDING_bit = 1 << 5, 95de2362d3Smrg CP_RQ_PENDING_bit = 1 << 6, 96de2362d3Smrg CF_RQ_PENDING_bit = 1 << 7, 97de2362d3Smrg PF_RQ_PENDING_bit = 1 << 8, 98de2362d3Smrg GRBM_EE_BUSY_bit = 1 << 10, 99de2362d3Smrg GRBM_STATUS__VC_BUSY_bit = 1 << 11, 100de2362d3Smrg DB03_CLEAN_bit = 1 << 12, 101de2362d3Smrg CB03_CLEAN_bit = 1 << 13, 102de2362d3Smrg VGT_BUSY_NO_DMA_bit = 1 << 16, 103de2362d3Smrg GRBM_STATUS__VGT_BUSY_bit = 1 << 17, 104de2362d3Smrg TA03_BUSY_bit = 1 << 18, 105de2362d3Smrg GRBM_STATUS__TC_BUSY_bit = 1 << 19, 106de2362d3Smrg SX_BUSY_bit = 1 << 20, 107de2362d3Smrg SH_BUSY_bit = 1 << 21, 108de2362d3Smrg SPI03_BUSY_bit = 1 << 22, 109de2362d3Smrg SMX_BUSY_bit = 1 << 23, 110de2362d3Smrg SC_BUSY_bit = 1 << 24, 111de2362d3Smrg PA_BUSY_bit = 1 << 25, 112de2362d3Smrg DB03_BUSY_bit = 1 << 26, 113de2362d3Smrg CR_BUSY_bit = 1 << 27, 114de2362d3Smrg CP_COHERENCY_BUSY_bit = 1 << 28, 115de2362d3Smrg GRBM_STATUS__CP_BUSY_bit = 1 << 29, 116de2362d3Smrg CB03_BUSY_bit = 1 << 30, 117de2362d3Smrg GUI_ACTIVE_bit = 1 << 31, 118de2362d3Smrg GRBM_STATUS2 = 0x8014, 119de2362d3Smrg CR_CLEAN_bit = 1 << 0, 120de2362d3Smrg SMX_CLEAN_bit = 1 << 1, 121de2362d3Smrg SPI0_BUSY_bit = 1 << 8, 122de2362d3Smrg SPI1_BUSY_bit = 1 << 9, 123de2362d3Smrg SPI2_BUSY_bit = 1 << 10, 124de2362d3Smrg SPI3_BUSY_bit = 1 << 11, 125de2362d3Smrg TA0_BUSY_bit = 1 << 12, 126de2362d3Smrg TA1_BUSY_bit = 1 << 13, 127de2362d3Smrg TA2_BUSY_bit = 1 << 14, 128de2362d3Smrg TA3_BUSY_bit = 1 << 15, 129de2362d3Smrg DB0_BUSY_bit = 1 << 16, 130de2362d3Smrg DB1_BUSY_bit = 1 << 17, 131de2362d3Smrg DB2_BUSY_bit = 1 << 18, 132de2362d3Smrg DB3_BUSY_bit = 1 << 19, 133de2362d3Smrg CB0_BUSY_bit = 1 << 20, 134de2362d3Smrg CB1_BUSY_bit = 1 << 21, 135de2362d3Smrg CB2_BUSY_bit = 1 << 22, 136de2362d3Smrg CB3_BUSY_bit = 1 << 23, 137de2362d3Smrg GRBM_SOFT_RESET = 0x8020, 138de2362d3Smrg SOFT_RESET_CP_bit = 1 << 0, 139de2362d3Smrg SOFT_RESET_CB_bit = 1 << 1, 140de2362d3Smrg SOFT_RESET_CR_bit = 1 << 2, 141de2362d3Smrg SOFT_RESET_DB_bit = 1 << 3, 142de2362d3Smrg SOFT_RESET_PA_bit = 1 << 5, 143de2362d3Smrg SOFT_RESET_SC_bit = 1 << 6, 144de2362d3Smrg SOFT_RESET_SMX_bit = 1 << 7, 145de2362d3Smrg SOFT_RESET_SPI_bit = 1 << 8, 146de2362d3Smrg SOFT_RESET_SH_bit = 1 << 9, 147de2362d3Smrg SOFT_RESET_SX_bit = 1 << 10, 148de2362d3Smrg SOFT_RESET_TC_bit = 1 << 11, 149de2362d3Smrg SOFT_RESET_TA_bit = 1 << 12, 150de2362d3Smrg SOFT_RESET_VC_bit = 1 << 13, 151de2362d3Smrg SOFT_RESET_VGT_bit = 1 << 14, 152de2362d3Smrg SOFT_RESET_GRBM_GCA_bit = 1 << 15, 153de2362d3Smrg 154de2362d3Smrg WAIT_UNTIL = 0x8040, 155de2362d3Smrg WAIT_CP_DMA_IDLE_bit = 1 << 8, 156de2362d3Smrg WAIT_CMDFIFO_bit = 1 << 10, 157de2362d3Smrg WAIT_2D_IDLE_bit = 1 << 14, 158de2362d3Smrg WAIT_3D_IDLE_bit = 1 << 15, 159de2362d3Smrg WAIT_2D_IDLECLEAN_bit = 1 << 16, 160de2362d3Smrg WAIT_3D_IDLECLEAN_bit = 1 << 17, 161de2362d3Smrg WAIT_EXTERN_SIG_bit = 1 << 19, 162de2362d3Smrg CMDFIFO_ENTRIES_mask = 0x1f << 20, 163de2362d3Smrg CMDFIFO_ENTRIES_shift = 20, 164de2362d3Smrg 165de2362d3Smrg GRBM_READ_ERROR = 0x8058, 166de2362d3Smrg/* READ_ADDRESS_mask = 0xffff << 2, */ 167de2362d3Smrg/* READ_ADDRESS_shift = 2, */ 168de2362d3Smrg READ_REQUESTER_SRBM_bit = 1 << 28, 169de2362d3Smrg READ_REQUESTER_CP_bit = 1 << 29, 170de2362d3Smrg READ_REQUESTER_WU_POLL_bit = 1 << 30, 171de2362d3Smrg/* READ_ERROR_bit = 1 << 31, */ 172de2362d3Smrg 173de2362d3Smrg SCRATCH_REG0 = 0x8500, 174de2362d3Smrg SCRATCH_REG1 = 0x8504, 175de2362d3Smrg SCRATCH_REG2 = 0x8508, 176de2362d3Smrg SCRATCH_REG3 = 0x850c, 177de2362d3Smrg SCRATCH_REG4 = 0x8510, 178de2362d3Smrg SCRATCH_REG5 = 0x8514, 179de2362d3Smrg SCRATCH_REG6 = 0x8518, 180de2362d3Smrg SCRATCH_REG7 = 0x851c, 181de2362d3Smrg SCRATCH_UMSK = 0x8540, 182de2362d3Smrg SCRATCH_ADDR = 0x8544, 183de2362d3Smrg 184de2362d3Smrg CP_COHER_CNTL = 0x85f0, 185de2362d3Smrg DEST_BASE_0_ENA_bit = 1 << 0, 186de2362d3Smrg DEST_BASE_1_ENA_bit = 1 << 1, 187de2362d3Smrg SO0_DEST_BASE_ENA_bit = 1 << 2, 188de2362d3Smrg SO1_DEST_BASE_ENA_bit = 1 << 3, 189de2362d3Smrg SO2_DEST_BASE_ENA_bit = 1 << 4, 190de2362d3Smrg SO3_DEST_BASE_ENA_bit = 1 << 5, 191de2362d3Smrg CB0_DEST_BASE_ENA_bit = 1 << 6, 192de2362d3Smrg CB1_DEST_BASE_ENA_bit = 1 << 7, 193de2362d3Smrg CB2_DEST_BASE_ENA_bit = 1 << 8, 194de2362d3Smrg CB3_DEST_BASE_ENA_bit = 1 << 9, 195de2362d3Smrg CB4_DEST_BASE_ENA_bit = 1 << 10, 196de2362d3Smrg CB5_DEST_BASE_ENA_bit = 1 << 11, 197de2362d3Smrg CB6_DEST_BASE_ENA_bit = 1 << 12, 198de2362d3Smrg CB7_DEST_BASE_ENA_bit = 1 << 13, 199de2362d3Smrg DB_DEST_BASE_ENA_bit = 1 << 14, 200de2362d3Smrg CR_DEST_BASE_ENA_bit = 1 << 15, 201de2362d3Smrg TC_ACTION_ENA_bit = 1 << 23, 202de2362d3Smrg VC_ACTION_ENA_bit = 1 << 24, 203de2362d3Smrg CB_ACTION_ENA_bit = 1 << 25, 204de2362d3Smrg DB_ACTION_ENA_bit = 1 << 26, 205de2362d3Smrg SH_ACTION_ENA_bit = 1 << 27, 206de2362d3Smrg SMX_ACTION_ENA_bit = 1 << 28, 207de2362d3Smrg CR0_ACTION_ENA_bit = 1 << 29, 208de2362d3Smrg CR1_ACTION_ENA_bit = 1 << 30, 209de2362d3Smrg CR2_ACTION_ENA_bit = 1 << 31, 210de2362d3Smrg CP_COHER_SIZE = 0x85f4, 211de2362d3Smrg CP_COHER_BASE = 0x85f8, 212de2362d3Smrg CP_COHER_STATUS = 0x85fc, 213de2362d3Smrg MATCHING_GFX_CNTX_mask = 0xff << 0, 214de2362d3Smrg MATCHING_GFX_CNTX_shift = 0, 215de2362d3Smrg MATCHING_CR_CNTX_mask = 0xffff << 8, 216de2362d3Smrg MATCHING_CR_CNTX_shift = 8, 217de2362d3Smrg STATUS_bit = 1 << 31, 218de2362d3Smrg 219de2362d3Smrg CP_STALLED_STAT1 = 0x8674, 220de2362d3Smrg RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0, 221de2362d3Smrg RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1, 222de2362d3Smrg RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2, 223de2362d3Smrg RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3, 224de2362d3Smrg RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4, 225de2362d3Smrg RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5, 226de2362d3Smrg RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6, 227de2362d3Smrg RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7, 228de2362d3Smrg RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8, 229de2362d3Smrg RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9, 230de2362d3Smrg MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16, 231de2362d3Smrg MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17, 232de2362d3Smrg MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18, 233de2362d3Smrg RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24, 234de2362d3Smrg RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25, 235de2362d3Smrg RCIU_STALLED_ON_ME_READ_bit = 1 << 26, 236de2362d3Smrg RCIU_STALLED_ON_DMA_READ_bit = 1 << 27, 237de2362d3Smrg RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28, 238de2362d3Smrg CP_STALLED_STAT2 = 0x8678, 239de2362d3Smrg PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0, 240de2362d3Smrg PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1, 241de2362d3Smrg PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2, 242de2362d3Smrg PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3, 243de2362d3Smrg MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4, 244de2362d3Smrg ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8, 245de2362d3Smrg ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9, 246de2362d3Smrg CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10, 247de2362d3Smrg GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11, 248de2362d3Smrg ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12, 249de2362d3Smrg ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13, 250de2362d3Smrg ME_WAITING_DATA_FROM_PFP_bit = 1 << 14, 251de2362d3Smrg ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15, 252de2362d3Smrg RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16, 253de2362d3Smrg RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17, 254de2362d3Smrg EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18, 255de2362d3Smrg EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19, 256de2362d3Smrg EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20, 257de2362d3Smrg EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21, 258de2362d3Smrg SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22, 259de2362d3Smrg SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23, 260de2362d3Smrg PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24, 261de2362d3Smrg SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30, 262de2362d3Smrg SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31, 263de2362d3Smrg CP_BUSY_STAT = 0x867c, 264de2362d3Smrg REG_BUS_FIFO_BUSY_bit = 1 << 0, 265de2362d3Smrg RING_FETCHING_DATA_bit = 1 << 1, 266de2362d3Smrg INDR1_FETCHING_DATA_bit = 1 << 2, 267de2362d3Smrg INDR2_FETCHING_DATA_bit = 1 << 3, 268de2362d3Smrg STATE_FETCHING_DATA_bit = 1 << 4, 269de2362d3Smrg PRED_FETCHING_DATA_bit = 1 << 5, 270de2362d3Smrg COHER_CNTR_NEQ_ZERO_bit = 1 << 6, 271de2362d3Smrg PFP_PARSING_PACKETS_bit = 1 << 7, 272de2362d3Smrg ME_PARSING_PACKETS_bit = 1 << 8, 273de2362d3Smrg RCIU_PFP_BUSY_bit = 1 << 9, 274de2362d3Smrg RCIU_ME_BUSY_bit = 1 << 10, 275de2362d3Smrg OUTSTANDING_READ_TAGS_bit = 1 << 11, 276de2362d3Smrg SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12, 277de2362d3Smrg SEM_FAILED_AND_HOLDING_bit = 1 << 13, 278de2362d3Smrg SEM_POLLING_FOR_PASS_bit = 1 << 14, 279de2362d3Smrg _3D_BUSY_bit = 1 << 15, 280de2362d3Smrg _2D_BUSY_bit = 1 << 16, 281de2362d3Smrg CP_STAT = 0x8680, 282de2362d3Smrg CSF_RING_BUSY_bit = 1 << 0, 283de2362d3Smrg CSF_WPTR_POLL_BUSY_bit = 1 << 1, 284de2362d3Smrg CSF_INDIRECT1_BUSY_bit = 1 << 2, 285de2362d3Smrg CSF_INDIRECT2_BUSY_bit = 1 << 3, 286de2362d3Smrg CSF_STATE_BUSY_bit = 1 << 4, 287de2362d3Smrg CSF_PREDICATE_BUSY_bit = 1 << 5, 288de2362d3Smrg CSF_BUSY_bit = 1 << 6, 289de2362d3Smrg MIU_RDREQ_BUSY_bit = 1 << 7, 290de2362d3Smrg MIU_WRREQ_BUSY_bit = 1 << 8, 291de2362d3Smrg ROQ_RING_BUSY_bit = 1 << 9, 292de2362d3Smrg ROQ_INDIRECT1_BUSY_bit = 1 << 10, 293de2362d3Smrg ROQ_INDIRECT2_BUSY_bit = 1 << 11, 294de2362d3Smrg ROQ_STATE_BUSY_bit = 1 << 12, 295de2362d3Smrg ROQ_PREDICATE_BUSY_bit = 1 << 13, 296de2362d3Smrg ROQ_ALIGN_BUSY_bit = 1 << 14, 297de2362d3Smrg PFP_BUSY_bit = 1 << 15, 298de2362d3Smrg MEQ_BUSY_bit = 1 << 16, 299de2362d3Smrg ME_BUSY_bit = 1 << 17, 300de2362d3Smrg QUERY_BUSY_bit = 1 << 18, 301de2362d3Smrg SEMAPHORE_BUSY_bit = 1 << 19, 302de2362d3Smrg INTERRUPT_BUSY_bit = 1 << 20, 303de2362d3Smrg SURFACE_SYNC_BUSY_bit = 1 << 21, 304de2362d3Smrg DMA_BUSY_bit = 1 << 22, 305de2362d3Smrg RCIU_BUSY_bit = 1 << 23, 306de2362d3Smrg CP_STAT__CP_BUSY_bit = 1 << 31, 307de2362d3Smrg 308de2362d3Smrg CP_ME_CNTL = 0x86d8, 309de2362d3Smrg ME_STATMUX_mask = 0xff << 0, 310de2362d3Smrg ME_STATMUX_shift = 0, 311de2362d3Smrg ME_HALT_bit = 1 << 28, 312de2362d3Smrg CP_ME_STATUS = 0x86dc, 313de2362d3Smrg 314de2362d3Smrg CP_RB_RPTR = 0x8700, 315de2362d3Smrg RB_RPTR_mask = 0xfffff << 0, 316de2362d3Smrg RB_RPTR_shift = 0, 317de2362d3Smrg CP_RB_WPTR_DELAY = 0x8704, 318de2362d3Smrg PRE_WRITE_TIMER_mask = 0xfffffff << 0, 319de2362d3Smrg PRE_WRITE_TIMER_shift = 0, 320de2362d3Smrg PRE_WRITE_LIMIT_mask = 0x0f << 28, 321de2362d3Smrg PRE_WRITE_LIMIT_shift = 28, 322de2362d3Smrg 323de2362d3Smrg CP_ROQ_RB_STAT = 0x8780, 324de2362d3Smrg ROQ_RPTR_PRIMARY_mask = 0x3ff << 0, 325de2362d3Smrg ROQ_RPTR_PRIMARY_shift = 0, 326de2362d3Smrg ROQ_WPTR_PRIMARY_mask = 0x3ff << 16, 327de2362d3Smrg ROQ_WPTR_PRIMARY_shift = 16, 328de2362d3Smrg CP_ROQ_IB1_STAT = 0x8784, 329de2362d3Smrg ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0, 330de2362d3Smrg ROQ_RPTR_INDIRECT1_shift = 0, 331de2362d3Smrg ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16, 332de2362d3Smrg ROQ_WPTR_INDIRECT1_shift = 16, 333de2362d3Smrg CP_ROQ_IB2_STAT = 0x8788, 334de2362d3Smrg ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0, 335de2362d3Smrg ROQ_RPTR_INDIRECT2_shift = 0, 336de2362d3Smrg ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16, 337de2362d3Smrg ROQ_WPTR_INDIRECT2_shift = 16, 338de2362d3Smrg 339de2362d3Smrg CP_MEQ_STAT = 0x8794, 340de2362d3Smrg MEQ_RPTR_mask = 0x3ff << 0, 341de2362d3Smrg MEQ_RPTR_shift = 0, 342de2362d3Smrg MEQ_WPTR_mask = 0x3ff << 16, 343de2362d3Smrg MEQ_WPTR_shift = 16, 344de2362d3Smrg 345de2362d3Smrg CC_GC_SHADER_PIPE_CONFIG = 0x8950, 346de2362d3Smrg INACTIVE_QD_PIPES_mask = 0xff << 8, 347de2362d3Smrg INACTIVE_QD_PIPES_shift = 8, 348de2362d3Smrg R6XX_MAX_QD_PIPES = 8, 349de2362d3Smrg INACTIVE_SIMDS_mask = 0xff << 16, 350de2362d3Smrg INACTIVE_SIMDS_shift = 16, 351de2362d3Smrg R6XX_MAX_SIMDS = 8, 352de2362d3Smrg GC_USER_SHADER_PIPE_CONFIG = 0x8954, 353de2362d3Smrg 354de2362d3Smrg VC_ENHANCE = 0x9714, 355de2362d3Smrg DB_DEBUG = 0x9830, 356de2362d3Smrg PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31, 357de2362d3Smrg 358de2362d3Smrg DB_WATERMARKS = 0x00009838, 359de2362d3Smrg DEPTH_FREE_mask = 0x1f << 0, 360de2362d3Smrg DEPTH_FREE_shift = 0, 361de2362d3Smrg DEPTH_FLUSH_mask = 0x3f << 5, 362de2362d3Smrg DEPTH_FLUSH_shift = 5, 363de2362d3Smrg FORCE_SUMMARIZE_mask = 0x0f << 11, 364de2362d3Smrg FORCE_SUMMARIZE_shift = 11, 365de2362d3Smrg DEPTH_PENDING_FREE_mask = 0x1f << 15, 366de2362d3Smrg DEPTH_PENDING_FREE_shift = 15, 367de2362d3Smrg DEPTH_CACHELINE_FREE_mask = 0x1f << 20, 368de2362d3Smrg DEPTH_CACHELINE_FREE_shift = 20, 369de2362d3Smrg EARLY_Z_PANIC_DISABLE_bit = 1 << 25, 370de2362d3Smrg LATE_Z_PANIC_DISABLE_bit = 1 << 26, 371de2362d3Smrg RE_Z_PANIC_DISABLE_bit = 1 << 27, 372de2362d3Smrg DB_EXTRA_DEBUG_mask = 0x0f << 28, 373de2362d3Smrg DB_EXTRA_DEBUG_shift = 28, 374de2362d3Smrg 375de2362d3Smrg CP_RB_BASE = 0xc100, 376de2362d3Smrg CP_RB_CNTL = 0xc104, 377de2362d3Smrg RB_BUFSZ_mask = 0x3f << 0, 378de2362d3Smrg CP_RB_WPTR = 0xc114, 379de2362d3Smrg RB_WPTR_mask = 0xfffff << 0, 380de2362d3Smrg RB_WPTR_shift = 0, 381de2362d3Smrg CP_RB_RPTR_WR = 0xc108, 382de2362d3Smrg RB_RPTR_WR_mask = 0xfffff << 0, 383de2362d3Smrg RB_RPTR_WR_shift = 0, 384de2362d3Smrg 385de2362d3Smrg CP_INT_STATUS = 0xc128, 386de2362d3Smrg DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0, 387de2362d3Smrg ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1, 388de2362d3Smrg SEM_SIGNAL_INT_STAT_bit = 1 << 18, 389de2362d3Smrg CNTX_BUSY_INT_STAT_bit = 1 << 19, 390de2362d3Smrg CNTX_EMPTY_INT_STAT_bit = 1 << 20, 391de2362d3Smrg WAITMEM_SEM_INT_STAT_bit = 1 << 21, 392de2362d3Smrg PRIV_INSTR_INT_STAT_bit = 1 << 22, 393de2362d3Smrg PRIV_REG_INT_STAT_bit = 1 << 23, 394de2362d3Smrg OPCODE_ERROR_INT_STAT_bit = 1 << 24, 395de2362d3Smrg SCRATCH_INT_STAT_bit = 1 << 25, 396de2362d3Smrg TIME_STAMP_INT_STAT_bit = 1 << 26, 397de2362d3Smrg RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27, 398de2362d3Smrg DMA_INT_STAT_bit = 1 << 28, 399de2362d3Smrg IB2_INT_STAT_bit = 1 << 29, 400de2362d3Smrg IB1_INT_STAT_bit = 1 << 30, 401de2362d3Smrg RB_INT_STAT_bit = 1 << 31, 402de2362d3Smrg 403de2362d3Smrg// SX_ALPHA_TEST_CONTROL = 0x00028410, 404de2362d3Smrg ALPHA_FUNC__REF_NEVER = 0, 405de2362d3Smrg ALPHA_FUNC__REF_ALWAYS = 7, 406de2362d3Smrg// DB_SHADER_CONTROL = 0x0002880c, 407de2362d3Smrg Z_ORDER__EARLY_Z_THEN_LATE_Z = 2, 408de2362d3Smrg// PA_SU_SC_MODE_CNTL = 0x00028814, 409de2362d3Smrg// POLY_MODE_mask = 0x03 << 3, 410de2362d3Smrg POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE, 411de2362d3Smrg// POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, 412de2362d3Smrg POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES, 413de2362d3Smrg PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20, 414de2362d3Smrg DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */ 415de2362d3Smrg// DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, 416de2362d3Smrg DB_ALPHA_TO_MASK = 0x00028d44, 417de2362d3Smrg ALPHA_TO_MASK_ENABLE = 1 << 0, 418de2362d3Smrg ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, 419de2362d3Smrg ALPHA_TO_MASK_OFFSET0_shift = 8, 420de2362d3Smrg ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10, 421de2362d3Smrg ALPHA_TO_MASK_OFFSET1_shift = 10, 422de2362d3Smrg ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12, 423de2362d3Smrg ALPHA_TO_MASK_OFFSET2_shift = 12, 424de2362d3Smrg ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14, 425de2362d3Smrg ALPHA_TO_MASK_OFFSET3_shift = 14, 426de2362d3Smrg 427de2362d3Smrg// SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, 428de2362d3Smrg// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, 429de2362d3Smrg FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, 430de2362d3Smrg FMT_16=5, FMT_16_FLOAT, FMT_8_8, 431de2362d3Smrg FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, 432de2362d3Smrg FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, 433de2362d3Smrg FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, 434de2362d3Smrg FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, 435de2362d3Smrg FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, 436de2362d3Smrg FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, 437de2362d3Smrg FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, 438de2362d3Smrg FMT_1 = 37, FMT_GB_GR=39, 439de2362d3Smrg FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, 440de2362d3Smrg FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, 441de2362d3Smrg FMT_32_32_32_FLOAT=48, 442de2362d3Smrg 443de2362d3Smrg// High level register file lengths 444de2362d3Smrg SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */ 445de2362d3Smrg SQ_ALU_CONSTANT_ps_num = 256, 446de2362d3Smrg SQ_ALU_CONSTANT_vs_num = 256, 447de2362d3Smrg SQ_ALU_CONSTANT_all_num = 512, 448de2362d3Smrg SQ_ALU_CONSTANT_offset = 16, 449de2362d3Smrg SQ_ALU_CONSTANT_ps = 0, 450de2362d3Smrg SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num, 451de2362d3Smrg SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ 452de2362d3Smrg SQ_TEX_RESOURCE_ps_num = 160, 453de2362d3Smrg SQ_TEX_RESOURCE_vs_num = 160, 454de2362d3Smrg SQ_TEX_RESOURCE_fs_num = 16, 455de2362d3Smrg SQ_TEX_RESOURCE_gs_num = 160, 456de2362d3Smrg SQ_TEX_RESOURCE_all_num = 496, 457de2362d3Smrg SQ_TEX_RESOURCE_offset = 28, 458de2362d3Smrg SQ_TEX_RESOURCE_ps = 0, 459de2362d3Smrg SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num, 460de2362d3Smrg SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num, 461de2362d3Smrg SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num, 462de2362d3Smrg SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ 463de2362d3Smrg SQ_VTX_RESOURCE_ps_num = 160, 464de2362d3Smrg SQ_VTX_RESOURCE_vs_num = 160, 465de2362d3Smrg SQ_VTX_RESOURCE_fs_num = 16, 466de2362d3Smrg SQ_VTX_RESOURCE_gs_num = 160, 467de2362d3Smrg SQ_VTX_RESOURCE_all_num = 496, 468de2362d3Smrg SQ_VTX_RESOURCE_offset = 28, 469de2362d3Smrg SQ_VTX_RESOURCE_ps = 0, 470de2362d3Smrg SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num, 471de2362d3Smrg SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num, 472de2362d3Smrg SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num, 473de2362d3Smrg SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */ 474de2362d3Smrg SQ_TEX_SAMPLER_WORD_ps_num = 18, 475de2362d3Smrg SQ_TEX_SAMPLER_WORD_vs_num = 18, 476de2362d3Smrg SQ_TEX_SAMPLER_WORD_gs_num = 18, 477de2362d3Smrg SQ_TEX_SAMPLER_WORD_all_num = 54, 478de2362d3Smrg SQ_TEX_SAMPLER_WORD_offset = 12, 479de2362d3Smrg SQ_TEX_SAMPLER_WORD_ps = 0, 480de2362d3Smrg SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, 481de2362d3Smrg SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, 482de2362d3Smrg SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */ 483de2362d3Smrg SQ_LOOP_CONST_ps_num = 32, 484de2362d3Smrg SQ_LOOP_CONST_vs_num = 32, 485de2362d3Smrg SQ_LOOP_CONST_gs_num = 32, 486de2362d3Smrg SQ_LOOP_CONST_all_num = 96, 487de2362d3Smrg SQ_LOOP_CONST_offset = 4, 488de2362d3Smrg SQ_LOOP_CONST_ps = 0, 489de2362d3Smrg SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, 490de2362d3Smrg SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, 491de2362d3Smrg SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */ 492de2362d3Smrg SQ_BOOL_CONST_ps_num = 1, 493de2362d3Smrg SQ_BOOL_CONST_vs_num = 1, 494de2362d3Smrg SQ_BOOL_CONST_gs_num = 1, 495de2362d3Smrg SQ_BOOL_CONST_all_num = 3, 496de2362d3Smrg SQ_BOOL_CONST_offset = 4, 497de2362d3Smrg SQ_BOOL_CONST_ps = 0, 498de2362d3Smrg SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, 499de2362d3Smrg SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, 500de2362d3Smrg}; 501de2362d3Smrg 502de2362d3Smrg 503de2362d3Smrg#endif 504