1de2362d3Smrg/*
2de2362d3Smrg * Copyright 2005 Eric Anholt
3de2362d3Smrg * Copyright 2005 Benjamin Herrenschmidt
4de2362d3Smrg * Copyright 2008 Advanced Micro Devices, Inc.
5de2362d3Smrg * All Rights Reserved.
6de2362d3Smrg *
7de2362d3Smrg * Permission is hereby granted, free of charge, to any person obtaining a
8de2362d3Smrg * copy of this software and associated documentation files (the "Software"),
9de2362d3Smrg * to deal in the Software without restriction, including without limitation
10de2362d3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11de2362d3Smrg * and/or sell copies of the Software, and to permit persons to whom the
12de2362d3Smrg * Software is furnished to do so, subject to the following conditions:
13de2362d3Smrg *
14de2362d3Smrg * The above copyright notice and this permission notice (including the next
15de2362d3Smrg * paragraph) shall be included in all copies or substantial portions of the
16de2362d3Smrg * Software.
17de2362d3Smrg *
18de2362d3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19de2362d3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20de2362d3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
21de2362d3Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22de2362d3Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23de2362d3Smrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24de2362d3Smrg * SOFTWARE.
25de2362d3Smrg *
26de2362d3Smrg * Authors:
27de2362d3Smrg *    Eric Anholt <anholt@FreeBSD.org>
28de2362d3Smrg *    Zack Rusin <zrusin@trolltech.com>
29de2362d3Smrg *    Benjamin Herrenschmidt <benh@kernel.crashing.org>
30de2362d3Smrg *    Alex Deucher <alexander.deucher@amd.com>
31de2362d3Smrg *    Matthias Hopf <mhopf@suse.de>
32de2362d3Smrg */
33de2362d3Smrg#ifndef RADEON_EXA_SHARED_H
34de2362d3Smrg
35de2362d3Smrg#define RADEON_EXA_SHARED_H
36de2362d3Smrg
37de2362d3Smrgextern PixmapPtr RADEONGetDrawablePixmap(DrawablePtr pDrawable);
38de2362d3Smrg
39de2362d3Smrgextern void RADEONVlineHelperClear(ScrnInfoPtr pScrn);
40de2362d3Smrgextern void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
41de2362d3Smrgextern Bool RADEONValidPM(uint32_t pm, int bpp);
42de2362d3Smrgextern Bool RADEONCheckBPP(int bpp);
43de2362d3Smrgextern PixmapPtr RADEONSolidPixmap(ScreenPtr pScreen, uint32_t solid);
44de2362d3Smrg
45de2362d3Smrg#define RADEON_TRACE_FALL 0
46de2362d3Smrg#define RADEON_TRACE_DRAW 0
47de2362d3Smrg
48de2362d3Smrg#if RADEON_TRACE_FALL
49de2362d3Smrg#define RADEON_FALLBACK(x)     		\
50de2362d3Smrgdo {					\
51de2362d3Smrg	ErrorF("%s: ", __FUNCTION__);	\
52de2362d3Smrg	ErrorF x;			\
53de2362d3Smrg	return FALSE;			\
54de2362d3Smrg} while (0)
55de2362d3Smrg#else
56de2362d3Smrg#define RADEON_FALLBACK(x) return FALSE
57de2362d3Smrg#endif
58de2362d3Smrg
59de2362d3Smrg#if RADEON_TRACE_DRAW
60de2362d3Smrg#define TRACE do { ErrorF("TRACE: %s\n", __FUNCTION__); } while(0)
61de2362d3Smrg#else
62de2362d3Smrg#define TRACE
63de2362d3Smrg#endif
64de2362d3Smrg
65de2362d3Smrgstatic inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain)
66de2362d3Smrg{
67de2362d3Smrg    struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);
68de2362d3Smrg
6939413783Smrg    radeon_cs_space_add_persistent_bo(cs, driver_priv->bo->bo.radeon,
7039413783Smrg				      read_domains, write_domain);
71de2362d3Smrg}
72de2362d3Smrg
73de2362d3Smrgextern void radeon_ib_discard(ScrnInfoPtr pScrn);
74de2362d3Smrg
75de2362d3Smrgextern int radeon_cp_start(ScrnInfoPtr pScrn);
76de2362d3Smrgextern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size);
77de2362d3Smrgextern void radeon_vbo_done_composite(PixmapPtr pDst);
78de2362d3Smrg
79de2362d3Smrg#endif
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