1de2362d3Smrg/*
2de2362d3Smrg * Copyright © 2011 Intel Corporation.
3de2362d3Smrg *             2012 Advanced Micro Devices, Inc.
4de2362d3Smrg *
5de2362d3Smrg * Permission is hereby granted, free of charge, to any person
6de2362d3Smrg * obtaining a copy of this software and associated documentation
7de2362d3Smrg * files (the "Software"), to deal in the Software without
8de2362d3Smrg * restriction, including without limitation the rights to use, copy,
9de2362d3Smrg * modify, merge, publish, distribute, sublicense, and/or sell copies
10de2362d3Smrg * of the Software, and to permit persons to whom the Software is
11de2362d3Smrg * furnished to do so, subject to the following conditions:
12de2362d3Smrg *
13de2362d3Smrg * The above copyright notice and this permission notice (including
14de2362d3Smrg * the next paragraph) shall be included in all copies or substantial
15de2362d3Smrg * portions of the Software.
16de2362d3Smrg *
17de2362d3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18de2362d3Smrg * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19de2362d3Smrg * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20de2362d3Smrg * NONINFRINGEMENT.  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
21de2362d3Smrg * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
22de2362d3Smrg * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23de2362d3Smrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24de2362d3Smrg * DEALINGS IN THE SOFTWARE.
25de2362d3Smrg */
26de2362d3Smrg
27de2362d3Smrg#ifndef RADEON_GLAMOR_H
28de2362d3Smrg#define RADEON_GLAMOR_H
29de2362d3Smrg
30de2362d3Smrg#include "xf86xv.h"
310d16fef4Smrg
320d16fef4Smrgstruct radeon_pixmap;
330d16fef4Smrg
34de2362d3Smrg#ifdef USE_GLAMOR
35de2362d3Smrg
3639413783Smrg#ifndef HAVE_GLAMOR_FINISH
3739413783Smrg#include <GL/gl.h>
3839413783Smrg#endif
3939413783Smrg
4039413783Smrg#include <gbm.h>
4139413783Smrg
420d16fef4Smrg#define GLAMOR_FOR_XORG  1
430d16fef4Smrg#include <glamor.h>
440d16fef4Smrg
45de2362d3Smrg#include "radeon_surface.h"
46de2362d3Smrg
470d16fef4Smrg#define RADEON_CREATE_PIXMAP_SHARED(usage) \
480d16fef4Smrg	(((usage) & ~RADEON_CREATE_PIXMAP_TILING_FLAGS) == RADEON_CREATE_PIXMAP_DRI2 || \
490d16fef4Smrg	 (usage) == CREATE_PIXMAP_USAGE_SHARED)
500d16fef4Smrg
510d16fef4Smrg#ifndef GLAMOR_NO_DRI3
520d16fef4Smrg#define GLAMOR_NO_DRI3 0
530d16fef4Smrg#define glamor_fd_from_pixmap glamor_dri3_fd_from_pixmap
540d16fef4Smrg#define glamor_pixmap_from_fd glamor_egl_dri3_pixmap_from_fd
550d16fef4Smrg#endif
560d16fef4Smrg
570d16fef4Smrg#ifndef GLAMOR_INVERTED_Y_AXIS
580d16fef4Smrg#define GLAMOR_INVERTED_Y_AXIS 0
590d16fef4Smrg#endif
600d16fef4Smrg#ifndef GLAMOR_USE_SCREEN
610d16fef4Smrg#define GLAMOR_USE_SCREEN 0
620d16fef4Smrg#endif
630d16fef4Smrg#ifndef GLAMOR_USE_PICTURE_SCREEN
640d16fef4Smrg#define GLAMOR_USE_PICTURE_SCREEN 0
650d16fef4Smrg#endif
660d16fef4Smrg
67de2362d3SmrgBool radeon_glamor_pre_init(ScrnInfoPtr scrn);
68de2362d3SmrgBool radeon_glamor_init(ScreenPtr screen);
690d16fef4Smrgvoid radeon_glamor_fini(ScreenPtr screen);
700d16fef4Smrgvoid radeon_glamor_screen_init(ScreenPtr screen);
71de2362d3SmrgBool radeon_glamor_create_screen_resources(ScreenPtr screen);
72de2362d3Smrgvoid radeon_glamor_free_screen(int scrnIndex, int flags);
73de2362d3Smrg
7439413783SmrgBool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo);
75de2362d3Smrgvoid radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst);
767314432eSmrgPixmapPtr radeon_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap);
77de2362d3Smrg
78de2362d3SmrgXF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt);
79de2362d3Smrg
8039413783Smrgstatic inline void
8139413783Smrgradeon_glamor_finish(ScrnInfoPtr scrn)
8239413783Smrg{
8339413783Smrg	RADEONInfoPtr info = RADEONPTR(scrn);
8439413783Smrg
8539413783Smrg#if HAVE_GLAMOR_FINISH
8639413783Smrg	glamor_finish(scrn->pScreen);
8739413783Smrg#else
8839413783Smrg	glamor_block_handler(scrn->pScreen);
8939413783Smrg	glFinish();
9039413783Smrg#endif
9139413783Smrg
9239413783Smrg	info->gpu_flushed++;
9339413783Smrg}
9439413783Smrg
95de2362d3Smrg#else
96de2362d3Smrg
97de2362d3Smrgstatic inline Bool radeon_glamor_pre_init(ScrnInfoPtr scrn) { return FALSE; }
98de2362d3Smrgstatic inline Bool radeon_glamor_init(ScreenPtr screen) { return FALSE; }
990d16fef4Smrgstatic inline void radeon_glamor_fini(ScreenPtr screen) { }
100de2362d3Smrgstatic inline Bool radeon_glamor_create_screen_resources(ScreenPtr screen) { return FALSE; }
101de2362d3Smrgstatic inline void radeon_glamor_free_screen(int scrnIndex, int flags) { }
102de2362d3Smrg
10339413783Smrgstatic inline Bool radeon_glamor_create_textured_pixmap(PixmapPtr pixmap, struct radeon_buffer *bo) { return TRUE; }
104de2362d3Smrg
105de2362d3Smrgstatic inline void radeon_glamor_exchange_buffers(PixmapPtr src, PixmapPtr dst) {}
1067314432eSmrgstatic inline PixmapPtr radeon_glamor_set_pixmap_bo(DrawablePtr drawable, PixmapPtr pixmap) { return pixmap; }
107de2362d3Smrg
108de2362d3Smrgstatic inline struct radeon_pixmap *radeon_get_pixmap_private(PixmapPtr pixmap) { return NULL; }
109de2362d3Smrg
110de2362d3Smrgstatic inline XF86VideoAdaptorPtr radeon_glamor_xv_init(ScreenPtr pScreen, int num_adapt) { return NULL; }
11139413783Smrg
11239413783Smrgstatic inline void radeon_glamor_finish(ScrnInfoPtr pScrn) { }
11339413783Smrg
114de2362d3Smrg#endif
115de2362d3Smrg
116de2362d3Smrg#endif /* RADEON_GLAMOR_H */
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