atombios_output.c revision b13dfe66
1/* 2 * Copyright © 2007 Red Hat, Inc. 3 * Copyright 2007 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 * 24 * Authors: 25 * Dave Airlie <airlied@redhat.com> 26 * Alex Deucher <alexdeucher@gmail.com> 27 * 28 */ 29 30/* 31 * avivo output handling functions. 32 */ 33#ifdef HAVE_CONFIG_H 34#include "config.h" 35#endif 36/* DPMS */ 37#ifdef HAVE_XEXTPROTO_71 38#include <X11/extensions/dpmsconst.h> 39#else 40#define DPMS_SERVER 41#include <X11/extensions/dpms.h> 42#endif 43 44#include <unistd.h> 45 46#include "radeon.h" 47#include "radeon_reg.h" 48#include "radeon_macros.h" 49#include "radeon_atombios.h" 50 51#include "ati_pciids_gen.h" 52 53const char *device_name[12] = { 54 "CRT1", 55 "LCD1", 56 "TV1", 57 "DFP1", 58 "CRT2", 59 "LCD2", 60 "TV2", 61 "DFP2", 62 "CV", 63 "DFP3", 64 "DFP4", 65 "DFP5", 66}; 67 68#define AUX_NATIVE_WRITE 0x8 69#define AUX_NATIVE_READ 0x9 70 71#define AUX_I2C_WRITE 0x0 72#define AUX_I2C_READ 0x1 73#define AUX_I2C_STATUS 0x2 74#define AUX_I2C_MOT 0x4 75 76#define DP_DPCD_REV 0x0 77#define DP_MAX_LINK_RATE 0x1 78#define DP_MAX_LANE_COUNT 0x2 79#define DP_MAX_DOWNSPREAD 0x3 80#define DP_NORP 0x4 81#define DP_DOWNSTREAMPORT_PRESENT 0x5 82#define DP_MAIN_LINK_CHANNEL_CONFIG 0x6 83#define DP_DP11_DOWNSTREAM_PORT_COUNT 0x7 84 85/* from intel i830_dp.h */ 86#define DP_LINK_BW_SET 0x100 87//# define DP_LINK_BW_1_62 0x06 88//# define DP_LINK_BW_2_7 0x0a 89#define DP_LANE_COUNT_SET 0x101 90# define DP_LANE_COUNT_MASK 0x0f 91# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 92 93#define DP_TRAINING_PATTERN_SET 0x102 94 95# define DP_TRAINING_PATTERN_DISABLE 0 96# define DP_TRAINING_PATTERN_1 1 97# define DP_TRAINING_PATTERN_2 2 98# define DP_TRAINING_PATTERN_MASK 0x3 99 100# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) 101# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) 102# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) 103# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) 104# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) 105# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 106# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 107 108# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 109# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 110# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 111# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 112 113#define DP_TRAINING_LANE0_SET 0x103 114#define DP_TRAINING_LANE1_SET 0x104 115#define DP_TRAINING_LANE2_SET 0x105 116#define DP_TRAINING_LANE3_SET 0x106 117# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 118# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 119# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 120# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) 121# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) 122# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) 123# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) 124 125# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 126# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) 127# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) 128# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) 129# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) 130 131# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 132# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 133#define DP_DOWNSPREAD_CTRL 0x107 134# define DP_SPREAD_AMP_0_5 (1 << 4) 135 136#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 137# define DP_SET_ANSI_8B10B (1 << 0) 138 139#define DP_LANE0_1_STATUS 0x202 140#define DP_LANE2_3_STATUS 0x203 141 142# define DP_LANE_CR_DONE (1 << 0) 143# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 144# define DP_LANE_SYMBOL_LOCKED (1 << 2) 145 146#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 147#define DP_INTERLANE_ALIGN_DONE (1 << 0) 148#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 149#define DP_LINK_STATUS_UPDATED (1 << 7) 150 151#define DP_SINK_STATUS 0x205 152 153#define DP_RECEIVE_PORT_0_STATUS (1 << 0) 154#define DP_RECEIVE_PORT_1_STATUS (1 << 1) 155 156#define DP_ADJUST_REQUEST_LANE0_1 0x206 157#define DP_ADJUST_REQUEST_LANE2_3 0x207 158 159#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 160#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 161#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 162#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 163#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 164#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 165#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 166#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 167 168#define DP_LINK_STATUS_SIZE 6 169#define DP_LINK_CONFIGURATION_SIZE 9 170 171#define DP_SET_POWER_D0 0x1 172#define DP_SET_POWER_D3 0x2 173 174static void do_displayport_link_train(xf86OutputPtr output); 175 176static int 177atombios_output_dac_setup(xf86OutputPtr output, int action) 178{ 179 RADEONOutputPrivatePtr radeon_output = output->driver_private; 180 RADEONInfoPtr info = RADEONPTR(output->scrn); 181 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 182 radeon_tvout_ptr tvout = &radeon_output->tvout; 183 DAC_ENCODER_CONTROL_PS_ALLOCATION disp_data; 184 AtomBiosArgRec data; 185 unsigned char *space; 186 int index = 0, num = 0; 187 int clock = radeon_output->pixel_clock; 188 189 if (radeon_encoder == NULL) 190 return ATOM_NOT_IMPLEMENTED; 191 192 memset(&disp_data,0, sizeof(disp_data)); 193 194 switch (radeon_encoder->encoder_id) { 195 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 196 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 197 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 198 num = 1; 199 break; 200 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 201 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 202 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 203 num = 2; 204 break; 205 } 206 207 disp_data.ucAction =action; 208 209 if (radeon_output->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 210 disp_data.ucDacStandard = ATOM_DAC1_PS2; 211 else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) 212 disp_data.ucDacStandard = ATOM_DAC1_CV; 213 else { 214 switch (tvout->tvStd) { 215 case TV_STD_PAL: 216 case TV_STD_PAL_M: 217 case TV_STD_SCART_PAL: 218 case TV_STD_SECAM: 219 case TV_STD_PAL_CN: 220 disp_data.ucDacStandard = ATOM_DAC1_PAL; 221 break; 222 case TV_STD_NTSC: 223 case TV_STD_NTSC_J: 224 case TV_STD_PAL_60: 225 default: 226 disp_data.ucDacStandard = ATOM_DAC1_NTSC; 227 break; 228 } 229 } 230 disp_data.usPixelClock = cpu_to_le16(clock / 10); 231 232 data.exec.index = index; 233 data.exec.dataSpace = (void *)&space; 234 data.exec.pspace = &disp_data; 235 236 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 237 ErrorF("Output DAC%d setup success\n", num); 238 return ATOM_SUCCESS; 239 } 240 241 ErrorF("Output DAC%d setup failed\n", num); 242 return ATOM_NOT_IMPLEMENTED; 243 244} 245 246static int 247atombios_output_tv_setup(xf86OutputPtr output, int action) 248{ 249 RADEONOutputPrivatePtr radeon_output = output->driver_private; 250 radeon_tvout_ptr tvout = &radeon_output->tvout; 251 RADEONInfoPtr info = RADEONPTR(output->scrn); 252 TV_ENCODER_CONTROL_PS_ALLOCATION disp_data; 253 AtomBiosArgRec data; 254 unsigned char *space; 255 int clock = radeon_output->pixel_clock; 256 257 memset(&disp_data,0, sizeof(disp_data)); 258 259 disp_data.sTVEncoder.ucAction = action; 260 261 if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) 262 disp_data.sTVEncoder.ucTvStandard = ATOM_TV_CV; 263 else { 264 switch (tvout->tvStd) { 265 case TV_STD_NTSC: 266 disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 267 break; 268 case TV_STD_PAL: 269 disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 270 break; 271 case TV_STD_PAL_M: 272 disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 273 break; 274 case TV_STD_PAL_60: 275 disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 276 break; 277 case TV_STD_NTSC_J: 278 disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 279 break; 280 case TV_STD_SCART_PAL: 281 disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 282 break; 283 case TV_STD_SECAM: 284 disp_data.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 285 break; 286 case TV_STD_PAL_CN: 287 disp_data.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 288 break; 289 default: 290 disp_data.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 291 break; 292 } 293 } 294 295 disp_data.sTVEncoder.usPixelClock = cpu_to_le16(clock / 10); 296 data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 297 data.exec.dataSpace = (void *)&space; 298 data.exec.pspace = &disp_data; 299 300 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 301 ErrorF("Output TV setup success\n"); 302 return ATOM_SUCCESS; 303 } 304 305 ErrorF("Output TV setup failed\n"); 306 return ATOM_NOT_IMPLEMENTED; 307 308} 309 310int 311atombios_external_tmds_setup(xf86OutputPtr output, int action) 312{ 313 RADEONOutputPrivatePtr radeon_output = output->driver_private; 314 ScrnInfoPtr pScrn = output->scrn; 315 RADEONInfoPtr info = RADEONPTR(pScrn); 316 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION disp_data; 317 AtomBiosArgRec data; 318 unsigned char *space; 319 int clock = radeon_output->pixel_clock; 320 321 memset(&disp_data,0, sizeof(disp_data)); 322 323 disp_data.sXTmdsEncoder.ucEnable = action; 324 325 if (clock > 165000) 326 disp_data.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; 327 328 if (pScrn->rgbBits == 8) 329 disp_data.sXTmdsEncoder.ucMisc |= (1 << 1); 330 331 data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 332 data.exec.dataSpace = (void *)&space; 333 data.exec.pspace = &disp_data; 334 335 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 336 ErrorF("External TMDS setup success\n"); 337 return ATOM_SUCCESS; 338 } 339 340 ErrorF("External TMDS setup failed\n"); 341 return ATOM_NOT_IMPLEMENTED; 342} 343 344static int 345atombios_output_ddia_setup(xf86OutputPtr output, int action) 346{ 347 RADEONOutputPrivatePtr radeon_output = output->driver_private; 348 RADEONInfoPtr info = RADEONPTR(output->scrn); 349 DVO_ENCODER_CONTROL_PS_ALLOCATION disp_data; 350 AtomBiosArgRec data; 351 unsigned char *space; 352 int clock = radeon_output->pixel_clock; 353 354 memset(&disp_data,0, sizeof(disp_data)); 355 356 disp_data.sDVOEncoder.ucAction = action; 357 disp_data.sDVOEncoder.usPixelClock = cpu_to_le16(clock / 10); 358 359 if (clock > 165000) 360 disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; 361 362 data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 363 data.exec.dataSpace = (void *)&space; 364 data.exec.pspace = &disp_data; 365 366 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 367 ErrorF("DDIA setup success\n"); 368 return ATOM_SUCCESS; 369 } 370 371 ErrorF("DDIA setup failed\n"); 372 return ATOM_NOT_IMPLEMENTED; 373} 374 375static int 376atombios_output_digital_setup(xf86OutputPtr output, int action) 377{ 378 RADEONOutputPrivatePtr radeon_output = output->driver_private; 379 ScrnInfoPtr pScrn = output->scrn; 380 RADEONInfoPtr info = RADEONPTR(pScrn); 381 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 382 LVDS_ENCODER_CONTROL_PS_ALLOCATION disp_data; 383 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 disp_data2; 384 AtomBiosArgRec data; 385 unsigned char *space; 386 int index = 0; 387 int major, minor; 388 int lvds_misc = 0; 389 int clock = radeon_output->pixel_clock; 390 391 if (radeon_encoder == NULL) 392 return ATOM_NOT_IMPLEMENTED; 393 394 if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 395 radeon_lvds_ptr lvds = (radeon_lvds_ptr)radeon_encoder->dev_priv; 396 if (lvds == NULL) 397 return ATOM_NOT_IMPLEMENTED; 398 lvds_misc = lvds->lvds_misc; 399 } 400 401 memset(&disp_data,0, sizeof(disp_data)); 402 memset(&disp_data2,0, sizeof(disp_data2)); 403 404 switch (radeon_encoder->encoder_id) { 405 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 406 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 407 break; 408 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 409 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 410 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 411 break; 412 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 413 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 414 if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 415 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 416 else 417 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 418 break; 419 } 420 421 atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); 422 423 /*ErrorF("table is %d %d\n", major, minor);*/ 424 switch (major) { 425 case 0: 426 case 1: 427 case 2: 428 switch (minor) { 429 case 1: 430 disp_data.ucMisc = 0; 431 disp_data.ucAction = action; 432 if ((radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) || 433 (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_B)) 434 disp_data.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 435 disp_data.usPixelClock = cpu_to_le16(clock / 10); 436 if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 437 if (lvds_misc & (1 << 0)) 438 disp_data.ucMisc |= PANEL_ENCODER_MISC_DUAL; 439 if (lvds_misc & (1 << 1)) 440 disp_data.ucMisc |= (1 << 1); 441 } else { 442 if (radeon_output->linkb) 443 disp_data.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 444 if (clock > 165000) 445 disp_data.ucMisc |= PANEL_ENCODER_MISC_DUAL; 446 if (pScrn->rgbBits == 8) 447 disp_data.ucMisc |= (1 << 1); 448 } 449 data.exec.pspace = &disp_data; 450 break; 451 case 2: 452 case 3: 453 disp_data2.ucMisc = 0; 454 disp_data2.ucAction = action; 455 if (minor == 3) { 456 if (radeon_output->coherent_mode) { 457 disp_data2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 458 xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "Coherent Mode enabled\n"); 459 } 460 } 461 if ((radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_A) || 462 (radeon_output->ConnectorType == CONNECTOR_HDMI_TYPE_B)) 463 disp_data2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 464 disp_data2.usPixelClock = cpu_to_le16(clock / 10); 465 disp_data2.ucTruncate = 0; 466 disp_data2.ucSpatial = 0; 467 disp_data2.ucTemporal = 0; 468 disp_data2.ucFRC = 0; 469 if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 470 if (lvds_misc & (1 << 0)) 471 disp_data2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 472 if (lvds_misc & (1 << 5)) { 473 disp_data2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 474 if (lvds_misc & (1 << 1)) 475 disp_data2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 476 } 477 if (lvds_misc & (1 << 6)) { 478 disp_data2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 479 if (lvds_misc & (1 << 1)) 480 disp_data2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 481 if (((lvds_misc >> 2) & 0x3) == 2) 482 disp_data2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 483 } 484 } else { 485 if (radeon_output->linkb) 486 disp_data2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 487 if (clock > 165000) 488 disp_data2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 489 } 490 data.exec.pspace = &disp_data2; 491 break; 492 default: 493 ErrorF("Unknown table version\n"); 494 exit(-1); 495 } 496 break; 497 default: 498 ErrorF("Unknown table version\n"); 499 exit(-1); 500 } 501 502 data.exec.index = index; 503 data.exec.dataSpace = (void *)&space; 504 505 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 506 ErrorF("Output digital setup success\n"); 507 return ATOM_SUCCESS; 508 } 509 510 ErrorF("Output digital setup failed\n"); 511 return ATOM_NOT_IMPLEMENTED; 512} 513 514static int 515atombios_maybe_hdmi_mode(xf86OutputPtr output) 516{ 517#ifndef EDID_COMPLETE_RAWDATA 518 /* there's no getting this right unless we have complete EDID */ 519 return ATOM_ENCODER_MODE_DVI; 520#else 521 if (output && xf86MonitorIsHDMI(output->MonInfo)) 522 return ATOM_ENCODER_MODE_HDMI; 523 524 return ATOM_ENCODER_MODE_DVI; 525#endif 526} 527 528int 529atombios_get_encoder_mode(xf86OutputPtr output) 530{ 531 ScrnInfoPtr pScrn = output->scrn; 532 RADEONInfoPtr info = RADEONPTR(pScrn); 533 RADEONOutputPrivatePtr radeon_output = output->driver_private; 534 535 /* DVI should really be atombios_maybe_hdmi_mode() as well */ 536 switch (radeon_output->ConnectorType) { 537 case CONNECTOR_DVI_I: 538 if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) 539 return ATOM_ENCODER_MODE_DVI; 540 else 541 return ATOM_ENCODER_MODE_CRT; 542 break; 543 case CONNECTOR_DVI_D: 544 default: 545 return ATOM_ENCODER_MODE_DVI; 546 break; 547 case CONNECTOR_HDMI_TYPE_A: 548 case CONNECTOR_HDMI_TYPE_B: 549 if (IS_DCE4_VARIANT) 550 return ATOM_ENCODER_MODE_DVI; 551 else 552 return atombios_maybe_hdmi_mode(output); 553 break; 554 case CONNECTOR_LVDS: 555 return ATOM_ENCODER_MODE_LVDS; 556 break; 557 case CONNECTOR_DISPLAY_PORT: 558 case CONNECTOR_EDP: 559 if (radeon_output->MonType == MT_DP) 560 return ATOM_ENCODER_MODE_DP; 561 else { 562 if (IS_DCE4_VARIANT) 563 return ATOM_ENCODER_MODE_DVI; 564 else 565 return atombios_maybe_hdmi_mode(output); 566 } 567 break; 568 case CONNECTOR_DVI_A: 569 case CONNECTOR_VGA: 570 case CONNECTOR_STV: 571 case CONNECTOR_CTV: 572 case CONNECTOR_DIN: 573 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) 574 return ATOM_ENCODER_MODE_TV; 575 else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) 576 return ATOM_ENCODER_MODE_CV; 577 else 578 return ATOM_ENCODER_MODE_CRT; 579 break; 580 } 581 582} 583 584static const int dp_clocks[] = { 585 5400, // 1 lane, 1.62 Ghz 586 9000, // 1 lane, 2.70 Ghz 587 10800, // 2 lane, 1.62 Ghz 588 18000, // 2 lane, 2.70 Ghz 589 21600, // 4 lane, 1.62 Ghz 590 36000, // 4 lane, 2.70 Ghz 591}; 592static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int); 593 594# define DP_LINK_BW_1_62 0x06 595# define DP_LINK_BW_2_7 0x0a 596static int radeon_dp_max_lane_count(xf86OutputPtr output); 597 598static int 599dp_lanes_for_mode_clock(xf86OutputPtr output, int mode_clock) 600{ 601 RADEONOutputPrivatePtr radeon_output = output->driver_private; 602 int i; 603 int max_link_bw = radeon_output->dpcd[1]; 604 int max_lane_count = radeon_dp_max_lane_count(output); 605 606 switch (max_link_bw) { 607 case DP_LINK_BW_1_62: 608 default: 609 for (i = 0; i < num_dp_clocks; i++) { 610 if (i % 2) 611 continue; 612 switch (max_lane_count) { 613 case 1: 614 if (i > 1) 615 return 0; 616 break; 617 case 2: 618 if (i > 3) 619 return 0; 620 break; 621 case 4: 622 default: 623 break; 624 } 625 if (dp_clocks[i] > (mode_clock/10)) { 626 if (i < 2) 627 return 1; 628 else if (i < 4) 629 return 2; 630 else 631 return 4; 632 } 633 } 634 break; 635 case DP_LINK_BW_2_7: 636 for (i = 0; i < num_dp_clocks; i++) { 637 switch (max_lane_count) { 638 case 1: 639 if (i > 1) 640 return 0; 641 break; 642 case 2: 643 if (i > 3) 644 return 0; 645 break; 646 case 4: 647 default: 648 break; 649 } 650 if (dp_clocks[i] > (mode_clock/10)) { 651 if (i < 2) 652 return 1; 653 else if (i < 4) 654 return 2; 655 else 656 return 4; 657 } 658 } 659 break; 660 } 661 662 return 0; 663} 664 665static int 666dp_link_clock_for_mode_clock(xf86OutputPtr output, int mode_clock) 667{ 668 RADEONOutputPrivatePtr radeon_output = output->driver_private; 669 int i; 670 int max_link_bw = radeon_output->dpcd[1]; 671 int max_lane_count = radeon_dp_max_lane_count(output); 672 673 switch (max_link_bw) { 674 case DP_LINK_BW_1_62: 675 default: 676 for (i = 0; i < num_dp_clocks; i++) { 677 if (i % 2) 678 continue; 679 switch (max_lane_count) { 680 case 1: 681 if (i > 1) 682 return 0; 683 break; 684 case 2: 685 if (i > 3) 686 return 0; 687 break; 688 case 4: 689 default: 690 break; 691 } 692 if (dp_clocks[i] > (mode_clock/10)) 693 return 16200; 694 } 695 break; 696 case DP_LINK_BW_2_7: 697 for (i = 0; i < num_dp_clocks; i++) { 698 switch (max_lane_count) { 699 case 1: 700 if (i > 1) 701 return 0; 702 break; 703 case 2: 704 if (i > 3) 705 return 0; 706 break; 707 case 4: 708 default: 709 break; 710 } 711 if (dp_clocks[i] > (mode_clock/10)) 712 return (i % 2) ? 27000 : 16200; 713 } 714 break; 715 } 716 717 return 0; 718} 719 720/* 721 * DIG Encoder/Transmitter Setup 722 * 723 * DCE 3.0/3.1 724 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 725 * Supports up to 3 digital outputs 726 * - 2 DIG encoder blocks. 727 * DIG1 can drive UNIPHY link A or link B 728 * DIG2 can drive UNIPHY link B or LVTMA 729 * 730 * DCE 3.2 731 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 732 * Supports up to 5 digital outputs 733 * - 2 DIG encoder blocks. 734 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 735 * 736 * DCE 4.0 737 * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B). 738 * Supports up to 6 digital outputs 739 * - 6 DIG encoder blocks. 740 * - DIG to PHY mapping is hardcoded 741 * DIG1 drives UNIPHY0 link A, A+B 742 * DIG2 drives UNIPHY0 link B 743 * DIG3 drives UNIPHY1 link A, A+B 744 * DIG4 drives UNIPHY1 link B 745 * DIG5 drives UNIPHY2 link A, A+B 746 * DIG6 drives UNIPHY2 link B 747 * 748 * Routing 749 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 750 * Examples: 751 * crtc0 -> dig2 -> LVTMA links A+B 752 * crtc1 -> dig1 -> UNIPHY0 link B 753 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 754 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 755 */ 756 757union dig_encoder_control { 758 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 759 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 760 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 761}; 762 763static int 764atombios_output_dig_encoder_setup(xf86OutputPtr output, int action) 765{ 766 RADEONOutputPrivatePtr radeon_output = output->driver_private; 767 RADEONInfoPtr info = RADEONPTR(output->scrn); 768 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 769 union dig_encoder_control disp_data; 770 AtomBiosArgRec data; 771 unsigned char *space; 772 int index = 0, major, minor; 773 int clock = radeon_output->pixel_clock; 774 775 if (radeon_encoder == NULL) 776 return ATOM_NOT_IMPLEMENTED; 777 778 memset(&disp_data,0, sizeof(disp_data)); 779 780 if (IS_DCE4_VARIANT) 781 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 782 else if (radeon_output->dig_encoder) 783 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 784 else 785 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 786 787 atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); 788 789 disp_data.v1.ucAction = action; 790 disp_data.v1.usPixelClock = cpu_to_le16(clock / 10); 791 disp_data.v1.ucEncoderMode = atombios_get_encoder_mode(output); 792 793 if (disp_data.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { 794 if (dp_link_clock_for_mode_clock(output, clock) == 27000) 795 disp_data.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 796 disp_data.v1.ucLaneNum = dp_lanes_for_mode_clock(output, clock); 797 } else if (clock > 165000) 798 disp_data.v1.ucLaneNum = 8; 799 else 800 disp_data.v1.ucLaneNum = 4; 801 802 if (IS_DCE4_VARIANT) { 803 disp_data.v3.acConfig.ucDigSel = radeon_output->dig_encoder; 804 disp_data.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; 805 } else { 806 switch (radeon_encoder->encoder_id) { 807 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 808 disp_data.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 809 break; 810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 811 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 812 disp_data.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 813 break; 814 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 815 disp_data.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 816 break; 817 } 818 if (radeon_output->linkb) 819 disp_data.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 820 else 821 disp_data.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 822 } 823 824 data.exec.index = index; 825 data.exec.dataSpace = (void *)&space; 826 data.exec.pspace = &disp_data; 827 828 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 829 ErrorF("Output DIG%d encoder setup success\n", radeon_output->dig_encoder); 830 return ATOM_SUCCESS; 831 } 832 833 ErrorF("Output DIG%d setup failed\n", radeon_output->dig_encoder); 834 return ATOM_NOT_IMPLEMENTED; 835 836} 837 838union dig_transmitter_control { 839 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 840 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 841 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 842}; 843 844static int 845atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t lane_num, uint8_t lane_set) 846{ 847 RADEONOutputPrivatePtr radeon_output = output->driver_private; 848 RADEONInfoPtr info = RADEONPTR(output->scrn); 849 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 850 union dig_transmitter_control disp_data; 851 AtomBiosArgRec data; 852 unsigned char *space; 853 int index = 0, num = 0; 854 int major, minor; 855 int clock = radeon_output->pixel_clock; 856 857 if (radeon_encoder == NULL) 858 return ATOM_NOT_IMPLEMENTED; 859 860 memset(&disp_data,0, sizeof(disp_data)); 861 862 if (IS_DCE32_VARIANT || IS_DCE4_VARIANT) 863 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 864 else { 865 switch (radeon_encoder->encoder_id) { 866 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 867 index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); 868 break; 869 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 870 index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); 871 break; 872 } 873 } 874 875 atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); 876 877 disp_data.v1.ucAction = action; 878 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 879 disp_data.v1.usInitInfo = radeon_output->connector_object_id; 880 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 881 disp_data.v1.asMode.ucLaneSel = lane_num; 882 disp_data.v1.asMode.ucLaneSet = lane_set; 883 } else { 884 if (radeon_output->MonType == MT_DP) 885 disp_data.v1.usPixelClock = 886 cpu_to_le16(dp_link_clock_for_mode_clock(output, clock)); 887 else if (clock > 165000) 888 disp_data.v1.usPixelClock = cpu_to_le16((clock / 2) / 10); 889 else 890 disp_data.v1.usPixelClock = cpu_to_le16(clock / 10); 891 } 892 893 if (IS_DCE4_VARIANT) { 894 if (radeon_output->MonType == MT_DP) 895 disp_data.v3.ucLaneNum = dp_lanes_for_mode_clock(output, clock); 896 else if (clock > 165000) 897 disp_data.v3.ucLaneNum = 8; 898 else 899 disp_data.v3.ucLaneNum = 4; 900 901 if (radeon_output->linkb) { 902 disp_data.v3.acConfig.ucLinkSel = 1; 903 disp_data.v2.acConfig.ucEncoderSel = 1; 904 } 905 906 // select the PLL for the UNIPHY 907 if (radeon_output->MonType == MT_DP && info->dp_extclk) 908 disp_data.v3.acConfig.ucRefClkSource = 2; /* ext clk */ 909 else 910 disp_data.v3.acConfig.ucRefClkSource = radeon_output->pll_id; 911 912 switch (radeon_encoder->encoder_id) { 913 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 914 disp_data.v3.acConfig.ucTransmitterSel = 0; 915 num = 0; 916 break; 917 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 918 disp_data.v3.acConfig.ucTransmitterSel = 1; 919 num = 1; 920 break; 921 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 922 disp_data.v3.acConfig.ucTransmitterSel = 2; 923 num = 2; 924 break; 925 } 926 927 if (radeon_output->MonType == MT_DP) 928 disp_data.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 929 else if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) { 930 if (radeon_output->coherent_mode) 931 disp_data.v3.acConfig.fCoherentMode = 1; 932 if (clock > 165000) 933 disp_data.v3.acConfig.fDualLinkConnector = 1; 934 } 935 } else if (IS_DCE32_VARIANT) { 936 if (radeon_output->dig_encoder) 937 disp_data.v2.acConfig.ucEncoderSel = 1; 938 939 if (radeon_output->linkb) 940 disp_data.v2.acConfig.ucLinkSel = 1; 941 942 switch (radeon_encoder->encoder_id) { 943 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 944 disp_data.v2.acConfig.ucTransmitterSel = 0; 945 num = 0; 946 break; 947 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 948 disp_data.v2.acConfig.ucTransmitterSel = 1; 949 num = 1; 950 break; 951 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 952 disp_data.v2.acConfig.ucTransmitterSel = 2; 953 num = 2; 954 break; 955 } 956 957 if (radeon_output->MonType == MT_DP) 958 disp_data.v2.acConfig.fCoherentMode = 1; /* DP requires coherent */ 959 else if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) { 960 if (radeon_output->coherent_mode) 961 disp_data.v2.acConfig.fCoherentMode = 1; 962 if (clock > 165000) 963 disp_data.v2.acConfig.fDualLinkConnector = 1; 964 } 965 } else { 966 disp_data.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 967 968 if (radeon_output->dig_encoder) 969 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 970 else 971 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 972 973 switch (radeon_encoder->encoder_id) { 974 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 975 if (info->IsIGP) { 976 if (clock > 165000) { 977 if (radeon_output->igp_lane_info & 0x3) 978 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 979 else if (radeon_output->igp_lane_info & 0xc) 980 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 981 } else { 982 if (radeon_output->igp_lane_info & 0x1) 983 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 984 else if (radeon_output->igp_lane_info & 0x2) 985 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 986 else if (radeon_output->igp_lane_info & 0x4) 987 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 988 else if (radeon_output->igp_lane_info & 0x8) 989 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 990 } 991 } 992 break; 993 } 994 if (radeon_output->linkb) 995 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 996 else 997 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 998 999 if (radeon_output->MonType == MT_DP) 1000 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; /* DP requires coherent */ 1001 else if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) { 1002 if (radeon_output->coherent_mode) 1003 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1004 if (clock > 165000) 1005 disp_data.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1006 } 1007 } 1008 1009 data.exec.index = index; 1010 data.exec.dataSpace = (void *)&space; 1011 data.exec.pspace = &disp_data; 1012 1013 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 1014 if (IS_DCE32_VARIANT) 1015 ErrorF("Output UNIPHY%d transmitter setup success\n", num); 1016 else 1017 ErrorF("Output DIG%d transmitter setup success\n", num); 1018 return ATOM_SUCCESS; 1019 } 1020 1021 ErrorF("Output DIG%d transmitter setup failed\n", num); 1022 return ATOM_NOT_IMPLEMENTED; 1023 1024} 1025 1026static void atom_rv515_force_tv_scaler(ScrnInfoPtr pScrn, RADEONCrtcPrivatePtr radeon_crtc) 1027{ 1028 RADEONInfoPtr info = RADEONPTR(pScrn); 1029 unsigned char *RADEONMMIO = info->MMIO; 1030 int index_reg = 0x6578, data_reg = 0x657c; 1031 1032 index_reg += radeon_crtc->crtc_offset; 1033 data_reg += radeon_crtc->crtc_offset; 1034 1035 OUTREG(0x659C + radeon_crtc->crtc_offset, 0x0); 1036 OUTREG(0x6594 + radeon_crtc->crtc_offset, 0x705); 1037 OUTREG(0x65A4 + radeon_crtc->crtc_offset, 0x10001); 1038 OUTREG(0x65D8 + radeon_crtc->crtc_offset, 0x0); 1039 OUTREG(0x65B0 + radeon_crtc->crtc_offset, 0x0); 1040 OUTREG(0x65C0 + radeon_crtc->crtc_offset, 0x0); 1041 OUTREG(0x65D4 + radeon_crtc->crtc_offset, 0x0); 1042 OUTREG(index_reg,0x0); 1043 OUTREG(data_reg,0x841880A8); 1044 OUTREG(index_reg,0x1); 1045 OUTREG(data_reg,0x84208680); 1046 OUTREG(index_reg,0x2); 1047 OUTREG(data_reg,0xBFF880B0); 1048 OUTREG(index_reg,0x100); 1049 OUTREG(data_reg,0x83D88088); 1050 OUTREG(index_reg,0x101); 1051 OUTREG(data_reg,0x84608680); 1052 OUTREG(index_reg,0x102); 1053 OUTREG(data_reg,0xBFF080D0); 1054 OUTREG(index_reg,0x200); 1055 OUTREG(data_reg,0x83988068); 1056 OUTREG(index_reg,0x201); 1057 OUTREG(data_reg,0x84A08680); 1058 OUTREG(index_reg,0x202); 1059 OUTREG(data_reg,0xBFF080F8); 1060 OUTREG(index_reg,0x300); 1061 OUTREG(data_reg,0x83588058); 1062 OUTREG(index_reg,0x301); 1063 OUTREG(data_reg,0x84E08660); 1064 OUTREG(index_reg,0x302); 1065 OUTREG(data_reg,0xBFF88120); 1066 OUTREG(index_reg,0x400); 1067 OUTREG(data_reg,0x83188040); 1068 OUTREG(index_reg,0x401); 1069 OUTREG(data_reg,0x85008660); 1070 OUTREG(index_reg,0x402); 1071 OUTREG(data_reg,0xBFF88150); 1072 OUTREG(index_reg,0x500); 1073 OUTREG(data_reg,0x82D88030); 1074 OUTREG(index_reg,0x501); 1075 OUTREG(data_reg,0x85408640); 1076 OUTREG(index_reg,0x502); 1077 OUTREG(data_reg,0xBFF88180); 1078 OUTREG(index_reg,0x600); 1079 OUTREG(data_reg,0x82A08018); 1080 OUTREG(index_reg,0x601); 1081 OUTREG(data_reg,0x85808620); 1082 OUTREG(index_reg,0x602); 1083 OUTREG(data_reg,0xBFF081B8); 1084 OUTREG(index_reg,0x700); 1085 OUTREG(data_reg,0x82608010); 1086 OUTREG(index_reg,0x701); 1087 OUTREG(data_reg,0x85A08600); 1088 OUTREG(index_reg,0x702); 1089 OUTREG(data_reg,0x800081F0); 1090 OUTREG(index_reg,0x800); 1091 OUTREG(data_reg,0x8228BFF8); 1092 OUTREG(index_reg,0x801); 1093 OUTREG(data_reg,0x85E085E0); 1094 OUTREG(index_reg,0x802); 1095 OUTREG(data_reg,0xBFF88228); 1096 OUTREG(index_reg,0x10000); 1097 OUTREG(data_reg,0x82A8BF00); 1098 OUTREG(index_reg,0x10001); 1099 OUTREG(data_reg,0x82A08CC0); 1100 OUTREG(index_reg,0x10002); 1101 OUTREG(data_reg,0x8008BEF8); 1102 OUTREG(index_reg,0x10100); 1103 OUTREG(data_reg,0x81F0BF28); 1104 OUTREG(index_reg,0x10101); 1105 OUTREG(data_reg,0x83608CA0); 1106 OUTREG(index_reg,0x10102); 1107 OUTREG(data_reg,0x8018BED0); 1108 OUTREG(index_reg,0x10200); 1109 OUTREG(data_reg,0x8148BF38); 1110 OUTREG(index_reg,0x10201); 1111 OUTREG(data_reg,0x84408C80); 1112 OUTREG(index_reg,0x10202); 1113 OUTREG(data_reg,0x8008BEB8); 1114 OUTREG(index_reg,0x10300); 1115 OUTREG(data_reg,0x80B0BF78); 1116 OUTREG(index_reg,0x10301); 1117 OUTREG(data_reg,0x85008C20); 1118 OUTREG(index_reg,0x10302); 1119 OUTREG(data_reg,0x8020BEA0); 1120 OUTREG(index_reg,0x10400); 1121 OUTREG(data_reg,0x8028BF90); 1122 OUTREG(index_reg,0x10401); 1123 OUTREG(data_reg,0x85E08BC0); 1124 OUTREG(index_reg,0x10402); 1125 OUTREG(data_reg,0x8018BE90); 1126 OUTREG(index_reg,0x10500); 1127 OUTREG(data_reg,0xBFB8BFB0); 1128 OUTREG(index_reg,0x10501); 1129 OUTREG(data_reg,0x86C08B40); 1130 OUTREG(index_reg,0x10502); 1131 OUTREG(data_reg,0x8010BE90); 1132 OUTREG(index_reg,0x10600); 1133 OUTREG(data_reg,0xBF58BFC8); 1134 OUTREG(index_reg,0x10601); 1135 OUTREG(data_reg,0x87A08AA0); 1136 OUTREG(index_reg,0x10602); 1137 OUTREG(data_reg,0x8010BE98); 1138 OUTREG(index_reg,0x10700); 1139 OUTREG(data_reg,0xBF10BFF0); 1140 OUTREG(index_reg,0x10701); 1141 OUTREG(data_reg,0x886089E0); 1142 OUTREG(index_reg,0x10702); 1143 OUTREG(data_reg,0x8018BEB0); 1144 OUTREG(index_reg,0x10800); 1145 OUTREG(data_reg,0xBED8BFE8); 1146 OUTREG(index_reg,0x10801); 1147 OUTREG(data_reg,0x89408940); 1148 OUTREG(index_reg,0x10802); 1149 OUTREG(data_reg,0xBFE8BED8); 1150 OUTREG(index_reg,0x20000); 1151 OUTREG(data_reg,0x80008000); 1152 OUTREG(index_reg,0x20001); 1153 OUTREG(data_reg,0x90008000); 1154 OUTREG(index_reg,0x20002); 1155 OUTREG(data_reg,0x80008000); 1156 OUTREG(index_reg,0x20003); 1157 OUTREG(data_reg,0x80008000); 1158 OUTREG(index_reg,0x20100); 1159 OUTREG(data_reg,0x80108000); 1160 OUTREG(index_reg,0x20101); 1161 OUTREG(data_reg,0x8FE0BF70); 1162 OUTREG(index_reg,0x20102); 1163 OUTREG(data_reg,0xBFE880C0); 1164 OUTREG(index_reg,0x20103); 1165 OUTREG(data_reg,0x80008000); 1166 OUTREG(index_reg,0x20200); 1167 OUTREG(data_reg,0x8018BFF8); 1168 OUTREG(index_reg,0x20201); 1169 OUTREG(data_reg,0x8F80BF08); 1170 OUTREG(index_reg,0x20202); 1171 OUTREG(data_reg,0xBFD081A0); 1172 OUTREG(index_reg,0x20203); 1173 OUTREG(data_reg,0xBFF88000); 1174 OUTREG(index_reg,0x20300); 1175 OUTREG(data_reg,0x80188000); 1176 OUTREG(index_reg,0x20301); 1177 OUTREG(data_reg,0x8EE0BEC0); 1178 OUTREG(index_reg,0x20302); 1179 OUTREG(data_reg,0xBFB082A0); 1180 OUTREG(index_reg,0x20303); 1181 OUTREG(data_reg,0x80008000); 1182 OUTREG(index_reg,0x20400); 1183 OUTREG(data_reg,0x80188000); 1184 OUTREG(index_reg,0x20401); 1185 OUTREG(data_reg,0x8E00BEA0); 1186 OUTREG(index_reg,0x20402); 1187 OUTREG(data_reg,0xBF8883C0); 1188 OUTREG(index_reg,0x20403); 1189 OUTREG(data_reg,0x80008000); 1190 OUTREG(index_reg,0x20500); 1191 OUTREG(data_reg,0x80188000); 1192 OUTREG(index_reg,0x20501); 1193 OUTREG(data_reg,0x8D00BE90); 1194 OUTREG(index_reg,0x20502); 1195 OUTREG(data_reg,0xBF588500); 1196 OUTREG(index_reg,0x20503); 1197 OUTREG(data_reg,0x80008008); 1198 OUTREG(index_reg,0x20600); 1199 OUTREG(data_reg,0x80188000); 1200 OUTREG(index_reg,0x20601); 1201 OUTREG(data_reg,0x8BC0BE98); 1202 OUTREG(index_reg,0x20602); 1203 OUTREG(data_reg,0xBF308660); 1204 OUTREG(index_reg,0x20603); 1205 OUTREG(data_reg,0x80008008); 1206 OUTREG(index_reg,0x20700); 1207 OUTREG(data_reg,0x80108000); 1208 OUTREG(index_reg,0x20701); 1209 OUTREG(data_reg,0x8A80BEB0); 1210 OUTREG(index_reg,0x20702); 1211 OUTREG(data_reg,0xBF0087C0); 1212 OUTREG(index_reg,0x20703); 1213 OUTREG(data_reg,0x80008008); 1214 OUTREG(index_reg,0x20800); 1215 OUTREG(data_reg,0x80108000); 1216 OUTREG(index_reg,0x20801); 1217 OUTREG(data_reg,0x8920BED0); 1218 OUTREG(index_reg,0x20802); 1219 OUTREG(data_reg,0xBED08920); 1220 OUTREG(index_reg,0x20803); 1221 OUTREG(data_reg,0x80008010); 1222 OUTREG(index_reg,0x30000); 1223 OUTREG(data_reg,0x90008000); 1224 OUTREG(index_reg,0x30001); 1225 OUTREG(data_reg,0x80008000); 1226 OUTREG(index_reg,0x30100); 1227 OUTREG(data_reg,0x8FE0BF90); 1228 OUTREG(index_reg,0x30101); 1229 OUTREG(data_reg,0xBFF880A0); 1230 OUTREG(index_reg,0x30200); 1231 OUTREG(data_reg,0x8F60BF40); 1232 OUTREG(index_reg,0x30201); 1233 OUTREG(data_reg,0xBFE88180); 1234 OUTREG(index_reg,0x30300); 1235 OUTREG(data_reg,0x8EC0BF00); 1236 OUTREG(index_reg,0x30301); 1237 OUTREG(data_reg,0xBFC88280); 1238 OUTREG(index_reg,0x30400); 1239 OUTREG(data_reg,0x8DE0BEE0); 1240 OUTREG(index_reg,0x30401); 1241 OUTREG(data_reg,0xBFA083A0); 1242 OUTREG(index_reg,0x30500); 1243 OUTREG(data_reg,0x8CE0BED0); 1244 OUTREG(index_reg,0x30501); 1245 OUTREG(data_reg,0xBF7884E0); 1246 OUTREG(index_reg,0x30600); 1247 OUTREG(data_reg,0x8BA0BED8); 1248 OUTREG(index_reg,0x30601); 1249 OUTREG(data_reg,0xBF508640); 1250 OUTREG(index_reg,0x30700); 1251 OUTREG(data_reg,0x8A60BEE8); 1252 OUTREG(index_reg,0x30701); 1253 OUTREG(data_reg,0xBF2087A0); 1254 OUTREG(index_reg,0x30800); 1255 OUTREG(data_reg,0x8900BF00); 1256 OUTREG(index_reg,0x30801); 1257 OUTREG(data_reg,0xBF008900); 1258} 1259 1260static int 1261atombios_output_yuv_setup(xf86OutputPtr output, Bool enable) 1262{ 1263 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1264 RADEONInfoPtr info = RADEONPTR(output->scrn); 1265 RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; 1266 ENABLE_YUV_PS_ALLOCATION disp_data; 1267 AtomBiosArgRec data; 1268 unsigned char *space; 1269 unsigned char *RADEONMMIO = info->MMIO; 1270 uint32_t temp, reg; 1271 1272 if (info->ChipFamily >= CHIP_FAMILY_R600) 1273 reg = R600_BIOS_3_SCRATCH; 1274 else 1275 reg = RADEON_BIOS_3_SCRATCH; 1276 1277 //fix up scratch reg handling 1278 temp = INREG(reg); 1279 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1280 OUTREG(reg, (ATOM_S3_TV1_ACTIVE | 1281 (radeon_crtc->crtc_id << 18))); 1282 else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1283 OUTREG(reg, (ATOM_S3_CV_ACTIVE | 1284 (radeon_crtc->crtc_id << 24))); 1285 else 1286 OUTREG(reg, 0); 1287 1288 memset(&disp_data, 0, sizeof(disp_data)); 1289 1290 if (enable) 1291 disp_data.ucEnable = ATOM_ENABLE; 1292 disp_data.ucCRTC = radeon_crtc->crtc_id; 1293 1294 data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1295 data.exec.dataSpace = (void *)&space; 1296 data.exec.pspace = &disp_data; 1297 1298 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 1299 1300 OUTREG(reg, temp); 1301 1302 ErrorF("crtc %d YUV %s setup success\n", radeon_crtc->crtc_id, enable ? "enable" : "disable"); 1303 return ATOM_SUCCESS; 1304 } 1305 1306 OUTREG(reg, temp); 1307 1308 ErrorF("crtc %d YUV %s setup failed\n", radeon_crtc->crtc_id, enable ? "enable" : "disable"); 1309 return ATOM_NOT_IMPLEMENTED; 1310 1311} 1312 1313static int 1314atombios_output_overscan_setup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode) 1315{ 1316 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1317 RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; 1318 RADEONInfoPtr info = RADEONPTR(output->scrn); 1319 SET_CRTC_OVERSCAN_PS_ALLOCATION overscan_param; 1320 AtomBiosArgRec data; 1321 unsigned char *space; 1322 memset(&overscan_param, 0, sizeof(overscan_param)); 1323 1324 overscan_param.usOverscanRight = 0; 1325 overscan_param.usOverscanLeft = 0; 1326 overscan_param.usOverscanBottom = 0; 1327 overscan_param.usOverscanTop = 0; 1328 overscan_param.ucCRTC = radeon_crtc->crtc_id; 1329 1330 if (radeon_output->Flags & RADEON_USE_RMX) { 1331 if (radeon_output->rmx_type == RMX_FULL) { 1332 overscan_param.usOverscanRight = 0; 1333 overscan_param.usOverscanLeft = 0; 1334 overscan_param.usOverscanBottom = 0; 1335 overscan_param.usOverscanTop = 0; 1336 } else if (radeon_output->rmx_type == RMX_CENTER) { 1337 overscan_param.usOverscanTop = (adjusted_mode->CrtcVDisplay - mode->CrtcVDisplay) / 2; 1338 overscan_param.usOverscanBottom = (adjusted_mode->CrtcVDisplay - mode->CrtcVDisplay) / 2; 1339 overscan_param.usOverscanLeft = (adjusted_mode->CrtcHDisplay - mode->CrtcHDisplay) / 2; 1340 overscan_param.usOverscanRight = (adjusted_mode->CrtcHDisplay - mode->CrtcHDisplay) / 2; 1341 } else if (radeon_output->rmx_type == RMX_ASPECT) { 1342 int a1 = mode->CrtcVDisplay * adjusted_mode->CrtcHDisplay; 1343 int a2 = adjusted_mode->CrtcVDisplay * mode->CrtcHDisplay; 1344 1345 if (a1 > a2) { 1346 overscan_param.usOverscanLeft = (adjusted_mode->CrtcHDisplay - (a2 / mode->CrtcVDisplay)) / 2; 1347 overscan_param.usOverscanRight = (adjusted_mode->CrtcHDisplay - (a2 / mode->CrtcVDisplay)) / 2; 1348 } else if (a2 > a1) { 1349 overscan_param.usOverscanLeft = (adjusted_mode->CrtcVDisplay - (a1 / mode->CrtcHDisplay)) / 2; 1350 overscan_param.usOverscanRight = (adjusted_mode->CrtcVDisplay - (a1 / mode->CrtcHDisplay)) / 2; 1351 } 1352 } 1353 } 1354 1355 data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 1356 data.exec.dataSpace = (void *)&space; 1357 data.exec.pspace = &overscan_param; 1358 1359 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 1360 ErrorF("Set CRTC %d Overscan success\n", radeon_crtc->crtc_id); 1361 return ATOM_SUCCESS ; 1362 } 1363 1364 ErrorF("Set CRTC %d Overscan failed\n", radeon_crtc->crtc_id); 1365 return ATOM_NOT_IMPLEMENTED; 1366} 1367 1368static int 1369atombios_output_scaler_setup(xf86OutputPtr output) 1370{ 1371 RADEONInfoPtr info = RADEONPTR(output->scrn); 1372 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1373 radeon_tvout_ptr tvout = &radeon_output->tvout; 1374 RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; 1375 ENABLE_SCALER_PS_ALLOCATION disp_data; 1376 AtomBiosArgRec data; 1377 unsigned char *space; 1378 1379 if (!IS_AVIVO_VARIANT && radeon_crtc->crtc_id) 1380 return ATOM_SUCCESS; 1381 1382 memset(&disp_data, 0, sizeof(disp_data)); 1383 1384 disp_data.ucScaler = radeon_crtc->crtc_id; 1385 1386 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 1387 switch (tvout->tvStd) { 1388 case TV_STD_NTSC: 1389 disp_data.ucTVStandard = ATOM_TV_NTSC; 1390 break; 1391 case TV_STD_PAL: 1392 disp_data.ucTVStandard = ATOM_TV_PAL; 1393 break; 1394 case TV_STD_PAL_M: 1395 disp_data.ucTVStandard = ATOM_TV_PALM; 1396 break; 1397 case TV_STD_PAL_60: 1398 disp_data.ucTVStandard = ATOM_TV_PAL60; 1399 break; 1400 case TV_STD_NTSC_J: 1401 disp_data.ucTVStandard = ATOM_TV_NTSCJ; 1402 break; 1403 case TV_STD_SCART_PAL: 1404 disp_data.ucTVStandard = ATOM_TV_PAL; /* ??? */ 1405 break; 1406 case TV_STD_SECAM: 1407 disp_data.ucTVStandard = ATOM_TV_SECAM; 1408 break; 1409 case TV_STD_PAL_CN: 1410 disp_data.ucTVStandard = ATOM_TV_PALCN; 1411 break; 1412 default: 1413 disp_data.ucTVStandard = ATOM_TV_NTSC; 1414 break; 1415 } 1416 disp_data.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 1417 ErrorF("Using TV scaler %x %x\n", disp_data.ucTVStandard, disp_data.ucEnable); 1418 } else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) { 1419 disp_data.ucTVStandard = ATOM_TV_CV; 1420 disp_data.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 1421 ErrorF("Using CV scaler %x %x\n", disp_data.ucTVStandard, disp_data.ucEnable); 1422 } else if (radeon_output->Flags & RADEON_USE_RMX) { 1423 ErrorF("Using RMX\n"); 1424 if (radeon_output->rmx_type == RMX_FULL) 1425 disp_data.ucEnable = ATOM_SCALER_EXPANSION; 1426 else if (radeon_output->rmx_type == RMX_CENTER) 1427 disp_data.ucEnable = ATOM_SCALER_CENTER; 1428 else if (radeon_output->rmx_type == RMX_ASPECT) 1429 disp_data.ucEnable = ATOM_SCALER_EXPANSION; 1430 } else { 1431 ErrorF("Not using RMX\n"); 1432 if (IS_AVIVO_VARIANT) 1433 disp_data.ucEnable = ATOM_SCALER_DISABLE; 1434 else 1435 disp_data.ucEnable = ATOM_SCALER_CENTER; 1436 } 1437 1438 data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 1439 data.exec.dataSpace = (void *)&space; 1440 data.exec.pspace = &disp_data; 1441 1442 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 1443 if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT) 1444 && info->ChipFamily >= CHIP_FAMILY_RV515 && info->ChipFamily <= CHIP_FAMILY_RV570) { 1445 ErrorF("forcing TV scaler\n"); 1446 atom_rv515_force_tv_scaler(output->scrn, radeon_crtc); 1447 } 1448 ErrorF("scaler %d setup success\n", radeon_crtc->crtc_id); 1449 return ATOM_SUCCESS; 1450 } 1451 1452 ErrorF("scaler %d setup failed\n", radeon_crtc->crtc_id); 1453 return ATOM_NOT_IMPLEMENTED; 1454 1455} 1456 1457void 1458atombios_output_dpms(xf86OutputPtr output, int mode) 1459{ 1460 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1461 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1462 RADEONInfoPtr info = RADEONPTR(output->scrn); 1463 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION disp_data; 1464 AtomBiosArgRec data; 1465 unsigned char *space; 1466 int index = 0; 1467 Bool is_dig = FALSE; 1468 1469 if (radeon_encoder == NULL) 1470 return; 1471 1472 switch (radeon_encoder->encoder_id) { 1473 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1474 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1475 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1476 break; 1477 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1478 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1479 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1480 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1481 is_dig = TRUE; 1482 break; 1483 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1484 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1485 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1486 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1487 break; 1488 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1489 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1490 break; 1491 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1492 if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 1493 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1494 else 1495 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1496 break; 1497 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1498 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1499 if (IS_DCE32_VARIANT) 1500 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1501 else { 1502 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1503 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1504 else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1505 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1506 else 1507 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1508 } 1509 break; 1510 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1511 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1512 if (IS_DCE32_VARIANT) 1513 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1514 else { 1515 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1516 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1517 else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1518 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1519 else 1520 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1521 } 1522 break; 1523 } 1524 1525 switch (mode) { 1526 case DPMSModeOn: 1527 radeon_encoder->devices |= radeon_output->active_device; 1528 if (is_dig) { 1529 atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1530 if (((radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT) || 1531 (radeon_output->ConnectorType == CONNECTOR_EDP)) && 1532 (radeon_output->MonType == MT_DP)) { 1533 do_displayport_link_train(output); 1534 if (IS_DCE4_VARIANT) 1535 atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_VIDEO_ON); 1536 } 1537 } 1538 else { 1539 disp_data.ucAction = ATOM_ENABLE; 1540 data.exec.index = index; 1541 data.exec.dataSpace = (void *)&space; 1542 data.exec.pspace = &disp_data; 1543 1544 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) 1545 ErrorF("Output %s enable success\n", 1546 device_name[radeon_get_device_index(radeon_output->active_device)]); 1547 else 1548 ErrorF("Output %s enable failed\n", 1549 device_name[radeon_get_device_index(radeon_output->active_device)]); 1550 } 1551 /* at least for TV atom fails to reassociate the correct crtc source at dpms on */ 1552 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1553 atombios_set_output_crtc_source(output); 1554 break; 1555 case DPMSModeStandby: 1556 case DPMSModeSuspend: 1557 case DPMSModeOff: 1558 radeon_encoder->devices &= ~(radeon_output->active_device); 1559 if (!radeon_encoder->devices) { 1560 if (is_dig) { 1561 atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1562 if (((radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT) || 1563 (radeon_output->ConnectorType == CONNECTOR_EDP)) && 1564 (radeon_output->MonType == MT_DP)) { 1565 if (IS_DCE4_VARIANT) 1566 atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_VIDEO_OFF); 1567 } 1568 } else { 1569 disp_data.ucAction = ATOM_DISABLE; 1570 data.exec.index = index; 1571 data.exec.dataSpace = (void *)&space; 1572 data.exec.pspace = &disp_data; 1573 1574 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) 1575 == ATOM_SUCCESS) 1576 ErrorF("Output %s disable success\n", 1577 device_name[radeon_get_device_index(radeon_output->active_device)]); 1578 else 1579 ErrorF("Output %s disable failed\n", 1580 device_name[radeon_get_device_index(radeon_output->active_device)]); 1581 } 1582 } 1583 break; 1584 } 1585} 1586 1587union crtc_source_param { 1588 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1589 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1590}; 1591 1592void 1593atombios_set_output_crtc_source(xf86OutputPtr output) 1594{ 1595 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1596 RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; 1597 RADEONInfoPtr info = RADEONPTR(output->scrn); 1598 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1599 AtomBiosArgRec data; 1600 unsigned char *space; 1601 union crtc_source_param args; 1602 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1603 int major, minor; 1604 1605 if (radeon_encoder == NULL) 1606 return; 1607 1608 memset(&args, 0, sizeof(args)); 1609 1610 atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); 1611 1612 /*ErrorF("select crtc source table is %d %d\n", major, minor);*/ 1613 1614 switch(major) { 1615 case 1: 1616 switch(minor) { 1617 case 0: 1618 case 1: 1619 default: 1620 if (IS_AVIVO_VARIANT) 1621 args.v1.ucCRTC = radeon_crtc->crtc_id; 1622 else { 1623 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) 1624 args.v1.ucCRTC = radeon_crtc->crtc_id; 1625 else 1626 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1627 } 1628 switch (radeon_encoder->encoder_id) { 1629 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1631 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1632 break; 1633 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1634 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1635 if (radeon_output->active_device & ATOM_DEVICE_LCD1_SUPPORT) 1636 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1637 else 1638 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1639 break; 1640 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1641 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1642 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1643 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1644 break; 1645 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1646 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1647 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1648 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1649 else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1650 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1651 else 1652 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1653 break; 1654 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1655 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1656 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1657 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1658 else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1659 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1660 else 1661 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1662 break; 1663 } 1664 /*ErrorF("device sourced: 0x%x\n", args.v1.ucDevice);*/ 1665 break; 1666 case 2: 1667 args.v2.ucCRTC = radeon_crtc->crtc_id; 1668 args.v2.ucEncodeMode = atombios_get_encoder_mode(output); 1669 switch (radeon_encoder->encoder_id) { 1670 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1671 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1672 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1674 switch (radeon_output->dig_encoder) { 1675 case 0: 1676 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1677 break; 1678 case 1: 1679 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1680 break; 1681 case 2: 1682 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1683 break; 1684 case 3: 1685 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1686 break; 1687 case 4: 1688 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1689 break; 1690 case 5: 1691 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1692 break; 1693 } 1694 break; 1695 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1696 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1697 break; 1698 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1699 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1700 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1701 else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1702 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1703 else 1704 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1705 break; 1706 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1707 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1708 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1709 else if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1710 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1711 else 1712 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1713 break; 1714 } 1715 /*ErrorF("device sourced: 0x%x\n", args.v2.ucEncoderID);*/ 1716 break; 1717 } 1718 break; 1719 default: 1720 ErrorF("Unknown table version\n"); 1721 exit(-1); 1722 } 1723 1724 data.exec.pspace = &args; 1725 data.exec.index = index; 1726 data.exec.dataSpace = (void *)&space; 1727 1728 if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 1729 ErrorF("Set CRTC %d Source success\n", radeon_crtc->crtc_id); 1730 return; 1731 } 1732 1733 ErrorF("Set CRTC Source failed\n"); 1734 return; 1735} 1736 1737static void 1738atombios_apply_output_quirks(xf86OutputPtr output, DisplayModePtr mode) 1739{ 1740 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1741 RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; 1742 RADEONInfoPtr info = RADEONPTR(output->scrn); 1743 unsigned char *RADEONMMIO = info->MMIO; 1744 1745 /* Funky macbooks */ 1746 if ((info->Chipset == PCI_CHIP_RV530_71C5) && 1747 (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x106b) && 1748 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0080)) { 1749 if (radeon_output->MonType == MT_LCD) { 1750 if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1751 uint32_t lvtma_bit_depth_control = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1752 1753 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1754 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1755 1756 OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1757 } 1758 } 1759 } 1760 1761 /* set scaler clears this on some chips */ 1762 if (!(radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))) { 1763 if (IS_AVIVO_VARIANT && (mode->Flags & V_INTERLACE)) 1764 OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN); 1765 } 1766 1767 if (IS_DCE32_VARIANT && 1768 (!IS_DCE4_VARIANT) && 1769 (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT))) { 1770 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1771 if (radeon_encoder == NULL) 1772 return; 1773 /* XXX: need to sort out why transmitter control table sometimes sets this to a 1774 * different golden value. 1775 */ 1776 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY2) { 1777 OUTREG(0x7ec4, 0x00824002); 1778 } 1779 } 1780} 1781 1782void 1783atombios_pick_dig_encoder(xf86OutputPtr output) 1784{ 1785 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(output->scrn); 1786 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1787 RADEONInfoPtr info = RADEONPTR(output->scrn); 1788 radeon_encoder_ptr radeon_encoder = NULL; 1789 Bool is_lvtma = FALSE; 1790 int i, mode; 1791 uint32_t dig_enc_use_mask = 0; 1792 1793 /* non digital encoders don't need a dig block */ 1794 mode = atombios_get_encoder_mode(output); 1795 if (mode == ATOM_ENCODER_MODE_CRT || 1796 mode == ATOM_ENCODER_MODE_TV || 1797 mode == ATOM_ENCODER_MODE_CV) 1798 return; 1799 1800 if (IS_DCE4_VARIANT) { 1801 radeon_encoder = radeon_get_encoder(output); 1802 1803 if (IS_DCE41_VARIANT) { 1804 if (radeon_output->linkb) 1805 radeon_output->dig_encoder = 1; 1806 else 1807 radeon_output->dig_encoder = 0; 1808 } else { 1809 switch (radeon_encoder->encoder_id) { 1810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1811 if (radeon_output->linkb) 1812 radeon_output->dig_encoder = 1; 1813 else 1814 radeon_output->dig_encoder = 0; 1815 break; 1816 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1817 if (radeon_output->linkb) 1818 radeon_output->dig_encoder = 3; 1819 else 1820 radeon_output->dig_encoder = 2; 1821 break; 1822 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1823 if (radeon_output->linkb) 1824 radeon_output->dig_encoder = 5; 1825 else 1826 radeon_output->dig_encoder = 4; 1827 break; 1828 default: 1829 ErrorF("Unknown encoder\n"); 1830 break; 1831 } 1832 } 1833 return; 1834 } 1835 1836 if (IS_DCE32_VARIANT) { 1837 RADEONCrtcPrivatePtr radeon_crtc = output->crtc->driver_private; 1838 radeon_output->dig_encoder = radeon_crtc->crtc_id; 1839 return; 1840 } 1841 1842 for (i = 0; i < xf86_config->num_output; i++) { 1843 xf86OutputPtr test = xf86_config->output[i]; 1844 RADEONOutputPrivatePtr radeon_test = test->driver_private; 1845 radeon_encoder = radeon_get_encoder(test); 1846 1847 if (!radeon_encoder || !test->crtc) 1848 continue; 1849 1850 if (output == test && radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) 1851 is_lvtma = TRUE; 1852 if (output != test && (radeon_test->dig_encoder >= 0)) 1853 dig_enc_use_mask |= (1 << radeon_test->dig_encoder); 1854 1855 } 1856 if (is_lvtma) { 1857 if (dig_enc_use_mask & 0x2) 1858 ErrorF("Need digital encoder 2 for LVTMA and it isn't free - stealing\n"); 1859 radeon_output->dig_encoder = 1; 1860 return; 1861 } 1862 if (!(dig_enc_use_mask & 1)) 1863 radeon_output->dig_encoder = 0; 1864 else 1865 radeon_output->dig_encoder = 1; 1866} 1867void 1868atombios_output_mode_set(xf86OutputPtr output, 1869 DisplayModePtr mode, 1870 DisplayModePtr adjusted_mode) 1871{ 1872 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1873 radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output); 1874 RADEONInfoPtr info = RADEONPTR(output->scrn); 1875 if (radeon_encoder == NULL) 1876 return; 1877 1878 radeon_output->pixel_clock = adjusted_mode->Clock; 1879 atombios_output_overscan_setup(output, mode, adjusted_mode); 1880 atombios_output_scaler_setup(output); 1881 atombios_set_output_crtc_source(output); 1882 1883 if (IS_AVIVO_VARIANT && !IS_DCE4_VARIANT) { 1884 if (radeon_output->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1885 atombios_output_yuv_setup(output, TRUE); 1886 else 1887 atombios_output_yuv_setup(output, FALSE); 1888 } 1889 1890 switch (radeon_encoder->encoder_id) { 1891 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1893 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1894 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1895 atombios_output_digital_setup(output, PANEL_ENCODER_ACTION_ENABLE); 1896 break; 1897 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1898 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1899 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1900 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1901 /* disable encoder and transmitter */ 1902 /* setup and enable the encoder and transmitter */ 1903 if (IS_DCE4_VARIANT) { 1904 atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1905 atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_SETUP); 1906 atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 1907 atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1908 } else { 1909 atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1910 atombios_output_dig_encoder_setup(output, ATOM_DISABLE); 1911 atombios_output_dig_encoder_setup(output, ATOM_ENABLE); 1912 1913 atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 1914 atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1915 atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1916 } 1917 break; 1918 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1919 atombios_output_ddia_setup(output, ATOM_ENABLE); 1920 break; 1921 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1922 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1923 atombios_external_tmds_setup(output, ATOM_ENABLE); 1924 break; 1925 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1926 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1927 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1928 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1929 atombios_output_dac_setup(output, ATOM_ENABLE); 1930 if (radeon_output->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 1931 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1932 atombios_output_tv_setup(output, ATOM_ENABLE); 1933 else 1934 atombios_output_tv_setup(output, ATOM_DISABLE); 1935 } 1936 break; 1937 } 1938 atombios_apply_output_quirks(output, adjusted_mode); 1939} 1940 1941static AtomBiosResult 1942atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) 1943{ 1944 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1945 RADEONInfoPtr info = RADEONPTR(output->scrn); 1946 DAC_LOAD_DETECTION_PS_ALLOCATION dac_data; 1947 AtomBiosArgRec data; 1948 unsigned char *space; 1949 int major, minor; 1950 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 1951 1952 atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); 1953 1954 dac_data.sDacload.ucMisc = 0; 1955 1956 if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1957 dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 1958 if (info->encoders[ATOM_DEVICE_CRT1_INDEX] && 1959 ((info->encoders[ATOM_DEVICE_CRT1_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1960 (info->encoders[ATOM_DEVICE_CRT1_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))) 1961 dac_data.sDacload.ucDacType = ATOM_DAC_A; 1962 else 1963 dac_data.sDacload.ucDacType = ATOM_DAC_B; 1964 } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1965 dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 1966 if (info->encoders[ATOM_DEVICE_CRT2_INDEX] && 1967 ((info->encoders[ATOM_DEVICE_CRT2_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1968 (info->encoders[ATOM_DEVICE_CRT2_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))) 1969 dac_data.sDacload.ucDacType = ATOM_DAC_A; 1970 else 1971 dac_data.sDacload.ucDacType = ATOM_DAC_B; 1972 } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) { 1973 dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 1974 if (info->encoders[ATOM_DEVICE_CV_INDEX] && 1975 ((info->encoders[ATOM_DEVICE_CV_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1976 (info->encoders[ATOM_DEVICE_CV_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))) 1977 dac_data.sDacload.ucDacType = ATOM_DAC_A; 1978 else 1979 dac_data.sDacload.ucDacType = ATOM_DAC_B; 1980 if (minor >= 3) 1981 dac_data.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1982 } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { 1983 dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 1984 if (info->encoders[ATOM_DEVICE_TV1_INDEX] && 1985 ((info->encoders[ATOM_DEVICE_TV1_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1986 (info->encoders[ATOM_DEVICE_TV1_INDEX]->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))) 1987 dac_data.sDacload.ucDacType = ATOM_DAC_A; 1988 else 1989 dac_data.sDacload.ucDacType = ATOM_DAC_B; 1990 if (minor >= 3) 1991 dac_data.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1992 } else 1993 return ATOM_NOT_IMPLEMENTED; 1994 1995 data.exec.index = index; 1996 data.exec.dataSpace = (void *)&space; 1997 data.exec.pspace = &dac_data; 1998 1999 if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { 2000 ErrorF("Dac detection success\n"); 2001 return ATOM_SUCCESS ; 2002 } 2003 2004 ErrorF("DAC detection failed\n"); 2005 return ATOM_NOT_IMPLEMENTED; 2006} 2007 2008RADEONMonitorType 2009atombios_dac_detect(xf86OutputPtr output) 2010{ 2011 ScrnInfoPtr pScrn = output->scrn; 2012 RADEONInfoPtr info = RADEONPTR(pScrn); 2013 unsigned char *RADEONMMIO = info->MMIO; 2014 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2015 RADEONMonitorType MonType = MT_NONE; 2016 AtomBiosResult ret; 2017 RADEONSavePtr save = info->ModeReg; 2018 2019 if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { 2020 if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) { 2021 if (radeon_output->ConnectorType == CONNECTOR_STV) 2022 return MT_STV; 2023 else 2024 return MT_CTV; 2025 } 2026 } 2027 2028 ret = atom_bios_dac_load_detect(info->atomBIOS, output); 2029 if (ret == ATOM_SUCCESS) { 2030 if (info->ChipFamily >= CHIP_FAMILY_R600) 2031 save->bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); 2032 else 2033 save->bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); 2034 /*ErrorF("DAC connect %08X\n", (unsigned int)save->bios_0_scratch);*/ 2035 2036 if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2037 if (save->bios_0_scratch & ATOM_S0_CRT1_MASK) 2038 MonType = MT_CRT; 2039 } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2040 if (save->bios_0_scratch & ATOM_S0_CRT2_MASK) 2041 MonType = MT_CRT; 2042 } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) { 2043 if (save->bios_0_scratch & (ATOM_S0_CV_MASK | ATOM_S0_CV_MASK_A)) 2044 MonType = MT_CV; 2045 } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { 2046 if (save->bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2047 MonType = MT_CTV; 2048 else if (save->bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2049 MonType = MT_STV; 2050 } 2051 } 2052 2053 return MonType; 2054} 2055 2056 2057static inline int atom_dp_get_encoder_id(xf86OutputPtr output) 2058{ 2059 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2060 int ret = 0; 2061 if (radeon_output->dig_encoder) 2062 ret |= ATOM_DP_CONFIG_DIG2_ENCODER; 2063 else 2064 ret |= ATOM_DP_CONFIG_DIG1_ENCODER; 2065 if (radeon_output->linkb) 2066 ret |= ATOM_DP_CONFIG_LINK_B; 2067 else 2068 ret |= ATOM_DP_CONFIG_LINK_A; 2069 return ret; 2070} 2071 2072union aux_channel_transaction { 2073 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 2074 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 2075}; 2076 2077Bool 2078RADEONProcessAuxCH(xf86OutputPtr output, uint8_t *req_bytes, uint8_t num_bytes, 2079 uint8_t *read_byte, uint8_t read_buf_len, uint8_t delay) 2080{ 2081 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2082 RADEONInfoPtr info = RADEONPTR(output->scrn); 2083 union aux_channel_transaction args; 2084 AtomBiosArgRec data; 2085 unsigned char *space; 2086 unsigned char *base; 2087 int retry_count = 0; 2088 2089 memset(&args, 0, sizeof(args)); 2090 if (info->atomBIOS->fbBase) 2091 base = info->FB + info->atomBIOS->fbBase; 2092 else if (info->atomBIOS->scratchBase) 2093 base = (unsigned char *)info->atomBIOS->scratchBase; 2094 else 2095 return FALSE; 2096 2097retry: 2098 memcpy(base, req_bytes, num_bytes); 2099 2100 args.v1.lpAuxRequest = 0; 2101 args.v1.lpDataOut = 16; 2102 args.v1.ucDataOutLen = 0; 2103 args.v1.ucChannelID = radeon_output->ucI2cId; 2104 args.v1.ucDelay = delay / 10; /* 10 usec */ 2105 if (IS_DCE4_VARIANT) 2106 args.v2.ucHPD_ID = radeon_output->hpd_id; 2107 2108 data.exec.index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 2109 data.exec.dataSpace = (void *)&space; 2110 data.exec.pspace = &args; 2111 2112 RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data); 2113 if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) { 2114 if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10) 2115 goto retry; 2116 ErrorF("failed to get auxch %02x%02x %02x %02x %02x after %d retries\n", 2117 req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], args.v1.ucReplyStatus, retry_count); 2118 return FALSE; 2119 } 2120 if (args.v1.ucDataOutLen && read_byte && read_buf_len) { 2121 if (read_buf_len < args.v1.ucDataOutLen) { 2122 ErrorF("%s: Buffer too small for return answer %d %d\n", __func__, read_buf_len, args.v1.ucDataOutLen); 2123 return FALSE; 2124 } 2125 { 2126 int len = read_buf_len < args.v1.ucDataOutLen ? read_buf_len : args.v1.ucDataOutLen; 2127 memcpy(read_byte, base+16, len); 2128 } 2129 } 2130 return TRUE; 2131} 2132 2133static int 2134RADEONDPEncoderService(xf86OutputPtr output, int action, uint8_t ucconfig, uint8_t lane_num) 2135{ 2136 RADEONInfoPtr info = RADEONPTR(output->scrn); 2137 DP_ENCODER_SERVICE_PARAMETERS args; 2138 AtomBiosArgRec data; 2139 unsigned char *space; 2140 2141 memset(&args, 0, sizeof(args)); 2142 2143 args.ucLinkClock = 0; 2144 args.ucConfig = ucconfig; 2145 args.ucAction = action; 2146 args.ucLaneNum = lane_num; 2147 args.ucStatus = 0; 2148 2149 data.exec.index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 2150 data.exec.dataSpace = (void *)&space; 2151 data.exec.pspace = &args; 2152 2153 RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data); 2154 2155 ErrorF("%s: %d %d\n", __func__, action, args.ucStatus); 2156 return args.ucStatus; 2157} 2158 2159int RADEON_DP_GetSinkType(xf86OutputPtr output) 2160{ 2161 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2162 2163 return RADEONDPEncoderService(output, ATOM_DP_ACTION_GET_SINK_TYPE, radeon_output->ucI2cId, 0); 2164} 2165 2166static Bool atom_dp_aux_native_write(xf86OutputPtr output, uint16_t address, 2167 uint8_t send_bytes, uint8_t *send) 2168{ 2169 uint8_t msg[20]; 2170 uint8_t msg_len, dp_msg_len; 2171 int ret; 2172 2173 dp_msg_len = 4; 2174 msg[0] = address; 2175 msg[1] = address >> 8; 2176 msg[2] = AUX_NATIVE_WRITE << 4; 2177 dp_msg_len += send_bytes; 2178 msg[3] = (dp_msg_len << 4)| (send_bytes - 1); 2179 2180 if (0) 2181 ErrorF("writing %02x %02x %02x, %d, %d\n", msg[0], msg[1], msg[3], send_bytes, dp_msg_len); 2182 if (send_bytes > 16) 2183 return FALSE; 2184 2185 memcpy(&msg[4], send, send_bytes); 2186 msg_len = 4 + send_bytes; 2187 ret = RADEONProcessAuxCH(output, msg, msg_len, NULL, 0, 0); 2188 return ret; 2189} 2190 2191static Bool atom_dp_aux_native_read(xf86OutputPtr output, uint16_t address, 2192 uint8_t delay, 2193 uint8_t expected_bytes, uint8_t *read_p) 2194{ 2195 uint8_t msg[20]; 2196 uint8_t msg_len, dp_msg_len; 2197 int ret; 2198 2199 msg_len = 4; 2200 dp_msg_len = 4; 2201 msg[0] = address; 2202 msg[1] = address >> 8; 2203 msg[2] = AUX_NATIVE_READ << 4; 2204 msg[3] = (dp_msg_len) << 4; 2205 msg[3] |= expected_bytes - 1; 2206 2207 if (0) 2208 ErrorF("reading %02x %02x %02x, %d, %d\n", msg[0], msg[1], msg[3], expected_bytes, dp_msg_len); 2209 ret = RADEONProcessAuxCH(output, msg, msg_len, read_p, expected_bytes, delay); 2210 return ret; 2211} 2212 2213/* fill out the DPCD structure */ 2214void RADEON_DP_GetDPCD(xf86OutputPtr output) 2215{ 2216 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2217 uint8_t msg[25]; 2218 int ret; 2219 2220 ret = atom_dp_aux_native_read(output, DP_DPCD_REV, 0, 8, msg); 2221 if (ret) { 2222 memcpy(radeon_output->dpcd, msg, 8); 2223 if (0) { 2224 int i; 2225 ErrorF("DPCD: "); 2226 for (i = 0; i < 8; i++) 2227 ErrorF("%02x ", radeon_output->dpcd[i]); 2228 ErrorF("\n"); 2229 } 2230 ret = atom_dp_aux_native_read(output, DP_LINK_BW_SET, 0, 2, msg); 2231 if (0) { 2232 ErrorF("0x200: %02x %02x\n", msg[0], msg[1]); 2233 } 2234 return; 2235 } 2236 radeon_output->dpcd[0] = 0; 2237 return; 2238} 2239 2240 2241enum dp_aux_i2c_mode { 2242 dp_aux_i2c_start, 2243 dp_aux_i2c_write, 2244 dp_aux_i2c_read, 2245 dp_aux_i2c_stop, 2246}; 2247 2248 2249static Bool atom_dp_aux_i2c_transaction(xf86OutputPtr output, uint16_t address, 2250 enum dp_aux_i2c_mode mode, 2251 uint8_t write_byte, uint8_t *read_byte) 2252{ 2253 uint8_t msg[8], msg_len, dp_msg_len; 2254 int ret; 2255 int auxch_cmd = 0; 2256 2257 memset(msg, 0, 8); 2258 2259 if (mode != dp_aux_i2c_stop) 2260 auxch_cmd = AUX_I2C_MOT; 2261 2262 if (address & 1) 2263 auxch_cmd |= AUX_I2C_READ; 2264 else 2265 auxch_cmd |= AUX_I2C_WRITE; 2266 2267 msg[2] = auxch_cmd << 4; 2268 2269 msg[4] = 0; 2270 msg[0] = (address >> 1); 2271 msg[1] = (address >> 9); 2272 2273 msg_len = 4; 2274 dp_msg_len = 3; 2275 switch (mode) { 2276 case dp_aux_i2c_read: 2277 /* bottom bits is byte count - 1 so for 1 byte == 0 */ 2278 dp_msg_len += 1; 2279 break; 2280 case dp_aux_i2c_write: 2281 dp_msg_len += 2; 2282 msg[4] = write_byte; 2283 msg_len++; 2284 break; 2285 default: 2286 break; 2287 } 2288 msg[3] = dp_msg_len << 4; 2289 2290 ret = RADEONProcessAuxCH(output, msg, msg_len, read_byte, 1, 0); 2291 return ret; 2292} 2293 2294static Bool 2295atom_dp_i2c_address(I2CDevPtr dev, I2CSlaveAddr addr) 2296{ 2297 I2CBusPtr bus = dev->pI2CBus; 2298 xf86OutputPtr output = bus->DriverPrivate.ptr; 2299 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2300 int ret; 2301 2302 radeon_output->dp_i2c_addr = addr; 2303 radeon_output->dp_i2c_running = TRUE; 2304 2305 /* call i2c start */ 2306 ret = atom_dp_aux_i2c_transaction(output, radeon_output->dp_i2c_addr, 2307 dp_aux_i2c_start, 0, NULL); 2308 2309 return ret; 2310} 2311static Bool 2312atom_dp_i2c_start(I2CBusPtr bus, int timeout) 2313{ 2314 ErrorF("%s\n", __func__); 2315 return TRUE; 2316} 2317 2318static void 2319atom_dp_i2c_stop(I2CDevPtr dev) 2320{ 2321 I2CBusPtr bus = dev->pI2CBus; 2322 xf86OutputPtr output = bus->DriverPrivate.ptr; 2323 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2324 2325 if (radeon_output->dp_i2c_running) 2326 atom_dp_aux_i2c_transaction(output, radeon_output->dp_i2c_addr, 2327 dp_aux_i2c_stop, 0, NULL); 2328 radeon_output->dp_i2c_running = FALSE; 2329} 2330 2331 2332static Bool 2333atom_dp_i2c_put_byte(I2CDevPtr dev, I2CByte byte) 2334{ 2335 I2CBusPtr bus = dev->pI2CBus; 2336 xf86OutputPtr output = bus->DriverPrivate.ptr; 2337 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2338 Bool ret; 2339 2340 ret = (atom_dp_aux_i2c_transaction(output, radeon_output->dp_i2c_addr, 2341 dp_aux_i2c_write, byte, NULL)); 2342 return ret; 2343} 2344 2345static Bool 2346atom_dp_i2c_get_byte(I2CDevPtr dev, I2CByte *byte_ret, Bool last) 2347{ 2348 I2CBusPtr bus = dev->pI2CBus; 2349 xf86OutputPtr output = bus->DriverPrivate.ptr; 2350 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2351 Bool ret; 2352 2353 ret = (atom_dp_aux_i2c_transaction(output, radeon_output->dp_i2c_addr, 2354 dp_aux_i2c_read, 0, byte_ret)); 2355 return ret; 2356} 2357 2358Bool 2359RADEON_DP_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, char *name, xf86OutputPtr output) 2360{ 2361 I2CBusPtr pI2CBus; 2362 2363 pI2CBus = xf86CreateI2CBusRec(); 2364 if (!pI2CBus) return FALSE; 2365 2366 pI2CBus->BusName = name; 2367 pI2CBus->scrnIndex = pScrn->scrnIndex; 2368 pI2CBus->I2CGetByte = atom_dp_i2c_get_byte; 2369 pI2CBus->I2CPutByte = atom_dp_i2c_put_byte; 2370 pI2CBus->I2CAddress = atom_dp_i2c_address; 2371 pI2CBus->I2CStart = atom_dp_i2c_start; 2372 pI2CBus->I2CStop = atom_dp_i2c_stop; 2373 pI2CBus->DriverPrivate.ptr = output; 2374 2375 /* 2376 * These were set incorrectly in the server pre-1.3, Having 2377 * duplicate settings is sub-optimal, but this lets the driver 2378 * work with older servers 2379 */ 2380 pI2CBus->ByteTimeout = 2200; /* VESA DDC spec 3 p. 43 (+10 %) */ 2381 pI2CBus->StartTimeout = 550; 2382 pI2CBus->BitTimeout = 40; 2383 pI2CBus->AcknTimeout = 40; 2384 pI2CBus->RiseFallTime = 20; 2385 2386 if (!xf86I2CBusInit(pI2CBus)) 2387 return FALSE; 2388 2389 *bus_ptr = pI2CBus; 2390 return TRUE; 2391} 2392 2393 2394static uint8_t dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], int r) 2395{ 2396 return link_status[r - DP_LANE0_1_STATUS]; 2397} 2398 2399static uint8_t dp_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane) 2400{ 2401 int i = DP_LANE0_1_STATUS + (lane >> 1); 2402 int s = (lane & 1) * 4; 2403 uint8_t l = dp_link_status(link_status, i); 2404 return (l >> s) & 0xf; 2405} 2406 2407static Bool dp_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 2408{ 2409 int lane; 2410 2411 uint8_t lane_status; 2412 2413 for (lane = 0; lane < lane_count; lane++) { 2414 lane_status = dp_get_lane_status(link_status, lane); 2415 if ((lane_status & DP_LANE_CR_DONE) == 0) 2416 return FALSE; 2417 } 2418 return TRUE; 2419} 2420 2421 2422/* Check to see if channel eq is done on all channels */ 2423#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 2424 DP_LANE_CHANNEL_EQ_DONE|\ 2425 DP_LANE_SYMBOL_LOCKED) 2426static Bool 2427dp_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 2428{ 2429 uint8_t lane_align; 2430 uint8_t lane_status; 2431 int lane; 2432 2433 lane_align = dp_link_status(link_status, 2434 DP_LANE_ALIGN_STATUS_UPDATED); 2435 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 2436 return FALSE; 2437 for (lane = 0; lane < lane_count; lane++) { 2438 lane_status = dp_get_lane_status(link_status, lane); 2439 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 2440 return FALSE; 2441 } 2442 return TRUE; 2443} 2444 2445/* 2446 * Fetch AUX CH registers 0x202 - 0x207 which contain 2447 * link status information 2448 */ 2449static Bool 2450atom_dp_get_link_status(xf86OutputPtr output, 2451 uint8_t link_status[DP_LINK_STATUS_SIZE]) 2452{ 2453 ScrnInfoPtr pScrn = output->scrn; 2454 int ret; 2455 ret = atom_dp_aux_native_read(output, DP_LANE0_1_STATUS, 100, 2456 DP_LINK_STATUS_SIZE, link_status); 2457 if (!ret) { 2458 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "dp link status failed\n"); 2459 return FALSE; 2460 } 2461 ErrorF("link status %02x %02x %02x %02x %02x %02x\n", link_status[0], link_status[1], 2462 link_status[2], link_status[3], link_status[4], link_status[5]); 2463 2464 return TRUE; 2465} 2466 2467static uint8_t 2468dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 2469 int lane) 2470 2471{ 2472 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 2473 int s = ((lane & 1) ? 2474 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 2475 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 2476 uint8_t l = dp_link_status(link_status, i); 2477 2478 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 2479} 2480 2481static uint8_t 2482dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 2483 int lane) 2484{ 2485 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 2486 int s = ((lane & 1) ? 2487 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 2488 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 2489 uint8_t l = dp_link_status(link_status, i); 2490 2491 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 2492} 2493 2494static char *voltage_names[] = { 2495 "0.4V", "0.6V", "0.8V", "1.2V" 2496}; 2497static char *pre_emph_names[] = { 2498 "0dB", "3.5dB", "6dB", "9.5dB" 2499}; 2500 2501/* 2502 * These are source-specific values; current Intel hardware supports 2503 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 2504 */ 2505#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 2506 2507static uint8_t 2508dp_pre_emphasis_max(uint8_t voltage_swing) 2509{ 2510 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2511 case DP_TRAIN_VOLTAGE_SWING_400: 2512 return DP_TRAIN_PRE_EMPHASIS_6; 2513 case DP_TRAIN_VOLTAGE_SWING_600: 2514 return DP_TRAIN_PRE_EMPHASIS_6; 2515 case DP_TRAIN_VOLTAGE_SWING_800: 2516 return DP_TRAIN_PRE_EMPHASIS_3_5; 2517 case DP_TRAIN_VOLTAGE_SWING_1200: 2518 default: 2519 return DP_TRAIN_PRE_EMPHASIS_0; 2520 } 2521} 2522 2523static void dp_set_training(xf86OutputPtr output, uint8_t training) 2524{ 2525 atom_dp_aux_native_write(output, DP_TRAINING_PATTERN_SET, 1, &training); 2526} 2527 2528static void dp_set_power(xf86OutputPtr output, uint8_t power_state) 2529{ 2530 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2531 2532 if (radeon_output->dpcd[0] >= 0x11) { 2533 atom_dp_aux_native_write(output, 0x600, 1, &power_state); 2534 } 2535} 2536 2537static void 2538dp_get_adjust_train(xf86OutputPtr output, 2539 uint8_t link_status[DP_LINK_STATUS_SIZE], 2540 int lane_count, 2541 uint8_t train_set[4]) 2542{ 2543 ScrnInfoPtr pScrn = output->scrn; 2544 uint8_t v = 0; 2545 uint8_t p = 0; 2546 int lane; 2547 2548 for (lane = 0; lane < lane_count; lane++) { 2549 uint8_t this_v = dp_get_adjust_request_voltage(link_status, lane); 2550 uint8_t this_p = dp_get_adjust_request_pre_emphasis(link_status, lane); 2551 2552 if (0) { 2553 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2554 "requested signal parameters: lane %d voltage %s pre_emph %s\n", 2555 lane, 2556 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 2557 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 2558 } 2559 if (this_v > v) 2560 v = this_v; 2561 if (this_p > p) 2562 p = this_p; 2563 } 2564 2565 if (v >= DP_VOLTAGE_MAX) 2566 v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 2567 2568 if (p >= dp_pre_emphasis_max(v)) 2569 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2570 2571 if (0) { 2572 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2573 "using signal parameters: voltage %s pre_emph %s\n", 2574 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 2575 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 2576 } 2577 for (lane = 0; lane < 4; lane++) 2578 train_set[lane] = v | p; 2579} 2580 2581static int radeon_dp_max_lane_count(xf86OutputPtr output) 2582{ 2583 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2584 int max_lane_count = 4; 2585 2586 if (radeon_output->dpcd[0] >= 0x11) { 2587 max_lane_count = radeon_output->dpcd[2] & 0x1f; 2588 switch(max_lane_count) { 2589 case 1: case 2: case 4: 2590 break; 2591 default: 2592 max_lane_count = 4; 2593 } 2594 } 2595 return max_lane_count; 2596} 2597 2598Bool radeon_dp_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode) 2599{ 2600 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2601 int clock = adjusted_mode->Clock; 2602 2603 radeon_output->dp_lane_count = dp_lanes_for_mode_clock(output, clock); 2604 radeon_output->dp_clock = dp_link_clock_for_mode_clock(output, clock); 2605 if (!radeon_output->dp_lane_count || !radeon_output->dp_clock) 2606 return FALSE; 2607 return TRUE; 2608} 2609 2610static void dp_update_dpvs_emph(xf86OutputPtr output, uint8_t train_set[4]) 2611{ 2612 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2613 int i; 2614 for (i = 0; i < radeon_output->dp_lane_count; i++) 2615 atombios_output_dig_transmitter_setup(output, ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, i, train_set[i]); 2616 2617 atom_dp_aux_native_write(output, DP_TRAINING_LANE0_SET, radeon_output->dp_lane_count, train_set); 2618} 2619 2620static void do_displayport_link_train(xf86OutputPtr output) 2621{ 2622 ScrnInfoPtr pScrn = output->scrn; 2623 RADEONInfoPtr info = RADEONPTR(pScrn); 2624 RADEONOutputPrivatePtr radeon_output = output->driver_private; 2625 int enc_id = atom_dp_get_encoder_id(output); 2626 Bool clock_recovery; 2627 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2628 uint8_t tries, voltage, ss_cntl; 2629 uint8_t train_set[4]; 2630 int i; 2631 Bool channel_eq; 2632 uint8_t dp_link_configuration[DP_LINK_CONFIGURATION_SIZE]; 2633 2634 memset(train_set, 0, 4); 2635 2636 /* set up link configuration */ 2637 memset(dp_link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 2638 2639 if (radeon_output->dp_clock == 27000) 2640 dp_link_configuration[0] = DP_LINK_BW_2_7; 2641 else 2642 dp_link_configuration[0] = DP_LINK_BW_1_62; 2643 dp_link_configuration[1] = radeon_output->dp_lane_count; 2644 2645 if (radeon_output->dpcd[0] >= 0x11) { 2646 dp_link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2647 } 2648 2649 /* power up to D0 */ 2650 dp_set_power(output, DP_SET_POWER_D0); 2651 2652 /* disable training */ 2653 dp_set_training(output, DP_TRAINING_PATTERN_DISABLE); 2654 2655 /* write link rate / num / eh framing */ 2656 atom_dp_aux_native_write(output, DP_LINK_BW_SET, 2, 2657 dp_link_configuration); 2658 2659 /* write ss cntl */ 2660 ss_cntl = 0; 2661 atom_dp_aux_native_write(output, DP_DOWNSPREAD_CTRL, 1, 2662 &ss_cntl); 2663 2664 /* start local training start */ 2665 if (IS_DCE4_VARIANT) { 2666 atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START); 2667 atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1); 2668 } else { 2669 RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_START, enc_id, 0); 2670 RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, enc_id, 0); 2671 } 2672 2673 usleep(400); 2674 dp_set_training(output, DP_TRAINING_PATTERN_1); 2675 dp_update_dpvs_emph(output, train_set); 2676 2677 /* loop around doing configuration reads and DP encoder setups */ 2678 clock_recovery = FALSE; 2679 tries = 0; 2680 voltage = 0xff; 2681 for (;;) { 2682 usleep(100); 2683 if (!atom_dp_get_link_status(output, link_status)) 2684 break; 2685 2686 if (dp_clock_recovery_ok(link_status, radeon_output->dp_lane_count)) { 2687 clock_recovery = TRUE; 2688 break; 2689 } 2690 2691 for (i = 0; i < radeon_output->dp_lane_count; i++) 2692 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 2693 break; 2694 if (i == radeon_output->dp_lane_count) { 2695 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2696 "clock recovery reached max voltage\n"); 2697 break; 2698 } 2699 2700 /* Check to see if we've tried the same voltage 5 times */ 2701 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 2702 ++tries; 2703 if (tries == 5) { 2704 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2705 "clock recovery tried 5 times\n"); 2706 break; 2707 } 2708 } else 2709 tries = 0; 2710 2711 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 2712 2713 dp_get_adjust_train(output, link_status, radeon_output->dp_lane_count, train_set); 2714 dp_update_dpvs_emph(output, train_set); 2715 2716 } 2717 2718 if (!clock_recovery) 2719 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2720 "clock recovery failed\n"); 2721 2722 /* channel equalization */ 2723 tries = 0; 2724 channel_eq = FALSE; 2725 dp_set_training(output, DP_TRAINING_PATTERN_2); 2726 if (IS_DCE4_VARIANT) 2727 atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2); 2728 else 2729 RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, enc_id, 1); 2730 2731 for (;;) { 2732 usleep(400); 2733 if (!atom_dp_get_link_status(output, link_status)) 2734 break; 2735 2736 if (dp_channel_eq_ok(link_status, radeon_output->dp_lane_count)) { 2737 channel_eq = TRUE; 2738 break; 2739 } 2740 2741 /* Try 5 times */ 2742 if (tries > 5) { 2743 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2744 "channel eq failed: 5 tries\n"); 2745 break; 2746 } 2747 2748 /* Compute new train_set as requested by target */ 2749 dp_get_adjust_train(output, link_status, radeon_output->dp_lane_count, train_set); 2750 dp_update_dpvs_emph(output, train_set); 2751 2752 ++tries; 2753 } 2754 2755 if (!channel_eq) 2756 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2757 "channel eq failed\n"); 2758 2759 dp_set_training(output, DP_TRAINING_PATTERN_DISABLE); 2760 if (IS_DCE4_VARIANT) 2761 atombios_output_dig_encoder_setup(output, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE); 2762 else 2763 RADEONDPEncoderService(output, ATOM_DP_ACTION_TRAINING_COMPLETE, enc_id, 0); 2764 2765} 2766 2767